SU1068712A1 - Device for registering single electric pulses - Google Patents

Abstract

A DEVICE FOR REGISTRATION OF SINGLE ELECTRIC PULSES containing an amplifier whose input is the device input, an analog digital converter whose input is connected to the amplifier output, a memory block whose information inputs are connected to the outputs of the analog digital converter, the first counter, the outputs of which are connected to the address of the amplifier the memory block inputs, the first trigger, the output of which is connected to the block write enable input, the second counter, the output of which is connected to the installation input of the first zero the second trigger, the first element I, the first input of which is connected to the output of the second trigger, the comparison element, whose inputs of the first group are K, the control inputs of the device, the clock generator, the output of which is connected to the second input of the first element I, Understanding that, in order to increase the reliability of pulse registration by increasing noise immunity, it contains the first and second threshold elements whose inputs are connected to the amplifier output, the second and third elements AND, the first inputs of which x connected to the outputs of the first and second threshold elements, respectively, the element NOT, the input of which is connected to the output of the second threshold element and the second input of the second element AND, the delay element whose input is connected to the output of the element NO, the first element OR, the first input of which is connected to the output the delay element, the third, the counter and the trigger, the inputs of the zero setting are connected to the output of the first element OR, and the installation input of the unit of the third trigger and the counting input of the third counter are connected to the outputs of the second and t Third element AND respectively, the outputs of the third counter are connected g to the inputs of the second group of an element of comparison - (L neni, the fourth element of AND, the first, second and third, whose inputs are connected to the outputs of the element NOT, the comparison element and the third trigger, respectively, and the output is connected to the input of the unit installation of the second trigger, the second element OR, the left input of which is connected to the output of the second counter / second input of the second element OR, the second input of the first element OR, the installation input of the unit of the first trigger and the installation input Via the second counter, the switching element is connected to the common bus of the device, the output of the second element OR is connected to the input of the second zero trigger device, the first input of the first AND element is connected to the second trigger output, and the output is connected to the counting input of the second counter, clock pulse generator output connected to the clocking inputs of the analog-digital converter and the memory unit, the input of the first counter and the second input of the third element AND, the outputs of the memory unit are the device outputs.

Description

The invention relates to automation and computing and can be used in measuring and controlling devices, automatic control devices, as well as in information systems for collecting and processing data. A device for detecting an electrical pulse, containing the amplification unit, the frequency modulator, the mixing unit, the recording head, the comparison, subtraction, addition, counter, decoder, reproducible signal amplification unit, filters and amplitude detectors, At the time the threshold pulses are exceeded (usually 0.1 A, where A is the amplitude), the device generates a signal to start recording the pulse into the memory on the magnetic carrier l. However, this method is unacceptable for signals of complex shape, since it can lead to a false triggering of the system and, therefore, to a reduction in its noise immunity. Increasing the trigger threshold, in order to increase noise immunity, leads to a sharp decrease in the accuracy of determining the moment of the pulse beginning. The closest to the technical essence of the proposed device for registering single electric pulses is a device for storing and repeated reproduction of electric pulses, containing an amplifier whose input is an input of the device, an analog-digital converter whose input is connected to the output of the amplifier, a memory block, information the inputs of which are connected to the outputs of the analog-digital converter-atel, the first counter, the outputs of which are connected to the address inputs of the memory block, is the first trigger, the output of which is connected to the write enable input of the memory block, the second counter, the output of which is connected to the input of the zero setting of the first trigger, the second trigger, the first element I, the first input of which is connected to the output of the second trigger, the comparison element whose inputs of the first group are The control inputs of the device, a clock generator, the output of which is connected to the second input of the first element AND 2. However, in the device for storing and repeated reproduction of pulses, They calculate the moment when the derivative of the pulse exceeds the specified threshold level and continue to record for two pulse durations. This does not allow to accurately determine the beginning of a pulse with a gentle front and vice versa, the disturbance having a steep front is registered as a pulse, as a result of which the reliability of recording information decreases. The purpose of the invention is to increase the reliability of pulse registration by increasing noise immunity. The goal is achieved in that a device for recording single electrical pulses, containing an amplifier whose input is an input of the device, an analog-to-digital converter whose input is connected to the output of the amplifier, a memory unit whose information inputs are connected to the outputs of an analog-digital converter the first counter, the outputs of which are connected to the address inputs of the memory unit, the first trigger, the output of which is connected to the write enable input of the memory block, the second counter, the output of which is connected to the input For setting the zero of the first trigger, the second trigger, the first element And, the first input of which is connected to the output of the second trigger, the comparison element, the inputs of the first group of which are the control inputs of the device, the clock generator, the output of which is connected to the second input of the first element And, contains the first and second threshold elements, the inputs of which are connected to the output of the amplifier, the second and third elements AND, the first inputs of which are connected to the outputs of the first and second threshold elements, respectively, the element is NOT input d which is connected to the output of the second threshold element and the second input of the second element I, the delay element whose input is connected to the output of the element NOT, the first element OR whose first input is connected to the output is the delay element, the third counter and trigger, the setting inputs zero connected to the output of the first element OR, and the installation input of the unit of the third trigger and the counting input of the third counter are connected to the outputs of the second and third elements AND, respectively, the outputs of the third counter are connected to the inputs of the second group Comparison element, the fourth element is AND, the first, second and third inputs of which are connected to the outputs of the element NO, the element of comparison and the third trigger, respectively, and the output is connected to the installation input of the unit of the second trigger, the second element is OR, the first input of which is connected to the output of the second counter , the second input of the second element OR, the second input of the first element OR, the installation input of the unit of the first trigger and the installation input of the second counter through the switching element connected to the common bus device, the output of the second element LI is connected to the input of the zero setting of the second trigger, the first input of the first element I is connected to the output of the second trigger, -a output - to the counting input of the second counter, the output of the clock generator is connected to the clock inputs of the analog and digital converter and the memory block to the input of the first the counter and the second input of the third element AND, the outputs of the memory block are the outputs of the device. FIG. 1 shows a block diagram of the device; FIG. 2 shows time diagrams of the device operation; in fig. 3 - order of filling the memory block. The device contains an amplifier 1, whose input is an input of the device, analog-digital converter 2, memory block 3, first counter 4, first trigger 5, second counter b, second trigger 7, first element 8, comparison element 9, inputs first the groups of which are the control inputs of the device, the generator of 10 clock pulses, the first 11 and second 12 threshold elements, the second 13 and third 14 elements, the element. NOT 15, the delay element 16, the first element OR 17, the third counter 18, the third trigger 19, the fourth element AND 20, the second element OR 21, the outputs of the memory block are the device outputs, the second input of the second element OR 21, the second the input of the first element OR 17, the installation input of the unit of the first trigger 5 and the installation input of the second counter 6 through the switching element are connected to the common bus of the device. The device operates as follows. When the switching element is opened (the START button), the first trigger 5 is set to one, which corresponds to the write mode in memory block 3, and the second and third triggers 7 and 19 and the second and third counters 6 and 18 are reset. to zero through the first and second elements OR 17 and 21, respectively. The input analog signal from amplifier 1 is fed to the input of analog-digital converter 2. With the arrival of the next clock pulse from generator 10, analog-to-digital converter 2 starts converting the analog signal to digital form. At the same time, the contents of the first counter 4 is increased by one (by a signal from the generator 10). At the end of the clock pulse, the digital code from analog-to-digital converter 2 is copied to memory block 3 at the address determined by the first counter 4. Simultaneously, the angular input signal is compared with the peak level (first threshold element 11) and its duration is measured. The measurement of the duration is as follows. If the input signal has exceeded the threshold level (for example, 0.01 A, where A is the amplitude), then from the output of the second threshold element 12, the level of the logical unit is opened, which opens the AND 14 element and permits the passage of generator 10 pulses to the counting input of the third counter 18, the contents which is increased by a unit every time with the arrival of a clock pulse and is the duration of the input signal at a level of 0.01 A. In the case of a reverse transition of the threshold level, the element 14 is closed, and the positive voltage drop with the output and the element 15 through the delay element 16 and the element OR 17 is fed to the reset input of the counter 18 and trigger 19, which are set to zero so that when the threshold level of the signals is newly crossed, to begin measuring its duration and analysis for reaching the peak level. It should be noted that the generation of a signal that the peak level is exceeded is permitted only during the duration measurement period. These actions are repeated until the comparison element 9 signals the signal that the code of the analog signal is greater than or equal to the value given to the control inputs of the device, if, moreover, the peak level is exceeded by the third trigger 19, with the arrival of the measurement end signal supplied from the NOT 15 element, the AND 20 element will open, which will transfer the second trigger 7 to the one state, which in turn will allow the passage of the clock pulses of the generator 10 to the counting input the second counter 6 through the element And 8. With the arrival of each clock pulse, the counter 6 increases the content by one. The counter has such a number of binary bits, which determines the number of samples recorded by the device after the pulse expires, after m cycles, it generates an overflow signal, which pushes the first trigger 5 into the zero state, which sets the read mode of the memory block 3. The device ends the registration of the analog signal and proceeds to display its digital equivalent. It should be noted that the delay element 16 is needed to eliminate the situation where, by the end of measurement signal, the third counter 18 and the third trigger 19 are reset before element 20 I opens.

It should also be noted that the number of states of the first counter 4, like the number of cells of the memory block 3, is equal to and is chosen so as to place the f points of prehistory at the points of the impulse and m points of response, i.e. n 1 + 4 m:

The third counter 18 has N states, the number of which is determined by the maximum possible duration of the input pulse, expressed in generator 10 cycles, i.e.

m - max

g 0

Gd & i f f - maximum possible pulse duration; tp is the sampling step. Let the voltage of a complex shape enter the recorder input (Fig. 2a). The duration of the pulsations, measured at a level of respectively

 (one)

2

(2) 4 -t6-tjr; (3)

In the first case, the information is considered false, even if min (where EL is the minimum expected value of the voltage duration), since the pulsation did not exceed the peak level (A n).

In the second case, the impulse is also not recorded, as is the duration. The fact of the presence of a pulse in memory block 3 is detected at time t /, since the conditions eiin

Ht).

Then, the system enters the pulse aftertreatment mode (interval t ty-tg), and then stops recording the input voltage.

The corresponding timing diagrams of the device operation are shown in FIG. 2, b.

It should be noted that the memory size is chosen so as to accommodate not only the impulse and its aftereffect, but also the prehistory (for example, during Tj -tj-t). Recall once again that the information in the memory is written cyclically. This makes it possible to begin displaying a signal with its history, starting with the address of the cell in which the signal value is registered during the last moment of the response. Indeed, suppose that as a result of multiple cyclic memory filling with a volume of m points (the k-bit binary number is implied), the signal value at the last moment of the response was recorded in the cell (), then the pulse response, pulse and its history are located at addresses

p, G1 - T ;, 2, -J, o, t, gp-1, ...,, ntl, and at the (n + 1) address, the signal value is recorded at the first moment of the prehistory.

FIG. 3 illustrates the process of filling the memory. The arrow indicates the direction of filling and reading.

Thus, the proposed device allows to increase the reliability of registration of pulses of any complex shape, the power of which is greater than the interference power, and for the normal operation of the device, no additional signal is required that synchronizes the beginning of the pulse. The known methods and devices solve this problem insufficiently, as they try to determine the beginning of the impulse in various ways without having a priori information about it, which is quite difficult and can lead, as we have seen, to a loss of signal in general. Thus, it was possible to get a significant gain in accuracy (the threshold can be set arbitrarily small) and reliability.

The invention greatly expands the class of recorded pulses compared to the known one, which determines the practical value of the invention.

Output Fig

5J (Score.

Gipg

eleven

Jljslj

fig 2

I

Phi 3

Claims (1)

DEVICE FOR REGISTRATION OF ONE-TIME ELECTRIC PULSE, containing an amplifier, the input of which is the input of a device, an analog to digital converter, the input of which is connected to the output of the amplifier, a memory unit, the information inputs of which are connected to the outputs of the analog digital converter, the first counter, the outputs of which are connected to the address inputs of the unit memory, the first trigger, the output of which is connected to the recording permission input of the memory block, the second counter, the output of which is connected to the zero-setting input of the first trigger Era, the second trigger, the first element And, the first input of which is connected to the output of the second trigger, the comparison element, the inputs of the first group of which are the control inputs of the device, a clock generator, the output of which is connected to the second input of the first element And, resulting in that , in order to improve the reliability of pulse registration by increasing noise immunity, it contains the first and second threshold elements, the inputs of which are connected to the output of the amplifier, the second and third elements And, the first inputs of which are connected are connected to the input of the second AND element, the delay, whose input is the sub-output of the element NOT, the first OR, the first input of which is the outputs of the first and second threshold elements, respectively, the element is NOT, the input of which is connected to the output of the second threshold element and the second element is connected to the element is connected to the output of the element delays, third. counter and trigger, the zero setting inputs of which are connected to the output of the first OR element, and the unit setting input of the third trigger and the counting input of the third counter are connected to the outputs of the second and third elements accordingly, the outputs of the third counter are connected § to the inputs of the second group of the comparison element, the fourth element AND, the first, second and third, the inputs of which are connected to the outputs of the element NOT, the comparison element and the third trigger, respectively, and the output is connected to the installation input of the unit of the second trigger, the second OR element, the first input of which is connected to the output of the second OR element, the input of the unit of the first trigger and the zero of the second counter via the switching element are connected to the device’s common bus, the output is second of the first OR element is connected to the zero setting input of the second trigger, the first input of the first AND element is connected to the output of the second trigger, and the output to the counting input of the second counter, the output of the clock generator is connected to the clock inputs of the analog-to-digital converter and the memory unit, the input of the first counter and the second input of the third element AND, the outputs of the memory block are the outputs of the device.