SU792291A1

SU792291A1 - Shift register monitoring device

Info

Publication number: SU792291A1
Application number: SU782699918A
Authority: SU
Inventors: Владимир Андреевич Исаенко; Вадим Анатольевич Калиничев; Владимир Моисеевич Тафель
Original assignee: Предприятие П/Я В-8751
Priority date: 1978-12-21
Filing date: 1978-12-21
Publication date: 1980-12-30

Description

II

Изобретение относитс к запоминающим устройствам.This invention relates to memory devices.

Известны устройства дл контрол регистра сдвига 1, 2.Devices are known for controlling the shift register 1, 2.

Одно из известных устройств реализует оперативный контроль регистра сдвига и со держит аналоговые функциональные элементы 1 ,One of the known devices implements an on-line control of the shift register and contains analog functional elements 1,

К недостаткам этого устройства относ тс низкое быстродействие и недостаточна над,ежность .The disadvantages of this device are low speed and insufficient over frequency.

Из известных устройств наиболее близким к изобретению вл етс устройство дл контрол регистра сдвига, содержащее схему сравне1да , выход которой подключен к одному из входов элемента И, другой вход которого соединен с одним из входов устройства, а выход элемента И служит выходом устройства 2.Of the known devices, the closest to the invention is a device for controlling the shift register, which contains a comparable circuit, the output of which is connected to one of the inputs of the And element, the other input of which is connected to one of the inputs of the device, and the output of the And element serves as an output of the device 2.

Р1едостаток этого устройства состоит в применении в нем элементов задержки, что снижает его быстродействие.The disadvantage of this device is the use of delay elements in it, which reduces its speed.

Цель изобрете1га - повышение быстродействи устройства.The purpose of the invention is to increase the speed of the device.

Поставленна цель достигаетс тем, что устройство содержит счетчики и дополнительные элементы И, выходы которых подключены к первым входам счетчиков, выходы которых соединены со входами схемы сравнени , входы дополнительных элементов И и вторые входы счетчиков подключены к другим входам устройства.The goal is achieved by the fact that the device contains counters and additional elements AND, the outputs of which are connected to the first inputs of the meters, the outputs of which are connected to the inputs of the comparison circuit, the inputs of additional elements AND and the second inputs of the meters are connected to other inputs of the device.

На чертеже изображена блок-схема устройства .The drawing shows a block diagram of the device.

Устройство содержит схему 1 сравнени , первый 2 и второй 3 счетчики, элемент И 4, первый 5 и второй 6 дополнительные элементы И, щину 7 выходных сигналов, шины The device contains a comparison circuit 1, the first 2 and second 3 counters, the element 4, the first 5 and the second 6 additional elements, the bus 7 output signals, tires

15 8 входных сигналов и шины 9 тактовых сигналов , входы 10-13 устройства и выход 14 устройства.15 8 input signals and bus 9 clock signals, device inputs 10-13 and device output 14.

Выход схемы 1 сравнени подключен к одному из входов элемента И 4, другой вход The output of the comparison circuit 1 is connected to one of the inputs of the element 4, the other input

Claims

20 which is connected to the input 13 of the device. The output of the AND 4 item is the output 14 of the device. The outputs of the additional elements And 5 and 6 are connected to the first inputs 3 of counters 2 and 3, the outputs of which are connected to the inputs of the comparison circuit 1. The first inputs of the additional elements I 5 and., 6. Are connected respectively to the bus 8 input signals and bus 7 output signals, the second inputs to the bus 9 clock signals, and the third inputs to the input 10 of the mouth}. The second inputs of counters 2 and 3 are connected respectively to the inputs 1 and 12 of the device. The inputs of the controlled shift register 15 are connected to the buses 8 and 9 of the device, and the output to the bus 7 of the output signal. The device works as follows. In the Record mode, the input information received via bus 8 to the information input of the shift register 15 is sequentially entered into the controlled shift register 15 by the clock signals applied via the bus 91 act signals. At the same time, a single mode identification signal is written over bus 10 to the input of the first additional element 5, to the other inputs of which information and clock signals are transmitted. Due to this, the clock signals (sync signals) arriving at moments of a single level on the bus 8 of the input signal come from the output of the first additional element AND 5 to the counting input of the first counter 2. Counter 2, which was zeroed before the write cycle by a signal from input 11 reset), calculates the sum modulo m (t - counter capacity 2). the number of units recorded in the controlled shift register in Record mode. In the Playback mode, recirculation (cyclic shift to the left or right) of the information word recorded in the shift register 15 in Record mode is performed. The recirculation cycles can be performed m} 1 time, and in each cycle a clock signal packet arrives at the spike of 9 clock signals whose code is equal to the length of the shift register 15. The zero identification signal of the Replay mode arriving at input 10 (mode bus) to the third (inverse) input of the second additional element And 6, allows the second counter to count 3 numbers of units produced at the output of the shift register 15. Before each recycling count, counter 3 is nullified by a signal from input 12 of the device (from the second reset bus), so that by the end of the cycle in counter 3, store the modulo m sum (counter 3 capacity also equals t) the number of units in the word reproduced in this cycle. The inputs of counters 2 and 3 are connected to the inputs of comparison circuit 1, at the output of which there is an inversion of the comparison result of codes stored in 2 and 3. After each recirculation cycle, input 13 (the alarm polling bus) receives a second input of the And 4 element if the output of the comparison circuit 1 to the first input of the AND 4 element is received by a non-comparison signal, then from the output of the AND 4 element to the output 14 of the device an alarm signal is given. If the codes stored in counters 2 and 3 are equal, the alarm signal is not generated. The proposed device allows controlling the correctness of the reproduction of the information recorded in the shift register 15. The reliability of the control at a sufficiently large value of m is very high: almost already at m 8, the probability of not detecting any multiple failures is negligible for registers of arbitrary length. In any case, m lognN, where N is the length of the monitored shift register, the technical and economic advantage of the device described is to increase speed by synchronously performing the shifts and the control account, as well as high reliability of the control. An apparatus for controlling a shift register, comprising a comparison circuit, the output of which is connected to one of the inputs of the AND element, the other input of which is connected to one of the inputs of the device, and the output of the AND element is the output of the device, characterized in that, to speed up devices, it contains counters and additional elements And, the outputs of which are connected to the first inputs of the counters, the outputs of which are connected to the inputs of the comparison circuit, the inputs of additional elements And and the second inputs of the connection counters cheny other input device. Sources of information taken into account in the examination 1..The author's certificate of the USSR №399862, cl. G 06 F 11/02, 1971.

2. USSR author's certificate No. 529488, cl. G-11 C 29/00, q 06 F 11/00, 1975 (prototype).