SU624235A1 - Arrangement for moving averaging electric signals - Google Patents

Description

The invention relates to digital. about the processing of electronic signals and can be used in various computing devices, including automatic hymeromeorological stations and measuring devices. It is known a sliding averaging device consisting of a non-periodic signal converter, a shift register and a reversible counter. In this device, the shift register has a significant capacitance, which is determined by the maximum value of the measured frequency at the input. The closest to the invention according to the technical solution is a device for sliding averaging of the electric signal, comprising a pulse generator aHaHor 4acTOTaj, a counter, each bit of which is connected to the first inputs of the elements AND, the second inputs of which are connected to the first output of the generator, shifting the registers each counter and read block. However, it has a large number of episodes, caused by the significant redundancy of the recorded information and arithmetic operations required by the CPU to calculate the averaged values of the measured value over the entire averaging period. The aim of the invention is to reduce the equipment of a device for sliding averaging of electrical signals. In the proposed device, this is achieved by introducing a synchronization unit, an inverter, additional AND elements, OR elements and a display unit, with one input of the synchronization unit connected to the analog-frequency converter output, the other input to the first output of the pulse generator, and the output of the synchronization unit — with the counting input of the counter, the clock inputs of the shift registers and the unloading of the input block – reader are connected to the second output of the pulse generator, the outputs of the shift registers are connected to the information input I give the read unit and to first inputs of respective further epementov And, the outputs of which are connected to

the first gateways of the OR elements, the second gateways of which are connected with the output of the elements of AND, the second inputs of the additional elements of AND are connected to the clock input of the readout unit and connected to the output of the inverter, which is connected to the first output of the ator gene and installed About the counter , and the output of the readout unit is connected to the input unit of the input unit.

The drawing shows a schematic of a prescriptive device.

It contains a converter 1 anaaaaaaaaaaaaaaaa, a synchronization unit 2, a generator of 3 pulses, a counter 4, an inverter 5, elements 6, 7, 8, 9, 10 and 11.15

the elements OR 12, 13 and 14, the trigger registers 15,. 16 and 17, reading unit 18, incision bpog 19.

The device is based on the principle of dividing the period of relaxation to 20 equal-interval pa; during each interval of Tfonzoaaaaaa accumulation of anneformation, at the end of each interval, the accumulated information is recorded in the shifting solutions, the information is reset -5

Scientific research institutes in the accumulator (counter) after the shift) a new accumulation period begins, etc.

The shift registers are controlled by a clock (shift) input, 30 so that during each average information accumulation interval these registers are shifted by (H + 1) bit, and their output is at that moment associated with the input. 35

Each register has q bits.

Thus, by the end of each information accumulation interval in the first bits of the registers it turns out to be iformal data for the accumulation interval, ending in (T) seconds of the present moment, where T is the averaging period, and instead of this information is inserted.

Since at the output of the registers with the SCVI-15, the social index of each register T-shirt appears successively, by summing this information for each average interval one obtains information about the average. 50

The output of the transducer 1 to the input of the side 2 receives the frequency; proportional to the averaged electrical signal If the unit 2 input does not have a signal from the first output of reisepaTopa 3, then an hour of 55 seconds passes to the input of counter 4 without delay, if such a signal eats1, then bpok 2 delays the arrival of the average frequency pulse to the counting What is the counter of counter 4 until the signal is removed from the c- –pe | 5V () 1X generator output 3.

Signals to the first output are, in fact, strobe pulses, so the duty cycle of these signals is chosen as high as possible.

The same signal is fed to the input c6psa in O counter 4.

Thus, in the counter 4, an accumulation of averaged frequency pulses occurs between each two signals from the first output of the heater 3.

The period of arrival of signals from the first output g of generator 3 is equal to t.

 ,

gy, e P - the number of bits of each of the shift registers 15, 16 and 17;

T. is the averaging period.

The arrival time of the 1 Chr signals from the secondary output of the generator 3, associated with the clock-1 and the inputs of the shift registers 15, 16 and 17, is determined by the ratio

i.

. n + 1. Special, for the period

 information in registers 15, 16 and

17 (And + 1) bits

The output of each of these registers is connected to the input through the corresponding elements AND 9, Yu and 11, and elements OR 12 13 and 14.

When the signal is absent on the first output of reiiepaTOpa 3, a resolution is given from the output of the inverter 5 to the second inputs of elements 9, 10 and 11, and the information from the output of the last bit of each shift register is recorded for the first bit of the shift register. At the end of each nepHonai, a short signal appears on the first output of the generator 3, thus the inverter 5 and the elements 9, 10 and 11 prohibit the passage of information from the outputs of the shift registers to their inputs. Now the information D nepBFiie bits of the shift registers 15, 16 and 17 are recorded from the outputs of the counters 4 through the elements AND b, 7 and 8 and the elements OR 12, 13 and 14, respectively. This information is triggered by clock pulses from the second output of generator 3, the pulse at the first output of generator 3 ends, thereby wrapping the counter 4, and again the flow of information from the output of each shift register to its input is allowed.

The output of each shift register 15, 16 and 17 is connected to the inputs of the block.

18 reading.

The box 18 is produced by the parapepidae of the numbers coming from the scrolling registers 15, 16 and 17, the npUHevi team is sent to the second output of the generator 3, which goes to the box 18. So, from the register 15, the information comes 2 ° , from register 17 comes out, information 2,

The side 18 enters the input side 19 and the result is also based on the imp pulse from the first output of the generator 3; This distribution also represents a cluster of 1: the larger, abbreviated value of the electrical sieve. This value is stored in the display side 19 until the next value is received.

The economic effect of the present invention is a significant reduction in the equipment for performing a sliding average electric signal due to the fact that the accumulation of information does not take place in the entire T-averaging period as in the known device, but in the interval.

Claims (1)

Invention Formula Device for sliding elimination of an electrical signal, comprising an analog-to-frequency converter, a generator pulses, a counter, each bit of which is connected to the first inputs of the elements I, the second inputs of which are connected to the first output of the generator, scoring the register, according to the number of bits of the counter and reading bpok, characterized in that synchronization bpok, inverter, additional AND elements, OR elements and indication bpc are introduced, with one synchronization block input connected to the analog-frequency converter output, the other input to the first generator output of the pulses, and synchronizing bpoc output The counter with counting input of the counter, the clock inputs of the shift registers and the zero input of the readout unit are connected to the second output of the impulse generator, the outputs of the shifting replicas are connected to the information inputs of the readout unit and to the first inputs of the corresponding additional elements I, whose outputs are connected to the first inputs of the elements OR, the second inputs of which are connected to the outputs of the AND elements, the second inputs of the additional elements AND are connected to the clock input of the reading unit and connected to the output of the inverter, the stroke of which is connected to the first output of the generator and with the installation of the counter, and the output of the reading unit is connected to the input of the indication unit.