JPH01124773A - Frequency measuring instrument - Google Patents

Abstract

PURPOSE:To obtain a frequency measuring instrument with high measurement accuracy by correcting a sampling time by using last and current fraction time measured with a fraction count clock having a shorter period than a sampling period. CONSTITUTION:Inputs pulses, a sampling clock, and the fraction count clock are inputted to a synchronizing circuit 1 to generate a synchronous input pulse S1, a clear signal S2, a latch signal S3, and a clear signal S4. The synchronous input pulses S1 and clear signal S2 are inputted to an input pulse counter 2 to count the number N of the input pulses and the output of the counter is inputted to a latch 3. Further, the clear signal S4 and fraction count clock are inputted to a fraction counter 4 to count a fraction time, and counted value is inputted to a latch 5. Then the sampling period is corrected with the last fraction time and current fraction time and the number of the input pulses is divided by the corrected sampling period to find a frequency (f).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improving the accuracy of a frequency measuring device that measures the frequency of an input pulse every numbering period.

[Prior Art] As a conventional frequency measuring device, for example, the one shown in Fig. 5(a)
As shown in the time chart, there is a method in which the number N of input pulses is counted at every fixed numbering period T, and the frequency f of the input pulse is determined from f-N/T. The excluded frequencies are as shown in FIG. 3(b).

[Problems to be Solved by the Invention] However, since this device can only measure frequencies with a resolution of 1.1/T, there is a problem that sufficient measurement accuracy cannot be obtained. This is because the sampling period and the input pulse are not synchronized, so that a fractional time as shown in a occurs.

The present invention was made to solve these problems, and an object thereof is to realize a frequency measuring device that can measure frequency with high accuracy by correcting the rimbling time to a time synchronized with the input pulse. shall be.

[Means for Solving the Problems] The present invention provides a frequency measuring device that measures the frequency of an input pulse at each sampling period, which comprises: an input pulse counter that counts the number of input pulses at each sampling period; t, the fractional time from when the last pulse occurs to the end of the sampling period.
a fractional time output section that measures using a fractional clock with a shorter period than the sampling period and outputs the fractional time; a holding means that holds and outputs the fractional time of the previous sampling period; the input pulse counter; This frequency measuring device is characterized by comprising: a time output section and an operation section for calculating the frequency of the input pulse in the current sampling period using the following equation based on the output of the holding means.

f−N/(T+τvt−+−τn) f: frequency of input pulse N: Number of pulses generated in the current sampling period T: sampling period τl-1: Fractional time of the previous sampling period τn: Fractional time of current sampling cycle II [Example] The present invention will be explained below using the drawings.

FIG. 1 is a block diagram of an embodiment of a frequency measuring device according to the present invention.

In the figure, reference numeral 1 denotes a synchronous circuit, which synchronizes the input pulse sampling crotter with the fractional count clock CLK to generate a synchronous input pulse S+ and a synchronous 1 numbering crotter. The synchronous sampling clock is generated inside the synchronous circuit.

2 is an input pulse counter, sampling frequency +11
The count is cleared by the clear signal S2 from the synchronous circuit 1 every 1, and the synchronous input pulse S,
Count the number of pulses.

3 is a latch, and the latch signal 1"3 from the synchronous circuit 1
S3 latches and outputs the count of the input pulse counter 2.

4 is a fraction counter, and after the count is cleared by the clear signal 84 from the synchronization circuit 1, it starts counting the number of clocks of the fraction count clock CLK. The fractional count clock CLK has a period shorter than that of the sampling clock, and has a frequency of, for example, E5Ml-IZ.

A latch 5 wraps and outputs the count of the fraction counter 4 in response to a latch signal S from the synchronous circuit 1.

6 is a multiplier which calculates the fractional time from the fractional count outputted by the latch 5.

Fractional hours are (Fractional run 1 to clock period) × (fractional count) Find from.

A latch 7 latches and outputs the previous fractional time in response to a latch signal 85 from the synchronous circuit 1.

8 is an adder/subtractor, which performs the following addition/subtraction using the outputs of the multiplier 6 and latch 8.

T: TL -1 - τ1 T: Sampling period τl2 1: Previous fractional time τπ: Current fractional time 9 is divided by 1>2, and using the output of latch 3 and addition/subtraction r1, it is shown in the following equation. The current measurement frequency f is calculated by stopping and stopping.

f-N/(T-t τ 1 −1 − τ l )N
: Pulse number of input pulses Here, the fraction time output section in the claims is composed of a fraction counter 4, a latch 5, and an fjW device 6, the holding means is a latch 7, and the summation section is an adder/subtractor 8. Each corresponds to the i device 9 and the other.

Next, the operation of such a device will be explained.

2 is a time chart of the signal of the input pulse counter 2 part, and FIG. 3 is a time chart of the signal of the fraction counter 4 part.

In FIG. 2, the input pulse and the sampling clock are synchronized by the fractional count clock CLK to produce a synchronized input pulse S and a synchronized sampling clock. The count of the input pulse counter 2 increases every time the synchronization input pulse S1 is input. A clear signal S2 for the input cover counter 2 and a latch signal S3 for the latch 3 are generated from the synchronous sampling clock. These signals are offset by half a period of the fractional count clock to prevent contention between the counter clear and the latch.

In FIG. 3, a clear signal S4 for the fraction counter 4 is generated from the synchronous input pulse S1, and a latch signal S5 is generated from the synchronous sampling clock.

No. 91713 No. 84 is generated when the synchronization input pulse signal S+ is generated. Since the latch signal S5 is generated by a numbering clock, the output of the latch 5 is the number of fractional counting clocks counted from the time when the last pulse is generated in the sampling period until the end of sampling.

FIG. 4 is a diagram showing the relationship between the amount numbering time corrected by the end a time and the input clock.

In the 5A position according to the present invention, as shown in FIG. 4, N pulses are also input to the numbering time T+τ and -1−τl corrected using the previous fractional time τn−1 and the current fractional time τl. Therefore, the measurement frequency is calculated from N/(T+τ1−!−τn).

Note that the input pulse counter 2 and the fractional counter 4 are not limited to up counters, but may also be down counters.

[Effect] According to the present invention, the sampling time is corrected using the previous fractional time and the current fractional time measured by a fractional count clock with a period shorter than the sampling frequency (l),
Since the measurement frequency is calculated from the corrected sampling time, the measurement accuracy is higher than that of a device that measures the frequency with a resolution of 1/T.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a frequency measuring device according to the present invention, FIGS. 2 to 4 are explanatory diagrams of the operation of the device shown in FIG. 1, and FIG. 5 is an example of a conventional frequency am constant device. It is a time chart for explaining operation. 2...Input pulse counter, 4...Fraction counter,
5... Latch, 6... Multiplier, 7... Latch, 8
... adder/subtractor, 9... divider.

Claims (1)

[Claims] A frequency measuring device that measures the frequency of an input pulse at each sampling period, comprising: an input pulse counter that counts the number of input pulses at each sampling period; a fractional time output section that measures the fractional time from the time when the sampling period ends to the end of the sampling period using a fractional clock with a cycle shorter than the sampling period, and outputs the fractional time; and a fractional time output section that stores the fractional time of the previous sampling period. and an arithmetic unit that calculates the frequency of the input pulse in the current sampling period using the following equation based on the outputs of the input pulse counter, the fractional time output unit, and the holding unit. Characteristic frequency measurement device. f=N/(T+τ_n_-_1-τ_n) f: Frequency of input pulse N: Number of pulses counted in the current sampling period T: Sampling period τ_n_-_1: Fractional time of the previous sampling period τ_n: Fractional time of the current sampling period Fractional hours