RU2278390C1 - Digital frequency meter - Google Patents

Abstract

FIELD: measurement technology.

SUBSTANCE: frequency meter intends for measurement of signal frequency, deviation of frequency from nominal value, time intervals and for determination of signal frequency stability during different periods of time. Digital frequency meter has input signal receiving terminal, measurement period pulse receiving terminal, reference generator, two synchronization circuits, three counters with registers at output at any counter connected with processing and indication unit, inverter, error pulse former and pulse stretching circuit. First counter counts number of periods of frequency to be measured which pulses come to measurement interval. Second counter counts pulses from reference generator which allows determination of time scale to which scale the result of reading-out of first counter's readings are referred. Third counter counts number of pulses from reference generator from moment of forming of last front of signal of frequency to be measured till moment of reading codes of counters into registers out.

EFFECT: simplified design.

2 cl, 7 dwg

Description

The invention relates to measuring equipment and can be used in radio engineering, electrical engineering, metrology and other industries for precision measurement of signal frequency, frequency deviations from the nominal value, time intervals, as well as for obtaining statistical parameters characterizing frequency stability over various time periods.

Digital frequency meters of various designs are known. For example, a frequency meter is known (Fig. 1), including a port for receiving an input signal 1, a port for receiving a pulse of the measuring period 2, a reference generator 3, counters 4, 5, 6, registers 7, 8, 9 at their outputs, synchronization circuits 10, 11 , inverter 12, pulse shaper errors 13, the stretching circuit of the pulse 14, the processing and display means 15 [RF Patent No. 2210785].

This frequency meter is not characterized by a wide range of measured frequencies. The limitation on this range is due to the fact that the duration of the elongated pulse EL should not exceed the duration of the measuring interval.

Another frequency meter is known (Fig. 2), characterized in that for the purpose of expanding the range of measured frequencies it is equipped with a second error pulse shaper 16, a second duration measurement channel (counter 17 and register 18 connected in series) and a mismatch 19 selection circuit [RF Patent No. 2210785 ]. This frequency meter is the closest analogue of the proposed frequency meter for the largest number of similar features and is taken as a prototype of the invention. A complex circuit has been introduced in this frequency meter: a second error pulse shaper, a second duration measurement channel, and a mismatch selection circuit. In this case, to measure the time interval between the end of the measurement period and the next edge of the measured frequency, this interval is divided into two intervals, one of which contains an integer number of periods of the reference frequency, and the other contains a fractional part of this period. Only the second interval is measured using a stretching circuit, and the first interval is measured in an additional channel for measuring duration based on a counter that counts the impulses of the reference frequency.

The disadvantage of this frequency meter is the complexity of its design.

The problem to which the invention is directed, is to simplify the design of the frequency meter.

The problem is solved by the fact that a digital frequency counter is proposed, including an input signal receiving port, a measuring period pulse receiving port, a model generator, first and second synchronization circuits, first, second and third counters with registers at the output of each counter connected to the inputs of the processing means and indications, an inverter, an error pulse shaper and a pulse stretching circuit, the output of the input signal receiving port being connected through the first synchronization circuit to the input of the first counter, an exemplary gene the ator is connected to the inputs of the second and third counters, with the clock input of the first synchronization circuit and through the inverter with the clock input of the second synchronization circuit, the error pulse generator is connected via the pulse stretching circuit to the control input of the third counter, the output of the second synchronization circuit is connected to the clock inputs of the first and second counter, which also contains a trigger, the first input of which is connected to the output port of the pulse reception of the measuring period and the clock input of the register of the third counter, the second input with is single with the output port of the input signal, and the output is connected to the input of the second synchronization circuit.

Figure 1 shows a diagram of a frequency counter - analogue, in accordance with the patent of the Russian Federation No. 2210785.

Figure 2 shows a diagram of a frequency counter - prototype, in accordance with the patent of the Russian Federation No. 2210785.

Figure 3 shows a diagram of the proposed frequency meter.

Figure 4 shows a diagram of the proposed frequency meter without register 9.

Figure 5 shows a diagram of a two-channel frequency counter.

Figure 6 shows an embodiment of a synchronization circuit.

Figure 7 shows the preferred circuit of the proposed frequency meter.

The proposed digital frequency counter is shown in figure 3 and works as follows. The device comprises a port for receiving an input signal 1, a port for receiving a pulse of the measuring period 2, a reference generator 3, three counters (4, 5 and 6) with registers (7, 8 and 9) at the output, two synchronization circuits 10 and 11, an inverter 12, error pulse shaper 13, pulse stretching circuit 14, and processing and indication means 15 and trigger 20. For clarity, we select the pulse counter channel A1 containing elements 1, 10, 4, and 7 and the channel for determining the delay of front B formed by elements 13, 14, 6 and 9. The pulse counter channel A1 receives an input signal with port 1, synchronously ation F ₁ generated pulses synchronizing circuit 10, their continuous count counter 4 and the readout of the counter K ₁ in the register 7 with the advent of read signals WR. At the same time, counter 5 counts the pulses F _{0 of the} model generator 3, and its reading Ko is rewritten in register 8 with the arrival of the same signal WR. To generate WR signals, the receiving port of the measuring period 2 and the synchronization circuit 11 connected to the output of the reference generator through the inverter 12 are used. High accuracy of measurements is provided by the channel for determining the delay of the front 18, which allows to determine the duration of the pulse arriving at its input. To accurately measure this duration, the generated signal is fed to a stretching circuit of duration 14, which generates an impulse EL, the duration of which is increased by a predetermined number M times, for example, M = 100. This pulse is supplied to the control input of the counter 6, and the signal of reference frequency F ₀ from the output of the reference generator 3 is received at its counter input 3. The result K _{E of the} counter 6 during the existence of a pulse at its control input, proportional to this duration, is read into register 9, and from it to the processing and indication means (computer) 15, which makes it possible to clarify the time of arrival of the measured signal front from which the error pulse was generated. Thus, the pulse counting channel calculates an integer number of periods of the measured frequency falling in the measuring interval τ specified by the pulses WR. Synchronous count of these pulses output from intervals model generator 3 counter 5 enables the calculation of the timeline to which the attached readout of the counter 4. The channel allows specifying the time from formation of the last edge of the signal F ₁ within a measuring period, before the code reading counters 4, 5, 24 to registers 8, 7 and 25, respectively. Read control is carried out by the WR signal, which is synchronized by an inverted reference frequency pulse. Reading the code K _E from counter 6 into register 9 is carried out earlier, for which purpose the pulse from the output port of the pulse receiving port of the measuring period 2 serves. There may be no connection between the output of element 2 and the control zeroing at the input of counter 6, since counter 6 can be programmed to zero or not reset. In the second case, the counting result in the measurement cycle is calculated as the difference between the received code and the previous one, just as it is with the reading results of the counter codes 4, 5 and 24.

Compared to the prototype, the hardware is significantly simplified: instead of a complex additional pulse shaper of an error and a multi-bit counter with a register for the same number of bits, only one trigger is used. The software part is also simplified, because instead of reading the codes from registers 7 and 18 and summing the results, only reading the register 7 remains.

Thus, the simplification of the hardware and processing programs while maintaining all the characteristics of the frequency meter is ensured.

Additionally, the device can be simplified by eliminating register 9. Since counter 6 does not count continuously, but only during the existence of the EL pulse, which always ends before the measuring interval ends, by the time its information is read, counter 6 always ends the count, its code may be read directly from it.

Figure 4 shows a frequency meter, characterized by the absence of a register 9, and the output of the counter 6 is connected to the input of the processing and indication means 15.

Additionally, you can solve the problem of increasing the number of simultaneously measured frequencies while maintaining high accuracy and without a significant increase in hardware.

The problem is solved in that a switch and additional pulse counting channels are introduced into the device according to the number of additional measuring inputs, each of which contains a serial port for receiving input signals, a synchronization circuit, a counter and a register, while the inputs of the switch are connected to the outputs of the ports for receiving input signals , its output is with the trigger input, and the clock inputs of the synchronization circuits are connected to the output of the model generator.

The frequency meter works as follows (see Fig. 5, where the frequency meter diagram is shown for the case of one additional measuring input, that is, for a two-channel frequency meter). The device contains a port for receiving an input signal 1, a port for receiving a pulse of the measuring period 2, a reference generator 3, three counters (4, 5 and 6) with registers (7 and 8) at the output, the register of the third counter may be absent, two synchronization circuits 10 and 11 , an inverter 12, an error pulse shaper 13, a pulse stretching circuit 14, and processing and indication means 15. A switch 21 and one additional channel for pulse counting A2, comprising an input signal receiving port 22, a synchronization circuit 23, a counter 24, and a register 25, are introduced into the device. Highlighted the first Kana counting pulses A1, containing the elements 1, 10, 4 and 7 and the delay specification of the front channel in the formed elements 13, 14, 6 and 9. All elements work in the same way as in the previous frequency meter 3. Each of the pulse counting channels A1 and A2 receives the input signal with ports 1 and 22, synchronizes the generated pulses F ₁ and F _{2 with} synchronization circuits 10 and 23, continuously counts them with counters 4 and 24 and reads the readings of these counters K ₁ and K ₂ into the registers 7 and 25 with the arrival of WR read signals. At the same time, counter 5 counts the impulses F _{0 of the} model generator 3, and its reading K _{о is} written to register 8 with the arrival of the signal WR. The edge delay refinement channel B serves to clarify the length of the time interval between the edge of the read signal of register WR and the edge of the input signal. In contrast to the previous scheme, this channel in turn serves all measuring channels. In the shown two-channel frequency meter, on each odd cycle, the switch 21 connects the input of the error pulse shaper to the output of the first input signal receiving port 1, and in each even cycle, to the output of the second input signal receiving port 22. An ER pulse is generated with odd changes, the duration of which is equal to the duration the interval between the front of the signal WR and the front of the signal F _{1 of the} first channel A1, and in even measurements an impulse ER is formed corresponding to the duration of the interval between the signal WR and the front of the signal F _{2 of the} second channel A2. The result K _{E of the} counter b is used to clarify the arrival time of the edge of the measured signal from which the error pulse was generated. Channel B allows you to specify the time of arrival of the front at one of the alternately switched inputs F ₁ and F ₂ . In the N-channel version, information about this time comes from each channel N times less than in the single-channel version. Therefore, it allows you to clarify the measurement result for each channel only on the interval Nτ between two consecutive connections of the refinement channel B to a given input signal receiving port. As a result, simultaneous continuous measurement of frequencies arriving at a given number of N inputs is carried out. Moreover, at intervals of duration τ the refinement of the result does not occur, and at intervals of duration Nτ and multiples of this duration, the measurement result is refined M times. In this case, the hardware increases only by one N-channel switch and by N-1 additional pulse counting channels. The common part remains unchanged: the channel for determining the delay of the edge B, the pulse receiving port of the measuring period 2 with the synchronization circuit 11, the reference generator 3, inverter 12, counter 5, register 8, and computer 15.

Thus, an increase in the number of simultaneously measured frequencies is maintained while maintaining high accuracy and without a significant increase in hardware.

All elements can be made in the same way as in the prototype.

Each of the two synchronization schemes can be performed, for example, as in the prototype or as shown in Fig.6. It consists of three triggers in series and an inverter, with the clock input of the synchronization circuit connected to the clock input of the second trigger and through the inverter with the clock input of the third trigger, the output of the third trigger connected to the reset input of the first trigger and is the output of the synchronization circuit, and its input is the first input of the first trigger.

The counter pulse generator can be performed, for example, as described in the prototype.

Counters with registers can be performed, for example, on programmable logic.

Means of processing and display is a computer.

The port for receiving the pulse of the measuring period can be performed, for example, as a Schmitt trigger, and can also be replaced by a pulse shaper of the measuring period, for example, with the electronic clock included in the computer.

An exemplary generator may be any stable generator, for example, a hydrogen frequency standard.

The simplest version of the error pulse shaper is, for example, a trigger with a separate start. The pulse front of the exact boundaries WR sets the output signal ER to the active state, and the subsequent counting pulse F ₁ returns it to its original state, thereby forming the pulse duration ER.

The pulse stretching circuit converts a short pulse into an extended pulse with a given conversion factor for the duration.

The stretching scheme can be performed as in the prototype, for example, containing two current sources of opposite signs, included at the input of the integrator, at the output of which a threshold device is included. One of the current sources is switched, and its current is a specified number M times the current of the non-switched source, and a control circuit is included at its input.

A preferred digital frequency counter circuit is shown in FIG. 7. All hardware (except elements 13 and 15) is made on programmable logic. In the three-channel case, two additional channels A2 and A3 are introduced. Elements 29-32 of channel A3 are completely identical to elements 22-25 of channel A2.

Claims (2)

1. A digital frequency meter, including an input signal receiving port, a measurement period pulse receiving port, a reference generator, first and second synchronization circuits, first, second and third counters with registers at the output of each counter connected to the inputs of the processing and indication means, an inverter, a shaper an error pulse and a pulse stretching circuit, the output of the input signal receiving port being connected through the first synchronization circuit to the input of the first counter, the reference generator connected to the inputs of the second and third counts kov, with the clock input of the first synchronization circuit and through the inverter - with the clock input of the second synchronization circuit, the error pulse generator is connected via the pulse stretching circuit to the control input of the third counter, the output of the second synchronization circuit is connected to the clock inputs of the registers of the first and second counters, characterized in that it contains a trigger, the first input of which is connected to the output of the pulse receiving port of the measuring period and the clock input of the register of the third counter, the second input of which is connected to the output unit of reception of the input signal, and the output is connected to the input of the second synchronization circuit. 2. The frequency meter according to claim 1, characterized in that it comprises a switch and additional channels for counting pulses according to the number of additional measuring inputs, each of which contains a serial port for receiving input signals, a synchronization circuit, a counter and a register, while the inputs of the switch are connected to the outputs of the ports for receiving input signals, its output is connected to the second input of the trigger, and the clock inputs of the synchronization circuits are connected to the output of the reference generator.

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