JP2010261775A - Frequency measuring circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To measure frequency of an input signal at a desired accuracy, even when a pulse wave whose turning on time is unfixed is an input signal. <P>SOLUTION: When an observation signal becomes logic Low, detection voltage V<SB>2a</SB>held by an analog interpolator 7 with a built-in latch is selected, if the latch signal L<SB>a</SB>is logic High; and detection voltage V<SB>2b</SB>held by an analog interpolator 8 with a built-in latch is selected, if the latch signal L<SB>b</SB>is logic High. The frequency f<SB>in</SB>of the input signal is calculated, by using the selected detection voltage V<SB>2</SB>(V<SB>2a</SB>or V<SB>2b</SB>), detection voltage V<SB>1</SB>output from an analog interpolator 6, a counted value m, and a counted value n. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a frequency measurement circuit that is mounted on, for example, a radio communication device or a radar device and measures the frequency of an input signal.

FIG. 9 is a block diagram showing a frequency measurement circuit disclosed in Non-Patent Document 1.
When the processing circuit 101 receives the input of the observation signal from the outside, the processing circuit 101 outputs the control signals B and C to the counters 104 and 106 in order to start measuring the frequency of the input signal (frequency f _in ). Are reset to zero, and control signals D and E are output to the analog interpolators 107 and 108 to set the analog interpolators 107 and 108 to the initial state.
Further, when receiving an observation signal input from the outside, the processing circuit 101 outputs a control signal A to the synchronization circuit 102 to start the operation of the synchronization circuit 102.

Upon receiving the control signal A from the processing circuit 101 and detecting the rising edge of the input signal (frequency f _in ), the synchronization circuit 102 sets the synchronization signal to logic high, as shown in FIG. Are output to the AND circuits 103 and 105 and the analog interpolators 107 and 108.

The AND circuit 103 receives the synchronization signal and the clock signal (frequency f _clk ) output from the synchronization circuit 102, and outputs the clock signal to the counter 104 during the period when the synchronization signal is logic high.
The AND circuit 105 receives the synchronization signal output from the synchronization circuit 102 and the input signal (frequency f _in ), and outputs the input signal to the counter 106 during a period when the synchronization signal is logic high.

The counter 104 increases the count value m by 1 in synchronization with the rising edge of the clock signal output from the AND circuit 103, and outputs the count value m to the processing circuit 101.
The counter 106 increases the count value n by 1 in synchronization with the rising edge of the clock signal output from the AND circuit 105, and outputs the count value n to the processing circuit 101.
Upon receiving the logic high synchronization signal from the synchronization circuit 102, the analog interpolator 107 detects the rising edge of the synchronization signal and the rising edge of the clock signal, and as shown in FIG. 11, the time difference T ₁ between these edges is detected. And a detection voltage V ₁ corresponding to the time difference T ₁ is output to the processing circuit 101.

When the count value n output from the counter 106 reaches a predetermined value (for example, N), the processing circuit 101 outputs a control signal A to the synchronization circuit 102 and stops the operation of the synchronization circuit 102.
Upon receiving the control signal A from the processing circuit 101 and detecting the rising edge of the input signal, the synchronization circuit 102 sets the synchronization signal to logic low, as shown in FIG. 105 and analog interpolators 107 and 108.

When the synchronization circuit 102 sets the synchronization signal to logic low, the count-up operation of the counters 104 and 106 stops.
At this time, the count value of the counter 104 is M, and the count value of the counter 106 is N.
Since the analog interpolator 107 detects the rising edge of the synchronization signal, it does not react even if the synchronization circuit 102 sets the synchronization signal to logic low, and outputs the detection voltage V ₁ to the processing circuit 101.
When the analog interpolator 108 receives the logic low synchronization signal from the synchronization circuit 102, the analog interpolator 108 detects the falling edge of the synchronization signal and the rising edge of the clock signal, and as shown in FIG. The time difference T ₂ is detected, and a detection voltage V ₂ corresponding to the time difference T ₂ is output to the processing circuit 101.

Here, FIG. 10 is a block diagram showing the inside of the analog interpolators 107 and.
The edge detection circuit 111 of the analog interpolator 107 detects the rising edge of the synchronization signal and the rising edge of the clock signal, and detects the rising edge of the synchronization signal until the rising edge of the clock signal is detected. A logic high control signal is output to the switch 113.
On the other hand, the edge detection circuit 111 of the analog interpolator 108 detects the falling edge of the synchronization signal and the rising edge of the clock signal, detects the falling edge of the synchronization signal, and then detects the rising edge of the clock signal. Until that time, a logic high control signal is output to the switch 113.

The switches 113 of the analog interpolators 107 and 108 are closed during the period of receiving the logic high control signal from the edge detection circuit 111, and the constant current output from the constant current source 112 flows to the capacitor 114.
As a result, the capacitor 114 of the analog interpolator 107 is charged with a charge proportional to the time difference T ₁ between the rising edge of the synchronization signal and the rising edge of the clock signal, and the detection voltage V ₁ corresponding to the charge amount of the charge is supplied. It is output to the processing circuit 101.
The capacitor 114 of the analog interpolator 108 is charged with a charge proportional to the time difference T ₂ between the falling edge of the synchronizing signal and the rising edge of the clock signal, and a detection voltage V ₂ corresponding to the charge amount of the charge is supplied. It is output to the processing circuit 101.

Note that the switch 115 of the analog interpolators 107 and 108 is closed when receiving a control signal from the outside.
Thereby, since both ends of the capacitor 114 of the analog interpolators 107 and 108 are grounded, the charged electric charge is discharged.

As shown in FIG. 11, time synchronization signal is logic High (time from _{T a} to _{T b)} is a _{(N-1) / f in} , _also in _{T 1 + M / f clk -T} 2 I know that there is.
At this time, since f _clk , N, M, T ₁ and T ₂ are already known, the frequency f _{in of the} input signal can be obtained by the following equation (1).
_{f in = (N-1)} / (T 1 + M / f clk -T 2) (1)

However, the frequency measurement circuit of FIG. 9 is based on the premise that the input signal is a continuous wave as shown in FIG.
That is, the frequency measurement circuit shown in FIG. 9, in the time until the predetermined count value (N / f _in), that the input signal is input, it is possible to counter 106 performs a desired operation.
Therefore, when the input signal is a pulse wave as shown in FIG. 12 and the input signal is turned off before the count value n of the counter 106 reaches the predetermined count value, correct frequency measurement cannot be performed. .

S. Johansson, “New frequency counting principal impulse resolution”, Proceedings of the 2005, IEEE International Frequency control, May 29, 2003 628 to 635

  Since the conventional frequency measurement circuit is configured as described above, if the input signal is a pulse wave and the time when the pulse wave is on is known, the predetermined count value N in the counter 106 is set in advance. The frequency can be measured by changing. However, when the time when the pulse wave is turned on changes and the time is indefinite, there is a problem that the frequency measurement accuracy is significantly deteriorated.

  The present invention has been made to solve the above-described problems, and is capable of measuring the frequency of an input signal with a desired accuracy even when a pulse wave with an indefinite time is an input signal. The purpose is to obtain a measurement circuit.

  The frequency measurement circuit according to the present invention includes a time difference detection unit that detects a time difference between the synchronization signal output from the synchronization signal generation unit and the clock signal, and a first delay time detection that detects a delay time of the input signal with respect to the clock signal. And a second delay time detecting means for detecting a delay time of the input signal with respect to the clock signal, and the frequency calculating means is configured to detect the delay time by the first delay time detecting means and detect the second delay time. The delay time detected by the first delay time detecting means or the second delay time detecting means and the time difference detected by the time difference detecting means are alternately executed every time the clock signal is detected. The frequency of the input signal is calculated using the count results of the clock signal counting means and the input signal counting means.

  According to this invention, the time difference detection means for detecting the time difference between the synchronization signal output from the synchronization signal generation means and the clock signal, the first delay time detection means for detecting the delay time of the input signal with respect to the clock signal, Second delay time detecting means for detecting the delay time of the input signal with respect to the clock signal is provided, and the frequency calculating means detects the delay time by the first delay time detecting means and the delay by the second delay time detecting means. The time detection process is alternately performed for each cycle of the clock signal, the delay time detected by the first delay time detection means or the second delay time detection means, the time difference detected by the time difference detection means, and the clock signal Since the frequency of the input signal is calculated using the counting means and the counting result of the input signal counting means, a pulse wave with an indefinite time to turn on Even if an input signal, there is an advantage of being able to measure the frequency of the input signal with a desired accuracy.

It is a block diagram which shows the frequency measurement circuit by Embodiment 1 of this invention. It is explanatory drawing which shows the time waveform of various signals. It is a block diagram which shows the frequency measurement circuit by Embodiment 2 of this invention. It is explanatory drawing which shows the time waveform of various signals. It is a block diagram which shows the latch built-in analog interpolators 7 and 11 of the frequency measurement circuit by Embodiment 3 of this invention. It is a block diagram which shows the latch built-in analog interpolators 8 and 12 of the frequency measurement circuit by Embodiment 3 of this invention. It is a block diagram which shows the latch built-in analog interpolators 7 and 11 of the frequency measurement circuit by Embodiment 4 of this invention. It is a block diagram which shows the latch built-in analog interpolators 8 and 12 of the frequency measurement circuit by Embodiment 4 of this invention. It is a block diagram which shows the frequency measurement circuit currently disclosed by the nonpatent literature 1. 2 is a configuration diagram showing the inside of analog interpolators 107 and 108. FIG. It is explanatory drawing which shows the time waveform of various signals. It is explanatory drawing which shows the time waveform of the input signal which is a continuous wave, and the input signal which is a pulse wave.

Embodiment 1 FIG.
1 is a block diagram showing a frequency measurement circuit according to Embodiment 1 of the present invention.
In FIG. 1, the synchronization circuit 1 receives a logic high control signal A from the frequency calculation processing circuit 9 (a signal that becomes logic high when an observation signal that becomes logic high is input during a period when the input signal is significant). In synchronization with the rising edge of the input signal (frequency f _in ), the synchronization signal is set to logic high, and the logic high synchronization signal is output to the AND circuits 2 and 4 and the analog interpolator 6. The synchronization circuit 1 constitutes a synchronization signal generating means.

The AND circuit 2 receives the synchronization signal and the clock signal (frequency f _clk ) output from the synchronization circuit 1, and performs a process of outputting the clock signal to the counter 3 while the synchronization signal is logic high.
The counter 3 performs a process of incrementing the count value m by 1 in synchronization with the rising edge of the clock signal output from the AND circuit 2 and outputting the count value m to the frequency calculation processing circuit 9.
The AND circuit 2 and the counter 3 constitute clock signal counting means.

The AND circuit 4 receives the synchronization signal output from the synchronization circuit 1 and the input signal (frequency f _in ), and performs a process of outputting the input signal to the counter 5 during a period in which the synchronization signal is logic high.
The counter 5 increases the count value n by 1 in synchronization with the rising edge of the input signal output from the AND circuit 4 and outputs the count value n to the frequency calculation processing circuit 9.
The AND circuit 4 and the counter 5 constitute input signal counting means.

The analog interpolator 6 detects the rising edge of the synchronizing signal output from the synchronizing circuit 1 and the rising edge of the clock signal, detects the time difference T ₁ between these edges, and detects the detection voltage V corresponding to the time difference T _{1. 1} is output to the frequency calculation processing circuit 9. The analog interpolator 6 constitutes a time difference detection means.

The latch built-in analog interpolator 7 detects the delay time T _2a of the input signal with respect to the clock signal, holds the detection voltage V _2a corresponding to the delay time T _2a , and calculates the frequency of the held detection voltage V _2a. Processing to be output to the processing circuit 9 is performed.
Further, the latch internal analog interpolator 7 detects a delay time T _2a, while outputting a latch signal L _a frequency calculation processing circuit 9, a latch from the control signal E (latch integrated analog interpolator 8 from the frequency calculation processing circuit 9 When the signal _Lb is output to the frequency calculation processing circuit 9, when the signal Lb is received), the held detection voltage _V2a is reset to zero (initialized).
The latch built-in analog interpolator 7 constitutes a first delay time detecting means.

The analog interpolator 8 with a built-in latch detects a delay time T _2b of the input signal with respect to the clock signal, holds the detection voltage V _2b corresponding to the delay time T _2b , and calculates the frequency of the held detection voltage V _2b. Processing to be output to the processing circuit 9 is performed.
Further, when the latch built-in analog interpolator 8 detects the delay time T _2b , it outputs the latch signal L _b to the frequency calculation processing circuit 9, while the frequency calculation processing circuit 9 outputs the control signal F (latches from the latch built-in analog interpolator 7. when the signal L _a is output to the frequency calculation circuit 9, it receives the signal) outputted from the frequency calculation processing circuit 9, a detected voltage V _2b held reset to zero (initialization).
The latch built-in analog interpolator 8 constitutes a second delay time detecting means.

When the frequency calculation processing circuit 9 receives the latch signal La from the latch built-in analog interpolator 7, it outputs _a control signal F to the latch built-in analog interpolator 8, and the detection voltage V held by the latch built-in analog interpolator 8. while reset to zero _2b, when receiving the latch signal L _b from the latch integrated analog interpolator 8, control signals E and outputs the latched internal analog interpolator 7, the detection voltage held by the latch internal analog interpolator 7 _V2a is reset to zero.
Further, when the frequency calculation circuit 9 which observed signal becomes logic Low, if a latch signal L _a latch integrated analog interpolator 7 is outputting the logic High, it is held by the latch internal analog interpolator 7 select a detection voltage V _2a which are, conversely, if the latch signal L _b is logic High latch integrated analog interpolator 8 is outputting the detection voltage V _2b held by the latch internal analog interpolator 8 The selected detection voltage V ₂ (V _2a or V _2b ), the detection voltage V ₁ output from the analog interpolator 6, the count value m output from the counter 3 and the counter 5 by using the count value n, which carries out a process of calculating the frequency f _in of the input signal.
The frequency calculation processing circuit 9 constitutes frequency calculation means.

Next, the operation will be described.
When the input signal (frequency f _in ) is significant from the outside (during the period when the pulse wave is ON: see FIG. 12), the frequency calculation processing circuit 9 receives the input of the observation signal that becomes logic high. Control signals B and C are output to the counters 3 and 5, and the count values m and n of the counters 3 and 5 are reset to zero.
The frequency calculation processing circuit 9 receives the input from outside observation signal, and outputs a control signal D to the analog interpolator 6, as well as the zero reset detection voltage V ₁ of the analog interpolator 6, the control signal E , F are output to the latch built-in analog interpolators 7 and 8, and the detection voltages V _2a and V _2b of the latch built-in analog interpolators 7 and 8 are reset to zero. When the input is received, the control signal A is output to the synchronization circuit 1 to start the operation of the synchronization circuit 1.

When receiving the control signal A from the frequency calculation processing circuit 9 and detecting the rising edge of the input signal (frequency f _in ), the synchronization circuit 1 sets the synchronization signal to logic high as shown in FIG. The synchronization signal is output to the AND circuits 2 and 4 and the analog interpolator 6.

The AND circuit 2 receives the synchronization signal and the clock signal (frequency f _clk ) output from the synchronization circuit 1, and outputs the clock signal to the counter 3 during the period when the synchronization signal is logic high.
The AND circuit 4 receives the synchronization signal and the input signal (frequency f _in ) output from the synchronization circuit 1, and outputs the input signal to the counter 5 during a period when the synchronization signal is logic high.

The counter 3 increases the count value m by 1 in synchronization with the rising edge of the clock signal output from the AND circuit 2, and outputs the count value m to the frequency calculation processing circuit 9.
The counter 5 increases the count value n by 1 in synchronization with the rising edge of the clock signal output from the AND circuit 4, and outputs the count value n to the frequency calculation processing circuit 9.
When the analog interpolator 6 receives the logic high synchronization signal from the synchronization circuit 1, the analog interpolator 6 detects the rising edge of the synchronization signal and the rising edge of the clock signal, and as shown in FIG. T ₁ is detected, and a detection voltage V ₁ corresponding to the time difference T ₁ is output to the frequency calculation processing circuit 9.

The latch built-in analog interpolator 7 and the latch built-in analog interpolator 8 operate alternately for each cycle of the clock signal under the control of the frequency calculation processing circuit 9, and the delay time T ₂ (V _2a of the input signal with respect to the clock signal). Or V _2b ).
In other words, the latch built-in analog interpolator 7 outputs the control signal E from the frequency calculation processing circuit 9 and resets the held detection voltage V _2a to zero, and then receives the clock signal and the input signal. Then, the rising edge of the clock signal and the input signal is detected.
The latch built-in analog interpolator 7 detects the time from when the rising edge of the clock signal is detected to when the rising edge of the input signal is detected as the delay time T _2a of the input signal with respect to the clock signal.
The latch built-in analog interpolator 7 holds the detection voltage V _2a corresponding to the delay time T _2a and outputs the held detection voltage V _2a to the frequency calculation processing circuit 9.
The latch integrated analog interpolator 7 detects a delay time T _2a of the input signal relative to the clock signal, and outputs a latch signal L _a frequency calculation processing circuit 9.

When the latch built-in analog interpolator 8 outputs the control signal F from the frequency calculation processing circuit 9 and resets the held detection voltage _V2b to zero, the clock signal and the input signal are input. The rising edges of the clock signal and the input signal are detected.
The latch built-in analog interpolator 8 detects the time from when the rising edge of the clock signal is detected to when the rising edge of the input signal is detected, as the delay time _T2b of the input signal with respect to the clock signal.
The latch built-in analog interpolator 8 holds the detection voltage V _2b corresponding to the delay time T _2b and outputs the held detection voltage V _2b to the frequency calculation processing circuit 9.
Further, the latch built-in analog interpolator 8 outputs the latch signal _Lb to the frequency calculation processing circuit 9 when detecting the delay time _T2b of the input signal with respect to the clock signal.

Frequency calculation processing circuit 9, for operating alternately latch integrated analog interpolator 7 and a latch integrated analog interpolator 8 every period of the clock signal, when receiving the latch signal L _a from the latch integrated analog interpolator 7, the control signal F is output to the analog interpolator 8 with a built-in latch, and the detection voltage _V2b held by the analog interpolator 8 with a built-in latch is reset to zero.
On the other hand, when receiving the latch signal L _b from the latch integrated analog interpolator 8, control signals E and outputs the latched internal analog interpolator 7, zero reset detection voltage V _2a held by the latch internal analog interpolator 7 To do.

When the observation signal becomes logic low, the frequency calculation processing circuit 9 outputs the control signal A to the synchronization circuit 1 and stops the operation of the synchronization circuit 1.
When receiving the control signal A from the frequency calculation processing circuit 9, the synchronization circuit 1 sets the synchronization signal to logic low and outputs the synchronization signal to the AND circuits 2 and 4 and the analog interpolator 6 as shown in FIG. 2. To do.

When the synchronization circuit 1 sets the synchronization signal to logic low, the count-up operations of the counters 3 and 5 are stopped.
At this time, the count value of the counter 3 is M, and the count value of the counter 5 is N.
Since the analog interpolator 6 detects the rising edge of the synchronization signal, it does not react even if the synchronization circuit 1 sets the synchronization signal to logic low, and outputs the detection voltage V ₁ to the frequency calculation processing circuit 9. .

Further, when the observation signal becomes logic low, the frequency calculation processing circuit 9 determines which of the latch signals L _a and L _b output from the latch built-in analog interpolators 7 and 8 is logic high. Is determined.
Frequency calculation processing circuit 9, a latch signal L _a latch integrated analog interpolator 7 is if the output is a logic High, selects the detection voltage V _2a held by the latch internal analog interpolator 7.
Conversely, the latch signal L _b latch integrated analog interpolator 8 is if the output is a logic High, selects the detection voltage V _2b held by the latch internal analog interpolator 8.

When the frequency calculation processing circuit 9 selects either the detection voltage V _2a held by the latch built-in analog interpolator 7 or the detection voltage V _2b held by the latch built-in analog interpolator 8, the selected detection voltage Using V ₂ (V _2a or V _2b ), the detection voltage V ₁ output from the analog interpolator 6, the count value M output from the counter 3, and the count value N output from the counter 5 The frequency f _{in of the} input signal is calculated.
That is, as shown in FIG. 2, (time from _{T a} to _{T b)} time synchronization signal is logic High is _{(N-1) / f in} , _{also, T 1 + (M-1} ) It can be seen that / f _clk + T ₂ .
At this time, since f _clk , N, M, T ₁ and T ₂ are already known, the frequency calculation processing circuit 9 obtains the frequency f _{in of the} input signal by the following equation (2).
f _in = (N−1) / (T ₁ + (M−1) / f _clk + T ₂ ) (2)
Note that is uniquely determined from the time difference _{T 1} is detected voltage _{V 1,} the delay time _{T 2} are detection voltage _V 2 _{(V 2a or,, V 2b)} it is uniquely determined from.

As apparent from the above, according to the first embodiment, the rising edge of the synchronizing signal and the rising edge of the clock signal output from the synchronizing circuit 1 are detected, and the time difference T ₁ between these edges is detected. The analog interpolator 6 that outputs the detection voltage V ₁ corresponding to the time difference T ₁ to the frequency calculation processing circuit 9 and the delay time T _2a of the input signal with respect to the clock signal are detected, and the delay time T _2a is determined according to the delay time T _2a holds the detected voltage V _2a, a latch integrated analog interpolator 7 outputs a detected voltage V _2a have the held frequency calculation circuit 9 detects a delay time T _2b of the input signal to the clock signal, the holds the detected voltage V _2b corresponding to the delay time T _2b, latch integrated analog interpolator 8 which outputs a detection voltage V _2b that its retention in the frequency calculation processing circuit 9 The provided, holding the frequency calculation processing circuit 9, when the observed signal becomes logic Low, the latch signal L _a latch integrated analog interpolator 7 is if the output is a logic High, the latch integrated analog interpolator 7 select a detection voltage V _2a being, conversely, if the latch signal L _b latch integrated analog interpolator 8 is outputting the logic High, the detection voltage V that is held by the latch internal analog interpolator 8 _2b , the selected detection voltage V ₂ (V _2a or V _2b ), the detection voltage V ₁ output from the analog interpolator 6, the count value m output from the counter 3, and the counter 5 by using the count value n outputted, since it is configured to calculate the frequency f _in of the input signal, the on and becomes time input indefinite pulse wave signal Even if it is a signal, there is an effect that the frequency of the input signal can be measured with a desired accuracy.
That is, in the first embodiment, the frequency is automatically measured until the observation signal becomes logic low without setting the count values of the counters 3 and 5, so that the counter is turned on. Even when a pulse wave having an indefinite time is an input signal, the frequency can be correctly measured.

In the first embodiment, the counters 3 and 5 increase the count values m and n by 1 in synchronization with the rising edge of the clock signal. However, the counters 3 and 5 are set at the falling edge of the clock signal. In synchronization, the count values m and n may be increased by one.
The analog interpolator 6 detects the rising edge of the rising edge and the clock signal of the synchronization signal, has been described to detect the time difference T ₁ of the between those edges, the falling edge of the analog interpolator 6 synchronizing signal Alternatively, the falling edge of the clock signal may be detected, and the time difference T ₁ between these edges may be detected.
The latch interpolating analog interpolators 7 and 8 determine the time from the detection of the rising edge of the clock signal to the detection of the rising edge of the input signal as the delay times T _2a and T _2b of the input signal with respect to the clock signal. Although what is detected is shown, the time from when the falling edge of the clock signal is detected to when the falling edge of the input signal is detected may be detected.

Embodiment 2. FIG.
FIG. 3 is a block diagram showing a frequency measurement circuit according to Embodiment 2 of the present invention. In the figure, the same reference numerals as those in FIG.
The two-frequency divider 10 divides the frequency of the clock signal by two and performs a process of outputting a rectangular signal, which is the clock signal after the frequency division by two, to the latch-embedded analog interpolators 11 and 12. The 2 frequency divider 10 constitutes frequency dividing means.

The analog interpolator 11 with a built-in latch detects a delay time T _2a of the input signal with respect to the rectangular signal (clock signal after frequency division by 2) output from the frequency divider 10, and a detection voltage corresponding to the delay time T _2a A process of holding V _2a and outputting the held detection voltage V _2a to the frequency calculation processing circuit 9 is performed.
Further, the latch internal analog interpolator 11 detects a delay time T _2a, while outputting a latch signal L _a frequency calculation processing circuit 9, the control signal E (latch from the latch integrated analog interpolator 12 from the frequency calculation processing circuit 9 When the signal _Lb is output to the frequency calculation processing circuit 9, when the signal Lb is received), the held detection voltage _V2a is reset to zero (initialized).
The latch built-in analog interpolator 11 constitutes a first delay time detecting means.

The latch built-in analog interpolator 12 detects the delay time T _2b of the input signal with respect to the rectangular signal (clock signal after frequency division by 2) output from the divide-by-two 10 and detects a voltage corresponding to the delay time T _2b. A process of holding V _2b and outputting the held detection voltage V _2b to the frequency calculation processing circuit 9 is performed.
Further, when the latch built-in analog interpolator 12 detects the delay time T _2b , it outputs the latch signal L _b to the frequency calculation processing circuit 9, while the frequency calculation processing circuit 9 outputs the control signal F (latches from the latch built-in analog interpolator 11. when the signal L _a is output to the frequency calculation circuit 9, it receives the signal) outputted from the frequency calculation processing circuit 9, a detected voltage V _2b held reset to zero (initialization).
The latch built-in analog interpolator 12 constitutes a second delay time detecting means.

Next, the operation will be described.
Except for the divide-by-two 10 and the analog interpolators 11 and 12 with a built-in latch, the processing is the same as that of the first embodiment.
When the clock signal is input, as shown in FIG. 4, the frequency divider 10 divides the frequency of the clock signal by 2, and a rectangular signal that is the clock signal after the frequency division by 2 is latched with an analog interpolator 11 with a built-in latch. 12 is output.

The latch built-in analog interpolator 11 and the latch built-in analog interpolator 12 operate alternately for each cycle of the clock signal under the control of the frequency calculation processing circuit 9, and the delay time T ₂ (V _2a of the input signal with respect to the clock signal). Or V _2b ).
That is, the latch built-in analog interpolator 11 outputs the control signal E from the frequency calculation processing circuit 9, so that the held detection voltage V _2a is reset to zero and then output from the frequency divider 10. When a rectangular signal and an input signal are input, rising edges of the rectangular signal and the input signal are detected.
As shown in FIG. 4, the latch built-in analog interpolator 11 detects a rising edge of the rectangular signal as a delay time T _2a of the input signal with respect to the rectangular signal and then detects a rising edge of the input signal. Detect time.
The latch built-in analog interpolator 11 holds the detection voltage V _2a corresponding to the delay time T _2a , and outputs the held detection voltage V _2a to the frequency calculation processing circuit 9.
The latch integrated analog interpolator 11 detects a delay time T _2a of the input signal to the rectangular signal, and outputs a latch signal L _a frequency calculation processing circuit 9.

The latch-embedded analog interpolator 12 outputs the control signal F from the frequency calculation processing circuit 9 so that the held detection voltage _V2b is reset to zero and then the rectangular signal output from the frequency divider 10 When the input signal is input, the falling edge of the rectangular signal and the rising edge of the input signal are detected.
As shown in FIG. 4, the latch-embedded analog interpolator 12 detects the falling edge of the rectangular signal as a delay time T _2b of the input signal until the rising edge of the input signal is detected. Detect the time.
The latch built-in analog interpolator 12 holds the detection voltage V _2b corresponding to the delay time T _2b , and outputs the held detection voltage V _2b to the frequency calculation processing circuit 9.
Further, when the latch built-in analog interpolator 12 detects the delay time T _2b of the input signal with respect to the rectangular signal, it outputs the latch signal L _b to the frequency calculation processing circuit 9.

As is apparent from the above, according to the second embodiment, the divide-by-two 10 that divides the frequency of the clock signal by two is provided, and the analog interpolator 11 with a latch is divided into two by the divide-by-two 10. A clock in which a time (delay time T _2a ) from when the frequency-divided clock signal is input to when the input signal is input is detected, and the analog interpolator 12 with a latch is frequency-divided by 2 by the frequency divider 10 Since the time (delay time T _2b ) from the end of the signal until the input signal is input is detected, the latch built-in analog interpolator 11 and the latch built-in analog interpolator 12 are surely provided for each cycle of the clock signal. There is an effect that can be operated alternately.

Embodiment 3 FIG.
FIG. 5 is a block diagram showing the analog interpolators 7 and 11 with a built-in latch of the frequency measuring circuit according to the third embodiment of the present invention.
In FIG. 5, a constant current source 21 is a current source that outputs a constant current (constant current).
The edge detection circuit 22 performs processing for detecting the rising edge of the clock signal (or the rectangular signal output from the frequency divider 10) and the rising edge of the input signal.

The charge charging circuit 23 is fixed after the rising edge of the clock signal (or the rectangular signal output from the frequency divider 10) is detected by the edge detection circuit 22 until the rising edge of the input signal is detected. A process of charging a charge with a constant current output from the current source 21 is performed.
Further, the charge charging circuit 23 uses a detection voltage V _2a that is a voltage value corresponding to the charge amount of the charge as the delay time T _2a of the input signal with respect to the clock signal (or the rectangular signal output from the frequency divider 10). while output to the frequency calculation circuit 9, when the latch signal L _b from the control signal E from the frequency calculation processing circuit 9 (latch integrated analog interpolator 8,12 is output to the frequency calculation circuit 9, a frequency calculation processing circuit When a signal (output from 9) is output, a process of discharging the charged charge is performed.

The switch 24 of the charge charging circuit 23 is closed when the edge detection circuit 22 detects the rising edge of the clock signal (or the rectangular signal output from the frequency divider 10), and the edge detection circuit 22 receives the input signal. This is a switching element that is opened when a rising edge is detected.
The capacitor 25 of the charge charging circuit 23 is an element that charges a charge with a constant current output from the constant current source 21 when the switch 24 is closed.

The switch 26 of the charge charging circuit 23 is a switching element for closing the charge when the control signal E is output from the frequency calculation processing circuit 9 and discharging the charge charged in the capacitor 25.
The latch circuit 27 is a clock signal by the edge detection circuit 22 from the rising edge is detected (or, the rectangular signal output from the 1/2 frequency divider 10), the rising edge of the input signal is detected, the latch signal L _a Is output to the frequency calculation processing circuit 9.

FIG. 6 is a block diagram showing the analog interpolators 8 and 12 with a built-in latch of the frequency measuring circuit according to the third embodiment of the present invention.
In FIG. 6, a constant current source 31 is a current source that outputs a constant current (constant current).
The edge detection circuit 32 performs processing for detecting the rising edge of the clock signal (or the falling edge of the rectangular signal output from the frequency divider 10) and the rising edge of the input signal.

In the charge charging circuit 33, the edge detection circuit 32 detects the rising edge of the clock signal (or the falling edge of the rectangular signal output from the frequency divider 10) until the rising edge of the input signal is detected. In the meantime, the process of charging the electric charge with the constant current output from the constant current source 31 is performed.
In addition, the charge charging circuit 33 uses a detection voltage V _2b that is a voltage value according to the charge amount as the delay time T _2b of the input signal with respect to the clock signal (or the rectangular signal output from the frequency divider 10). while output to the frequency calculation circuit 9, when the latch signal L _a from a control signal F (latch integrated analog interpolator 7, 11 from the frequency calculation processing circuit 9 is output to the frequency calculation circuit 9, a frequency calculation processing circuit When a signal (output from 9) is output, a process of discharging the charged charge is performed.

The switch 34 of the charge charging circuit 33 is closed when the edge detection circuit 32 detects the rising edge of the clock signal (or the falling edge of the rectangular signal output from the frequency divider 10), and the edge detection circuit This is a switching element that is opened when a rising edge of the input signal is detected by 32.
The capacitor 35 of the charge charging circuit 33 is an element that charges a charge with a constant current output from the constant current source 31 when the switch 34 is closed.

The switch 36 of the charge charging circuit 33 is a switching element that is closed when the control signal F is output from the frequency calculation processing circuit 9 and discharges the charge charged in the capacitor 35.
The latch circuit 37 detects the rising edge of the input signal after the rising edge of the clock signal (or the falling edge of the rectangular signal output from the frequency divider 10) is detected by the edge detection circuit 32. Processing to output the latch signal _Lb to the frequency calculation processing circuit 9 is performed.

In the first and second embodiments, the latch built-in analog interpolators 7 and 8 (or 11 and 12) have a delay time T _2a of the input signal with respect to the clock signal (or the rectangular signal output from the divide-by-2 divider 10). , T _2b has been shown to output the detection voltages V _2a , V _2b to the frequency calculation processing circuit 9, but in the third embodiment, latch-equipped analog interpolators 7, 8 (or 11, 12) The specific structure of will be described.

When the edge detection circuit 22 of the latch-embedded analog interpolators 7 and 11 receives a clock signal (or a rectangular signal output from the 2 frequency divider 10) and an input signal, the clock signal (or the 2 frequency divider 10) is input. The rising edge of the rectangular signal output from (1) and the rising edge of the input signal are detected.
The switch 24 of the charge charging circuit 23 in the latched analog interpolators 7 and 11 is closed when the edge detection circuit 22 detects the rising edge of the clock signal (or the rectangular signal output from the divide-by-2 divider 10). .
Thereby, the capacitor 25 of the charge charging circuit 23 in the analog interpolators 7 and 11 with a built-in latch is connected to the constant current source 21, so that the capacitor 25 is charged with the constant current output from the constant current source 21.

The switch 24 of the charge charging circuit 23 in the latch built-in analog interpolators 7 and 11 is opened when the edge detection circuit 22 detects the rising edge of the input signal.
As a result, the capacitor 25 of the charge charging circuit 23 in the analog interpolators 7 and 11 with a built-in latch is disconnected from the constant current source 21, so that the charge charging by the constant current output from the constant current source 21 is stopped.
The amount of charge in the capacitor 25 of the charge charging circuit 23 corresponds to the delay time _T2a of the input signal with respect to the clock signal (or the rectangular signal output from the frequency divider 10), and depends on the amount of charge charged. A detection voltage V _2a that is a voltage value is output to the frequency calculation processing circuit 9.

The latch circuits 27 of the latch-integrated analog interpolators 7 and 11 detect the rising edge of the clock signal (or the rectangular signal output from the frequency divider 10) by the edge detection circuit 22 and then the rising edge of the input signal. There Once detected, it outputs a latch signal L _a logic High frequency calculation processing circuit 9.
Switch 26 of the charge storage circuit 23 in the latch internal analog interpolator 7, 11 control the frequency calculation circuit 9 signals E (latch integrated analog interpolator 8,12 from a logic High latch signal _{L b} is the frequency calculation processing circuit 9 When a signal output from the frequency calculation processing circuit 9 is output, the closed state is established.
As a result, both ends of the capacitor 25 of the charge charging circuit 23 are grounded, so that the charge charged in the capacitor 25 is discharged.
Incidentally, the latch circuit 27, when the above control signal E from the frequency calculation processing circuit 9 is outputted, a latch signal L _a is changed to a logic Low reset.

When the edge detection circuit 32 of the latch-embedded analog interpolators 8 and 12 receives a clock signal (or a rectangular signal output from the frequency divider 10) and an input signal, the rising edge (or 2 minutes) of the clock signal is input. The falling edge of the rectangular signal output from the frequency divider 10 and the rising edge of the input signal are detected.
When the edge detection circuit 32 detects the rising edge of the clock signal (or the falling edge of the rectangular signal output from the frequency divider 10), the switch 34 of the charge charging circuit 33 in the analog interpolators 8 and 12 with built-in latches. Closed.
As a result, the capacitor 35 of the charge charging circuit 33 in the latch built-in analog interpolators 8 and 12 is connected to the constant current source 31, so that the capacitor 35 is charged with the constant current output from the constant current source 31.

The switch 34 of the charge charging circuit 33 in the latch built-in analog interpolators 8 and 12 is opened when the edge detection circuit 32 detects the rising edge of the input signal.
As a result, the capacitor 35 of the charge charging circuit 33 in the latch-embedded analog interpolators 8 and 12 is disconnected from the constant current source 31, so that charging of the charge by the constant current output from the constant current source 31 is stopped.
The charge amount in the capacitor 35 of the charge charging circuit 33 corresponds to the delay time T _2b of the input signal with respect to the clock signal (or the rectangular signal output from the divide-by-2 divider 10), and depends on the charge amount. A detection voltage V _2b that is a voltage value is output to the frequency calculation processing circuit 9.

The latch circuits 37 of the analog interpolators 8 and 12 with built-in latches are input after the edge detection circuit 32 detects the rising edge of the clock signal (or the falling edge of the rectangular signal output from the frequency divider 10). When a rising edge of the signal is detected, and outputs a latch signal L _b of logic High frequency calculation processing circuit 9.
Switch 36 of the charge storage circuit 33 in the latch internal analog interpolator 8 and 12, the control from the frequency calculation circuit 9 signals F (latch integrated analog interpolator 7, 11 from a logic High latch signal _{L a} frequency calculation processing circuit 9 When a signal output from the frequency calculation processing circuit 9 is output, the closed state is established.
As a result, both ends of the capacitor 35 of the charge charging circuit 33 are grounded, so that the charge charged in the capacitor 35 is discharged.
Incidentally, the latch circuit 37, when the control signal F from the frequency calculation processing circuit 9 is output, the latch signal L _b is changed to a logic Low reset.

As apparent from the above, the analog interpolators 7 and 11 with latches are configured as shown in FIG. 5 and the analog interpolators 8 and 12 with latches are configured as shown in FIG. 6 and are output from the latch circuits 27 and 37. Referring to the logic of the latch signals L _b and L _b , unlike the conventional analog interpolators 107 and 108 (see FIG. 9), the input to the clock signal (or the rectangular signal output from the divide-by-2 divider 10). There is an effect that it is possible to determine whether or not the signal delay times T _2a and T _2b can be normally detected.
In the conventional example of FIG. 9, when the input signal which is a pulse wave is turned off between the rising edge of the clock signal and the rising edge of the input signal, it is determined whether or not the non-zero detection voltage is a correct value. I can't judge.

Embodiment 4 FIG.
FIG. 7 is a block diagram showing the analog interpolators 7 and 11 with a built-in latch of the frequency measuring circuit according to the fourth embodiment of the present invention.
In FIG. 7, a constant current source 41 is a current source that outputs a constant current (constant current).
When the latch circuit 42 detects the rising edge of the clock signal (or the rectangular signal output from the frequency divider 10), the latch circuit 42 outputs a logic high latch signal to the switch 45 and the AND circuit 49 of the charge charging circuit 44. (when the latch signal L _b of the logic from the latch integrated analog interpolator 8,12 High is output to the frequency calculation circuit 9, the signal output from the frequency calculation processing circuit 9) from the calculation processing circuit 9 control signal E of Upon receipt, the latch signal output to the switch 45 and the AND circuit 49 of the charge charging circuit 44 is changed to logic low. The latch circuit 42 constitutes a first latch circuit.

When the latch circuit 43 detects the rising edge of the input signal, the latch circuit 43 outputs a logic high latch signal to the switch 46 and the AND circuit 49 of the charge charging circuit 44, and the control signal E (the latch built-in analog interpolator 8) from the frequency calculation processing circuit 9. , 12 receives a signal output from the frequency calculation processing circuit 9 when the logic high latch signal L _b is output to the frequency calculation processing circuit 9, the switch 46 and the AND circuit 49 of the charge charging circuit 44 receive the signal. A process of changing the output latch signal to logic low is performed. The latch circuit 43 constitutes a second latch circuit.

The charge charging circuit 44 performs a process of charging a charge with a constant current output from the constant current source 41 during a period in which the logic High latch signal is output from the latch circuits 42 and 43.
In addition, the charge charging circuit 44 uses a detection voltage V _2a that is a voltage value corresponding to the charge amount as a delay time T _2a of the input signal with respect to the clock signal (or the rectangular signal output from the frequency divider 10). while output to the frequency calculation circuit 9, when the latch signal L _b of logic High from the control signal E (latch integrated analog interpolator 8,12 from the frequency calculation processing circuit 9 is output to the frequency calculation circuit 9, a frequency When a signal output from the calculation processing circuit 9 is output, a process of discharging the charged charge is performed.

The switch 45 of the charge charging circuit 44 is a switching element that is in a closed state when a logic High latch signal is output from the latch circuit 42 and is in an open state when a logic Low latch signal is output from the latch circuit 42.
The switch 46 of the charge charging circuit 44 is a switching element that is in a closed state when a logic High latch signal is output from the latch circuit 43 and is in an open state when a logic Low latch signal is output from the latch circuit 43.
The capacitor 47 of the charge charging circuit 44 is an element that charges a charge by a constant current output from the constant current source 41 when the switches 45 and 46 are closed.

The switch 48 of the charge charging circuit 44 is a switching element that is closed when the control signal E is output from the frequency calculation processing circuit 9 and discharges the charge charged in the capacitor 47.
When the latch signal from the AND circuit 49 latch circuits 42 and 43 a logic High is output, and outputs a latch signal _{L a} logic High frequency calculation processing circuit 9, from at least one of the latch circuit 42 or latch circuit 43 logic When the latch signal of Low is outputted, and carries out a process of changing a latch signal L _a being output to the frequency calculation processing circuit 9 to the logic Low.

FIG. 8 is a block diagram showing the analog interpolators 8 and 12 with a built-in latch of the frequency measuring circuit according to the fourth embodiment of the present invention.
In FIG. 8, a constant current source 51 is a current source that outputs a constant current (constant current).
When the latch circuit 52 detects the rising edge of the clock signal (or the falling edge of the rectangular signal output from the frequency divider 10), the latch signal of logic High is sent to the switch 55 and the AND circuit 59 of the charge charging circuit 54. and outputs, when the latch signal L _a logic High from the control signal F (latch integrated analog interpolator 7, 11 from the frequency calculation processing circuit 9 is output to the frequency calculation circuit 9, is output from the frequency calculation processing circuit 9 Signal), the latch signal output to the switch 55 and the AND circuit 59 of the charge charging circuit 54 is changed to logic low. Note that the latch circuit 52 constitutes a first latch circuit.

When the latch circuit 53 detects the rising edge of the input signal, the latch circuit 53 outputs a logic high latch signal to the switch 56 and the AND circuit 59 of the charge charging circuit 54, and the control signal F (the latch-equipped analog interpolator 7) is output from the frequency calculation processing circuit 9. , when the latch signal L _a logic High is output to the frequency calculation circuit 9 from 11, when receiving the signal) outputted from the frequency calculation processing circuit 9, the switch 56 and the aND circuit 59 of the charge storage circuit 54 A process of changing the output latch signal to logic low is performed. Note that the latch circuit 53 constitutes a second latch circuit.

The charge charging circuit 54 performs a process of charging a charge with a constant current output from the constant current source 51 during a period in which a latch signal of logic high is output from the latch circuits 52 and 53.
Further, the charge charging circuit 54 uses a detection voltage V _2b which is a voltage value corresponding to the charge amount of the charge as the delay time T _2b of the input signal with respect to the clock signal (or the rectangular signal output from the frequency divider 10). while output to the frequency calculation circuit 9, when the latch signal L _a logic High from the control signal F (latch integrated analog interpolator 7, 11 from the frequency calculation processing circuit 9 is output to the frequency calculation circuit 9, a frequency When a signal output from the calculation processing circuit 9 is output, a process of discharging the charged charge is performed.

The switch 55 of the charge charging circuit 54 is a switching element that is closed when a logic High latch signal is output from the latch circuit 52 and is open when a logic Low latch signal is output from the latch circuit 52.
The switch 56 of the charge charging circuit 54 is a switching element that is in a closed state when a logic High latch signal is output from the latch circuit 53 and is in an open state when a logic Low latch signal is output from the latch circuit 53.
The capacitor 57 of the charge charging circuit 54 is an element that charges a charge by a constant current output from the constant current source 51 when the switches 55 and 56 are closed.

The switch 58 of the charge charging circuit 54 is a switching element that is closed when the control signal F is output from the frequency calculation processing circuit 9 and discharges the charge charged in the capacitor 57.
When the logic High latch signal is output from the latch circuits 52 and 53, the AND circuit 59 outputs the logic High latch signal L _b to the frequency calculation processing circuit 9, and logic is output from at least one of the latch circuit 52 or the latch circuit 53. When the latch signal of Low is outputted, and carries out a process of changing a latch signal L _b which is output to the frequency calculation processing circuit 9 to the logic Low.

In the first and second embodiments, the latch built-in analog interpolators 7 and 8 (or 11 and 12) have a delay time T _2a of the input signal with respect to the clock signal (or the rectangular signal output from the divide-by-2 divider 10). , T _2b has been shown to output the detection voltages V _2a , V _2b to the frequency calculation processing circuit 9, but in the fourth embodiment, latch-equipped analog interpolators 7, 8 (or 11, 12) The specific structure of will be described.

The latch circuit 42 of the latch-integrated analog interpolators 7 and 11 receives the clock signal (or the rectangular signal output from the divide-by-2 divider 10) and receives the clock signal (or the rectangle output from the divide-by-10 divider 10). When a rising edge of the signal) is detected, a logic high latch signal is output to the switch 45 and the AND circuit 49 of the charge charging circuit 44.
When the latch circuit 43 of the latch built-in analog interpolators 7 and 11 detects the rising edge of the input signal, the latch circuit 43 outputs a logic High latch signal to the switch 46 and the AND circuit 49 of the charge charging circuit 44.

The switch 45 of the charge charging circuit 44 in the latch built-in analog interpolators 7 and 11 is closed when a latch signal of logic high is output from the latch circuit 42.
Further, the switch 46 of the charge charging circuit 44 in the latch built-in analog interpolators 7 and 11 is closed when a latch signal of logic high is output from the latch circuit 43.
When the switches 45 and 46 are closed, the capacitor 47 of the charge charging circuit 44 is connected to the constant current source 41, so that the capacitor 47 is charged with the constant current output from the constant current source 41.

AND circuit 49 latches internal analog interpolator 7, 11, the latch signal from the latch circuits 42 and 43 of the logic High is output, and outputs a latch signal _{L a} logic High frequency calculation processing circuit 9.
The latch circuit 42 of the latch internal analog interpolators 7 and 11 outputs the control signal E from the frequency calculation processing circuit 9 (the logic high latch signal L _b is output from the latch internal analog interpolators 8 and 12 to the frequency calculation processing circuit 9. (The signal output from the frequency calculation processing circuit 9), the latch signal output to the switch 45 and the AND circuit 49 of the charge charging circuit 44 is changed to logic low.
The latch circuit 43 of the latch built-in analog interpolators 7 and 11 also receives the control signal E from the frequency calculation processing circuit 9 and outputs the latch signal output to the switch 46 and the AND circuit 49 of the charge charging circuit 44. To logic low.

The switch 45 of the charge charging circuit 44 in the latch built-in analog interpolators 7 and 11 is opened when a latch signal of logic low is output from the latch circuit 42.
Further, the switch 46 of the charge charging circuit 44 in the latch built-in analog interpolators 7 and 11 is opened when a logic low latch signal is output from the latch circuit 43.
When the switches 45 and 46 are in the open state, the capacitor 47 of the charge charging circuit 44 is disconnected from the constant current source 41, so that charge charging by the constant current output from the constant current source 41 is stopped.
The charge amount in the capacitor 47 of the charge charging circuit 44 corresponds to the delay time T _2a of the input signal with respect to the clock signal (or the rectangular signal output from the divide-by-2 divider 10), and depends on the charge amount. A detection voltage V _2a that is a voltage value is output to the frequency calculation processing circuit 9.

AND circuit 49 latches internal analog interpolator 7, 11, the latch signal from the latch circuits 42 and 43 of the logic Low is output, and outputs a latch signal _{L a} logic Low frequency calculation processing circuit 9.
Switch charge the charging circuit 44 in the latch internal analog interpolator 7, 11 48, the control signal E from the frequency calculation processing circuit 9 (latch integrated analog interpolator 8,12 from a logic High latch signal _{L b} is the frequency calculation processing circuit 9 When a signal output from the frequency calculation processing circuit 9 is output, the closed state is established.
As a result, both ends of the capacitor 47 of the charge charging circuit 44 are grounded, so that the charge charged in the capacitor 47 is discharged.

The latch circuit 52 of the analog interpolators 8 and 12 with a built-in latch inputs a clock signal (or a rectangular signal output from the divide-by-2 divider 10) and outputs a rising edge of the clock signal (or output from the divide-by-2 divider 10) When the detection signal (a falling edge of the rectangular signal) is detected, a logic High latch signal is output to the switch 55 and the AND circuit 59 of the charge charging circuit 54.
When the latch circuit 53 of the latch built-in analog interpolators 8 and 12 detects the rising edge of the input signal, it outputs a logic high latch signal to the switch 56 and the AND circuit 59 of the charge charging circuit 54.

The switch 55 of the charge charging circuit 54 in the latch built-in analog interpolators 8 and 12 is closed when a latch signal of logic high is output from the latch circuit 52.
Further, the switch 56 of the charge charging circuit 54 in the latch-embedded analog interpolators 8 and 12 is closed when a latch signal of logic High is output from the latch circuit 53.
When the switches 55 and 56 are closed, the capacitor 57 of the charge charging circuit 54 is connected to the constant current source 51, so that the capacitor 57 is charged with the constant current output from the constant current source 51.

The AND circuit 59 of the latch built-in analog interpolators 8 and 12 outputs the logic High latch signal _Lb to the frequency calculation processing circuit 9 when the latch signals 52 and 53 output the logic High latch signal.
The latch circuit latches integrated analog interpolator 8,12 52 latch signal L _a logic High from the control signal F (latch integrated analog interpolator 7, 11 from the frequency calculation processing circuit 9 is output to the frequency calculation processing circuit 9 (The signal output from the frequency calculation processing circuit 9), the latch signal output to the switch 55 and the AND circuit 59 of the charge charging circuit 54 is changed to logic low.
In addition, the latch circuit 53 of the analog interpolators 8 and 12 with latches also receives the control signal F from the frequency calculation processing circuit 9 and outputs the latch signal output to the switch 56 and the AND circuit 59 of the charge charging circuit 54. To logic low.

The switch 55 of the charge charging circuit 54 in the latch built-in analog interpolators 8 and 12 is opened when a latch signal of logic low is output from the latch circuit 52.
Further, the switch 56 of the charge charging circuit 54 in the analog interpolators 8 and 12 with a latch is opened when a latch signal of logic low is output from the latch circuit 53.
When the switches 55 and 56 are in the open state, the capacitor 57 of the charge charging circuit 54 is disconnected from the constant current source 51, so that charge charging by the constant current output from the constant current source 51 is stopped.
The charge amount in the capacitor 57 of the charge charging circuit 54 corresponds to the delay time T _2b of the input signal with respect to the clock signal (or the rectangular signal output from the divide-by-2 divider 10), and depends on the charge amount. A detection voltage V _2b that is a voltage value is output to the frequency calculation processing circuit 9.

The AND circuit 59 of the latch built-in analog interpolators 8 and 12 outputs a logic low latch signal _Lb to the frequency calculation processing circuit 9 when a logic low latch signal is output from the latch circuits 52 and 53.
Switch 58 of the charge storage circuit 54 in the latch internal analog interpolator 8 and 12, the control from the frequency calculation circuit 9 signals F (latch integrated analog interpolator 7, 11 from a logic High latch signal _{L a} frequency calculation processing circuit 9 When a signal output from the frequency calculation processing circuit 9 is output, the closed state is established.
As a result, both ends of the capacitor 57 of the charge charging circuit 54 are grounded, so that the charge charged in the capacitor 57 is discharged.

As apparent from the above, the analog interpolators 7 and 11 with a built-in latch are configured as shown in FIG. 7, the analog interpolators 8 and 12 with a built-in latch are configured as shown in FIG. 8, and are output from the AND circuits 49 and 59. Referring to the logic of the latch signals L _b and L _b , unlike the conventional analog interpolators 107 and 108 (see FIG. 9), the input to the clock signal (or the rectangular signal output from the divide-by-2 divider 10). There is an effect that it is possible to determine whether or not the signal delay times T _2a and T _2b can be normally detected.

  DESCRIPTION OF SYMBOLS 1 Synchronous circuit (synchronous signal production | generation means) 2 AND circuit (clock signal counting means) 3 Counter (clock signal counting means) 4 AND circuit (input signal counting means) 5 Counter (input signal counting means), 6 Analog Interpolator (time difference detecting means), 7 latch built-in analog interpolator (first delay time detecting means), 8 latch built-in analog interpolator (second delay time detecting means), 9 frequency calculation processing circuit (frequency calculating means) 10 2 frequency divider (frequency dividing means), 11 latch built-in analog interpolator (first delay time detecting means), 12 latch built-in analog interpolator (second delay time detecting means), 21, 31 constant current Source, 22, 32 edge detection circuit, 23, 33 charge charging circuit, 24, 34 switch, 25, 35 capacitor, 26, 36 switch, 27, 37 Latch circuit, 41, 51 Constant current source, 42, 52 Latch circuit (first latch circuit), 43, 53 Latch circuit (second latch circuit), 44, 54 Charge charging circuit, 45, 46, 55, 56 Switch, 47, 57 Capacitor, 48, 58 Switch, 49, 50 AND circuit, 101 Processing circuit, 102 Synchronization circuit, 103, 105 AND circuit, 104, 106 Counter, 107, 108 Analog interpolator, 111 Edge detection circuit, 112 Constant current source, 113, 115 switch, 114 capacitor.

Claims (4)

  During a period when the input signal is significant, a synchronization signal generating means for generating a synchronization signal synchronized with the input signal and outputting the synchronization signal, and a period during which the synchronization signal is output from the synchronization signal generating means The clock signal counting means for counting the clock signal, the input signal counting means for counting the input signal during the period in which the synchronization signal is output from the synchronization signal generating means, and the synchronization signal output from the synchronization signal generating means A time difference detecting means for detecting a time difference between the signal and the clock signal; a first delay time detecting means for detecting a delay time of the input signal with respect to the clock signal; and a delay time of the input signal with respect to the clock signal. Second delay time detection means, delay time detection processing by the first delay time detection means, and delay time by the second delay time detection means The detection process is alternately performed every period of the clock signal, and the delay time detected by the first delay time detection means or the second delay time detection means and the time difference detected by the time difference detection means A frequency measurement circuit comprising frequency calculation means for calculating the frequency of the input signal using the clock signal counting means and the counting result of the input signal counting means.   Frequency dividing means for dividing the frequency of the clock signal by two is provided. The first delay time detecting means receives the clock signal whose frequency is divided by 2 by the frequency dividing means and then inputs the input signal. The time until the input signal is input from the end of the clock signal whose frequency is divided by 2 by the frequency dividing means is detected as the delay time. The frequency measurement circuit according to claim 1, wherein the frequency measurement circuit is detected as: The first delay time detecting means includes a constant current source that outputs a constant current, an edge detection circuit that detects an edge of the clock signal and an edge of the input signal, and an edge of the clock signal detected by the edge detection circuit. Until the edge of the input signal is detected, a charge charging circuit that charges a charge with a constant current output from the constant current source, and an edge of the clock signal detected by the edge detection circuit, When the edge of the input signal is detected, it is composed of a latch circuit that outputs a latch signal,
The second delay time detection means includes a constant current source that outputs a constant current, an edge detection circuit that detects an edge of the clock signal and an edge of the input signal, and an edge of the clock signal detected by the edge detection circuit. Until the edge of the input signal is detected, a charge charging circuit that charges a charge with a constant current output from the constant current source, and an edge of the clock signal detected by the edge detection circuit, When the edge of the input signal is detected, it is composed of a latch circuit that outputs a latch signal,
The charge charging circuit of the first delay time detecting means outputs a voltage value corresponding to the charge amount of the charge as the delay time of the input signal with respect to the clock signal, while the latch of the second delay time detecting means When a latch signal is output from the circuit, the charged charge is discharged,
The charge charging circuit of the second delay time detecting means outputs a voltage value corresponding to the charge amount of the charge as the delay time of the input signal with respect to the clock signal, while the latch of the first delay time detecting means 2. The frequency measurement circuit according to claim 1, wherein when the latch signal is output from the circuit, the charged electric charge is discharged. The first delay time detecting means detects a constant current source that outputs a constant current, a first latch circuit that outputs a latch signal when an edge of a clock signal is detected, and a latch signal when an edge of an input signal is detected. A second latch circuit for outputting, a charge charging circuit for charging a charge with a constant current output from the constant current source during a period in which a latch signal is output from the first and second latch circuits, and When a latch signal is output from the first and second latch circuits, an AND circuit that outputs the latch signal is configured.
The second delay time detection means detects the edge of the constant current source that outputs a constant current, the first latch circuit that outputs the latch signal when the edge of the clock signal is detected, and the latch signal when the edge of the input signal is detected. A second latch circuit for outputting, a charge charging circuit for charging a charge with a constant current output from the constant current source during a period in which a latch signal is output from the first and second latch circuits, and When the latch signal is output from the first and second latch circuits, the AND circuit outputs the latch signal.
The charge charging circuit of the first delay time detecting means outputs a voltage value corresponding to the charge amount of the charge as the delay time of the input signal with respect to the clock signal, while the AND of the second delay time detecting means. When a latch signal is output from the circuit, the charged charge is discharged,
The first and second latch circuits and the AND circuit of the first delay time detection unit stop outputting the latch signal when the latch signal is output from the AND circuit of the second delay time detection unit,
The charge charging circuit of the second delay time detecting means outputs a voltage value corresponding to the charge amount of the charge as the delay time of the input signal with respect to the clock signal, while the AND of the first delay time detecting means. When a latch signal is output from the circuit, the charged charge is discharged,
The first and second latch circuits and the AND circuit of the second delay time detecting means stop outputting the latch signal when the latch signal is outputted from the AND circuit of the first delay time detecting means. The frequency measurement circuit according to claim 1.

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