JPS6298265A - Speed detecting device - Google Patents

Abstract

PURPOSE:To detect speeds from a low speed to a high speed by generating an interruption signal at every sampling period synchronized with an encoder signal and using and operating two program timer alternately at intervals of the interruption signal. CONSTITUTION:A program timer 7a inputs a signal GA which is the output of a frequency dividing circuit 5 and an interruption signal generating circuit 10a outputs an interruption signal IRQA and a status signal STSA indicating the occurrence of an interruption at the rise of the signal GA. Further, a counter 9a is reset when the signal GA falls and counts the cock signal of a microcomputer 14 in a low-level section. A counter 8a counts an encoder pulse S1 at low level section. A program timer 7b, on the other hand, has the same constitution with the timer A7a and inputs a signal GB which is the inverted signal of the signal GA to output an interruption signal IRQB and a status signal STSB. Then, the microcomputer 14 inputs the signals STSA and STSB to judge which program timer initiates an interruption and calculate the speed from a specific expression.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital speed detection device for an electric motor using an incremental encoder.

[Background of the invention]

As a conventional speed detection device, Japanese Patent Application Laid-Open No. 58-103666
As described in the above publication, there is a method of accurately detecting the speed from the sample period T synchronized with encoder pulses and the number N of pulses entering that period. However, in this method, when speed detection is performed using a programmable timer that is generally available on the market, especially at low speeds, N,
It takes some time to count T, input the data into the microcomputer, and start counting again with the program timer. As a result of this summer, there is a problem in that the speed can only be detected in the two-pulse cycle of the lowest encoder signal. In other words, it is necessary to detect N and T in one pulse section and input that data into the microcomputer in the next one pulse section, so that the number of pulses N is 2.
There is a problem in that it can only be detected in the above range. Note that in speed control of the electric motor, the longer the sampling period T corresponding to the speed detection period becomes, the worse the control characteristics become. For this reason.

Compared to a method that detects speed every pulse period (N = 1), the conventional method requires two pulses, so to obtain the same speed detection period, a high-frequency encoder that outputs twice the number of pulses per rotation is required. It becomes necessary.

This results in an expensive device. Furthermore, since the encoder pulses are of high frequency, there is a problem in that signal transmission becomes difficult.

[Purpose of the invention]

The object of the present invention is to eliminate the drawbacks of the prior art described above, and to provide a digital system that can detect speed in one pulse cycle of the encoder signal at low speeds with a simple control circuit, and that can continuously detect speeds from low speeds to high speeds with high accuracy. An object of the present invention is to provide a type speed detection device.

[Summary of the invention]

To achieve this object, the present invention generates an interrupt signal at every sampling period T synchronized with the encoder signal, and uses two program timers to operate alternately between interrupt signals. In other words, input the sampling period TB and the number of pulses counted by program timer B in the period in which program timer A is operating, and input the sampling period T^ and the number of pulses counted in program A in the period in which program timer B is operating. N^
is input, and the speed is detected based on this data.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIG.

The one-shot multi 2 operates in synchronization with the rise of the output 82 signal of the AND circuit 1 inputting the encoder pulse S1. In one shot multi 2, constant pulse width Ts
A signal S3 is output. Further, the delay circuit 3 delays the 83 signal by approximately the encoder pulse width and outputs it as the S4 signal. Note that the 84 signal is inverted by the inverting circuit 4 to become the S5 signal, which is input to the AND circuit 1.

In addition, the frequency dividing circuit 5 outputs a GA multiplied signal whose frequency is 1/2 of the S2 signal, and the inverting circuit 6 inverts the OA signal and outputs the GA signal.
It is output as a B signal.

Next, the internal configuration of the program timer A7a, which is usually commercially available as a peripheral element of a microprocessor, includes counters 8a and 9a, an interrupt signal generation circuit 10a, and an AND circuit 1.
1a, 12a, and an inversion circuit 13a. Note that the program timer A7a operates based on the GA multiplied signal that is the output of the frequency dividing circuit 5, and
0a is an OA double signal input, and at the rising edge of this signal, an interrupt signal IRQA and a status signal 5TSA indicating that an interrupt has occurred are output. In addition, the counter 9a is GA
Reset at the falling edge of the double signal, and count the clock signal of the microcomputer 14 (usually at a frequency of IMHz or higher) in the OA double signal low level section. Note that the counter 8a is reset at the falling edge of the GA multiplied signal, and counts the GA multiplied signal low level section encoder pulse S1.

On the other hand, the program timer B7b is the program timer A7.
It has exactly the same structure and operates in the same way as a, and is composed of counters 8b and 9b, an interrupt signal generation circuit 10b, AND circuits 11b and 12b, and an inverting circuit 13b.

The program timer B7b receives an OB double signal, which is an inverted OA double signal, and operates based on this signal. Also, program timer data output N^, T
^, 5TSA, Na, TB, and 5TSB are connected to the data bus of the microcomputer 14, and the interrupt signals IRQA and IRQB are connected to the microcomputer's interrupt IRQ terminal by a wired OR circuit.

In this way, interrupt signals of program timer A and program timer B are generated alternately every sampling period T between 82 signals.

Next, a description will be given of the sampling period T and the counting operation of the number N of pulses of the 81 signal that falls within that period. First, the AND circuit 11a of the program timer A operates during the GA times signal low level period, and the counter 8a is reset once at the falling edge of the GA times signal, as shown in FIG. , the GA double signal high level section, and the count value N^ are held.

Similarly, in measuring the sampling period T^, the counter 9a is reset once at the falling edge of the GA double signal, counts the clock signal of the microcomputer in the low level section of GAffi, and holds the count value T^ in the high level section of the GA double signal. Ru.

On the other hand, the measurement of the number of pulses NB and the sampling period Ta by the program timer B also operates in the GB multiple signal low level section as shown in FIG. In this way, the measurement of the encoder pulse number N and the sampling period T is also performed by alternately operating the program timer A and the program timer B for each S2 signal. Next, the speed calculation processing performed by the microcomputer 14 is shown in FIG. First, when an interrupt is input from the program timer, status registers 5TSA and 5TSB indicating the interrupt generation status are input, and it is determined which timer the interrupt is from. For interrupts from program timer A, enter N^ and T^ data, N=N^, T=
Let's say T^. On the other hand, in the case of an interrupt from program timer B, input Na and Ta data, N = Na, T:
Let it be Ta. Thereafter, the microcomputer calculates and obtains the speed ω using equation (1).

ωr ” K· − (1) However, K is a proportionality constant determined by the number of encoder pulses per rotation.

According to the embodiment of the present invention described above, program timer A and program timer B are operated alternately every speed detection sampling period T, so that the microcomputer can control It is possible to prevent the effects of dead time until data is input.

As a result, there is an effect that the speed can be detected even in one continuous pulse (N=1) period at low speed.

〔Effect of the invention〕

According to the present invention, by simply providing two identical program timers and operating them alternately every sampling period T, N, T,'
- It is possible to prevent dead time in one pulse section when capturing evening light. As a result, one period (N
= 1), the speed can be detected, and the speed can be detected continuously with high accuracy from the high speed region to the low speed region where the number of pulses N=1.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a time chart showing the operation of FIG. 1, and FIG. 3 is a flow chart showing software processing of the microcomputer shown in FIG. 1...AND circuit, 2...One-shot multi, 3
... Delay circuit, 5... Frequency dividing circuit, 4.6... Inverting circuit, 1st (¥)

Claims (1)

[Claims] 1. A program timer that generates an interrupt signal every arbitrary sampling period T synchronized with encoder pulses and measures the interrupt period T and the number N of encoder pulses that enter the interrupt signal period, and a N/T
In a speed detection device comprising a microcomputer that calculates the speed of The program timer A and the program timer B are operated alternately between each interrupt signal, and the above N and T are counted.
A speed detection device characterized by detecting speed by performing N/T calculation.