JPH0528526Y2 - - Google Patents

Description

[Detailed description of the invention] <Industrial application field> This invention relates to a signal waveform display device that displays the waveform of an input signal, and particularly relates to a signal waveform display device that has a simple configuration and does not generate jitter. .

<Prior Art> In recent years, as signal waveform display devices for observing waveforms, devices have been used that temporarily convert signals into digital signals, store them, and display waveforms based on this stored data. The configuration of such a signal waveform display device is shown in FIG. In FIG. 4, an input signal is input to an AD converter 1, converted into a digital signal in synchronization with the output of a free-run pulse generator 8, and stored in a memory 2. The input signal is also input to the trigger circuit 4. The trigger circuit 4 generates a trigger signal when the input signal reaches a preset trigger level. This trigger signal is input to the sawtooth wave generator 5 for the time axis. The time axis sawtooth wave generator 5 generates a time axis sawtooth wave in synchronization with this trigger signal. This sawtooth wave is synchronized with the output of the free run pulse generator 8.
It is converted into a digital signal by the AD converter 6 and stored in the memory 7. The data stored in the memories 2 and 7 are input to the Y-axis and X-axis of the display 3, and the waveform of the input signal is displayed. Note that the unblanking circuit 9 is for masking unnecessary display.

In such a signal waveform display device, since the input signal and the output of the free run pulse generator 8 are generally asynchronous, several cycles of the input signal are held in the memory 2 and displayed in a superimposed manner. However, when they are displayed in an overlapping manner, jitter occurs in which the starting point of the display portion is shifted by a width of less than half the period of the output of the free-run pulse generator 8, and the waveform becomes double, making it difficult to see. Therefore, the time difference between the trigger point and the sampling point of the AD converter 1 is measured, and the display is corrected based on this measurement result.

Such a time difference measuring circuit is shown in FIG. In this figure, the free run pulse output from the free run pulse generator 8 is input to the clock terminal of the flip-flop 10, and its output Q is input to the clock terminal of the flip-flop 10.
input to the enable terminal EN. Further, the data terminal D is set to a low level. A clock for timekeeping is input to the clock terminal of the counter 11. A trigger signal is input to the set terminal SET of the flip-flop 10 and the clear terminal CLR of the counter 11. The operation of this time difference measuring circuit will be explained based on the time chart of FIG. When the trigger signal (A) goes low at time, the flip-flop 10 is set, its output goes high as shown in (C), and the counter 11 is cleared. The counter 11 has its enable input set to high level by the output of the flip-flop 11, and (E)
The timer clock starts counting as follows.
When the free run pulse rises at the time, the output of the flip-flop 10 goes low and the counter 11 stops counting. Therefore, the count value of the counter 11 is equal to the time difference between the rising edge of the trigger signal and the free run pulse by the resolution of the period of the timekeeping clock, and this time difference can be measured.

<Problems to be Solved by the Invention> However, in such a signal waveform display device, the resolution of the time difference signal for correcting jitter is defined by the cycle of the time clock. Waveform display devices such as digital oscilloscopes typically magnify the time axis several hundred times for observation, but in order to prevent jitter from occurring even with such high magnification, timekeeping is required. The period of the operating clock must be sufficiently short. For example, if the free run pulse period is 1 MHz and the input signal is sampled at this period, the clock for clocking must be several hundred MHz, which has the disadvantage of requiring expensive high-speed components. .

<Purpose of the invention> The purpose of the invention is to provide a signal waveform display device that can correct jitter without using any high-speed components.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a signal waveform display device that converts an input signal into a digital signal and displays the waveform of the input signal based on the digital signal. , a trigger signal is generated by the trigger signal generation section when the input signal reaches a predetermined trigger level, and the digital signals before and after the generation of the trigger signal are input to the arithmetic unit, and these input data and Calculate the time difference between the trigger signal and the sampling point from the trigger level,
The display is corrected based on this time difference.

<Embodiment> FIG. 1 shows an embodiment of a signal waveform display device according to the present invention. Note that the same elements as in FIG. 4 are given the same reference numerals, and their explanations will be omitted. In Figure 1, 2
0 and 21 are registers, into which the output of the AD converter 1 is input. The outputs of the registers 20 and 21 are controlled by a control signal S. 22 is a flip-flop, and a trigger circuit 4 is connected to its data terminal D.
The output of is input. 23 is a flip-flop, and the flip-flop 22 is connected to its data terminal D.
The output Q of is input. 24 and 25 are AND gates whose inverting inputs receive the outputs Q of flip-flops 22 and 23, respectively. The clock terminals of flip-flops 22, 23 and
The output of the free run pulse generator 8 is input to the non-inverting inputs of the AND gates 24 and 25. Also
The outputs of the AND gates 24 and 25 are the register 20,
It is input to the clock terminal of 21. 26 is an arithmetic unit to which the outputs of registers 20 and 21 are input. 27 is a corrector to which the outputs of the memory 2 and the arithmetic unit 26 are input. The output of the corrector 27 is input to the Y axis of the display 3.

Next, the operation of this embodiment will be explained based on the time chart of FIG. In FIG. 2, A is the trigger signal that is the output of the trigger circuit 4, B is the free run pulse that is the output of the free run pulse generator 8, C and D are the outputs of the flip-flops 22 and 23, and E is the AD converter 1. The outputs of F and G are the outputs of registers 20 and 21. The AD converter 1 converts the input signal into a digital signal and outputs it in synchronization with the rising edge of the free run pulse. E's Dn _-1 ~
Dn ₊₂ represents the converted data. When the trigger signal becomes high level at a certain time, the output of flip-flop 22 becomes high level at a time a little delayed from the rise of the next free-run pulse, and the output of flip-flop 23 becomes high level at a time a little delayed from the rise of the next free-run pulse. output becomes high level. Before the time when the output of flip-flop 22 becomes high level, AND gate 24
The output changes in the same way as the free run pulse. Therefore, the same data as the output of the AD converter 1 is stored in the register 20. When the output of the flip-flop 22 becomes high level at the time, the output of the AND gate 24 is fixed at low level, so the register 20 holds the output Dn of the AD converter 1 immediately before the time when the trigger signal becomes high level. be done.
Similarly, the output of the flip-flop 23 becomes high level at the time, so the register 21 stores the output of the AD converter 1 immediately after the time when the trigger signal becomes high level.
The output of Dn ₊₁ is retained. The data held in the registers 20 and 21 is input to the arithmetic unit 26 by the control signal S.

The operation of the arithmetic unit 26 will be explained based on FIG. As shown in FIG. 3, the rising times of the free-run pulse immediately before and after the trigger signal rise are T ₁ and T ₃ , and the magnitude of the input signal at these times, that is, the data stored in registers 20 and 21, is Dn, Dn ₊₁ , the time of rise of the trigger signal is _T2 , the magnitude of the input signal at that time, that is, the trigger level, is _S1 , and the period of the free run pulse is T, then the time difference Δt between time _T3 and _T2 can be calculated as Δt=T×|Dn ₊₁ −S ₁ |/|Dn ₊₁ − Dn|. However, it is assumed that the input signal changes linearly. The trigger level S ₁ is known, and the arithmetic unit 26 executes the above calculation. This calculation result is input to the corrector 27. The corrector 27 delays the data read from the memory 2 by this Δt and outputs it to the display 3. By doing this, even if the input signal is displayed multiple times, the trigger point will always be at the same point on the display section, so no jitter will occur.

In this embodiment, the arithmetic unit 26 is configured separately, but it may be executed by a processor that controls the entire device.

<Effects of the invention> As explained in detail based on the embodiments above, this invention calculates the time difference between the trigger point and the sampling point from the magnitude of the input signal before and after the trigger point and the trigger level, and calculates the time difference between the trigger point and the sampling point. The display is now corrected based on the results. Therefore, since a high-speed clock is not required for time difference measurement, jitter reduction can be achieved with a simple and inexpensive configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the signal waveform display device according to the present invention, Fig. 2 is a time chart showing the operation, Fig. 3 is a diagram for explaining the calculation method, and Fig. 4 is a conventional one. FIG. 5 is a block diagram showing the configuration of a conventional signal waveform display device, FIG. 5 is a configuration diagram of a conventional circuit for measuring time differences, and FIG. 6 is a time chart showing its operation. 20,21...Register, 22,23...Flip-flop, 24,25...AND gate, 2
6...Arithmetic unit, 27...Corrector.

Claims (1)

[Claims for Utility Model Registration] A signal waveform display device that samples an input signal at a predetermined period, converts it into a digital signal, and displays the waveform of the input signal based on the digital signal, a trigger signal generator that generates a trigger signal when the input signal reaches a level; a free run pulse generator that outputs a free run pulse that is a fixed period rectangular wave while the input signal is being measured; an analog/digital converter that converts an input signal for each period of the free run pulse outputted from the run pulse generator into digital data; a first register that updates and holds data at the rising edge of the free run pulse immediately after the trigger signal is generated; and updates the data output from the analog/digital converter every cycle of the free run pulse; a second register that holds data at the rising edge of the second free run pulse after the trigger signal is generated; and digital data held in the first register and digital data held in the second register. an arithmetic unit that calculates the time interval between the trigger signal and the sampling point from the difference between each data using these data and the digital data of the predetermined trigger level. , a signal waveform display device characterized in that the display of the input signal is corrected based on the output of the arithmetic unit.