JP2971307B2 - Waveform recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform recording device such as a digital oscilloscope, and more particularly, to a device for recording waveforms having different time points as reference points on the same screen.

[0002]

2. Description of the Related Art Digital oscilloscopes perform A / D conversion of an input signal, temporarily record the waveform data in a waveform memory, then D / A convert the data, and display the waveform on a display device such as a cathode ray tube. I do.

When the configuration of an electronic device to be measured is complicated, it is not enough to examine only one signal waveform of the electronic device, and it is necessary to simultaneously observe the operations of a plurality of interconnected circuit portions. Conventional digital oscilloscopes have a plurality of channels for taking in signals from each circuit section in order to respond to such a point. A / D conversion of signals input from each channel is performed in parallel and provided for each channel. After being temporarily recorded in the stored waveform memory, D / A conversion is performed, and signal waveforms of a plurality of channels are displayed on one screen of the display device using the same time axis.

The waveform memory sequentially stores the A / D-converted waveform data. When the number of input waveform data exceeds the memory length, the waveform memory continuously stores new input data while sequentially deleting old data. The updating of the storage of the waveform memory is stopped based on a trigger pulse generated when the input signal crosses a certain level, and the waveform memory holds the waveform data representing the waveform of the input signal.

[0005] Many conventional digital oscilloscopes are equipped with a post counter. This post counter counts the number of A / D-converted waveform data input to the waveform memory based on a trigger pulse generated from an input signal, and when the number reaches a preset value, the waveform data is stored in the waveform memory. Stop the record update operation.

Therefore, assuming that the memory length of the waveform memory is M bytes and the numerical value preset in the post counter is N, the waveform data before the trigger pulse base point is M-N bytes and the subsequent data is Are recorded in N bytes, and the waveform in the time zone before and after the generation of the trigger pulse can be reproduced and displayed on a display device such as a cathode ray tube.

Further, a delay timer is started by a trigger pulse, and a post counter is started after a delay time set in advance by the delay timer, and the waveform data after the delay time is recorded is also performed. Have been.

Japanese Unexamined Patent Publication No. 61-93963 discloses a digital oscilloscope which does not have a post counter and stops recording / updating of a waveform memory by a trigger pulse. A configuration for providing the same delay time or setting the same delay time for all of a plurality of channels is disclosed.

[0009]

In a conventional digital oscilloscope, when one trigger pulse is generated,
The delay timer or the post counter is started based on the trigger pulse. Therefore, in the waveform memory of each channel, signal waveforms appearing in each circuit portion are recorded based on the signal that generated the trigger pulse, and are displayed on the display screen.

However, in a conventional digital oscilloscope, when a trigger pulse is continuously generated,
Waveforms based on trigger pulses at different points in time cannot be displayed on the same screen or compared and analyzed.

The present invention has been made to solve the above-described conventional problem. When a trigger pulse is repeatedly generated, a signal waveform obtained by using a plurality of waveform memories of a plurality of channels as trigger points of different trigger times. It is an object of the present invention to provide a waveform recording apparatus capable of recording the same, displaying the waveforms on the same screen, and analyzing the relationship between the signal waveforms.

[0012]

Accordingly, the present invention has a plurality of channels, and a signal input to each channel is A / A.
In a waveform recording apparatus including an A / D converter for D-conversion and a waveform memory for recording waveform data of an A / D-converted input signal, a trigger pulse is output based on a level of a signal input to a reference channel. Trigger generation means, delay pulse generation means for generating a delay pulse after a set time has elapsed from a trigger pulse, and address control for controlling recording of waveform data in the waveform memory of each channel based on the trigger pulse or the delay pulse. Means, and each of the address control means is set to perform the control based on a different trigger pulse or a delayed pulse generated based on a different trigger pulse.

Further, the sample rate of the waveform data recorded in the waveform memory can be changed by the address control means.

Further, there is provided arithmetic means for performing an arithmetic operation using the waveform data recorded in each waveform memory.

[0015]

Therefore, when a trigger pulse is repeatedly generated from the trigger generating means, the recording operation of the waveform memory of another channel is controlled for each trigger pulse, and the phenomena captured at different measurement points are recorded in each waveform memory. Is done.

When comparing the waveforms of the signals input to the respective channels, by changing the sample rate of the waveform data recorded in the waveform memory, for example, a compressed signal and an uncompressed signal can be kept in the same state. It becomes possible to compare.

Further, by computing the waveform data recorded in each waveform memory by the computing means, it is possible to observe a difference signal or the like.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A waveform recording apparatus according to an embodiment of the present invention comprises a channel 1 (CH1) and a channel 2 as shown in FIG.
(CH2) and input terminal 91 of channel 3 (CH3),
92, 93 and A for A / D conversion of a signal input from each terminal
A / D converters 2, 14, and 18, preamplifiers 1, 13, and 17 for adjusting the gain of input signals so that the A / D converter does not overflow, and temporarily store waveform data output from A / D converters 2, 14, and 18. Waveform memory to record 3, 1
5, 19, an address control circuit 8, 16, 20 for controlling the recording of waveform data in the waveform memories 3, 15, 19;
D converters 2, 14, 18 and address control circuits 8, 1
A clock oscillator 7 for supplying a clock for designating the operation timing to 6, 20; a trigger circuit 10 for generating a trigger pulse when an input signal crosses a certain level; and a delay pulse after a certain delay time when a trigger pulse is input , A display memory 4 for storing the waveform data held in the waveform memories 3, 15, and 19, and a waveform data bus connected to the display memory 4 via a data transfer bus and stored in the display memory 4. And an arithmetic circuit 21 for performing an arithmetic operation between the display memory 4 and the waveform data stored in the display memory 4.
An X signal generator 5 and a Y signal generator 9 for generating an X signal and a Y signal for performing the A / A conversion and displaying on the CRT 6 are provided.

The address control circuits 8, 16, and 20 include a frequency divider for dividing the frequency of the clock signal generated by the clock oscillator 7, an address counter for counting the clock output from the frequency divider, and a trigger circuit. It includes a post counter that counts clocks up to a set value based on the trigger pulse generated in 10 or the delay pulse output from the delay timer 11.

This waveform recording apparatus has an input terminal 91 of CH1.
Operates as follows when the signal shown in FIG. In FIG. 2, A, B, and C indicate the voltage or current waveform of the input signal, T indicates the timing at which the input signal is recorded, and the horizontal axis indicates the passage of time.

The input signal A is A / D-converted by the preamplifier 1.
The signal is attenuated or amplified to an amplitude corresponding to the dynamic range of the converter 2. The A / D converter 2 A / D converts the signal amplified by the preamplifier 1 in synchronization with the clock signal generated by the clock oscillator 7.

A part of the input signal attenuated or amplified by the preamplifier 1 is input to a trigger circuit 10 and the trigger circuit 10
Generates a trigger pulse when the input signal level crosses a certain level value. In FIG. 2, T ₀ indicates the time when the trigger pulse is generated.

The address control circuit 8 receives the trigger pulse generated by the trigger circuit 10 and the clock signal generated by the clock oscillator 7, and repeats the following operation. For easy understanding, the frequency of the clock signal is 10 Mc / s, and the memory length of the waveform memory 3 is 1 k.
It is assumed that the word is a word and the address number exists from address 1 to address 1024.

In the address control circuit 8, the frequency divider divides the frequency of the clock signal, the address counter counts the output of the frequency divider from 1 to 1024, and then returns to 1 again to 10
The counting up to 24 is performed and this is continuously repeated.

The count value of the address counter of the address control circuit 8 is sent to the address bus of the waveform memory 3 as address information. Accordingly, the waveform data generated by the A / D converter 2 has a frequency division ratio of 1 when the frequency division ratio is 1.
After being recorded in order from address 1 to address 1024 of the waveform memory 3 in accordance with the clock signal from the clock oscillator 7, it is recorded from address 1 again, and this is continuously repeated.

[0026] When the trigger circuit 10 generates a trigger pulse at T ₀ in Figure 2, to start the post counter of the address control circuit 8 by the trigger pulse, starts an operation of counting a clock output of the divider.

Assuming that the set value of the post counter is 700 and the frequency division ratio of the frequency divider of the address control circuit 8 is 1, the sample rate of the clock oscillator 7 is 10 Mc / s (that is, 0. 700 times (1 μs cycle),
That is, the counting operation of the address counter of the address control circuit 8 is stopped after 70 μs.

As a result, the waveform memory 3 switches to an operation for holding the recording of the waveform data. The waveform memory 3
Since the memory length can store 1024 data, the time interval of the waveform data that can be recorded and held is 102.4.
μs. Therefore, the recorded and held data has a waveform of 32.4 μs before the trigger pulse is generated and a waveform of 70 μs thereafter. In FIG. 2A, waveform data between T1 and T2 is recorded and held, and T1 and T2 are the waveform recording period in CH1.

The waveform data recorded and held in the waveform memory 3 is transferred to the data input bus of the display memory 4 via the data output bus and stored in the display memory 4.
The stored data is reproduced and displayed on the screen by an X signal generator 5 including a D / A converter, a Y signal generator 9 and a CRT 6.

FIG. 3 shows the waveform of the CH1 signal reproduced and displayed on the surface of the CRT 6 as a.

The sample rate of the waveform data recorded in the waveform memory 3 can be changed by changing the frequency division ratio of the frequency divider of the address control circuit 8. This is because the sample rate of the A / D converter 2 is determined by the clock rate of the clock oscillator 7, but the address counter of the address control circuit 8 counts according to the output of the frequency divider that divides the clock signal of the oscillator 7. To perform the operation, the waveform data that can be captured by the waveform memory 3 is A / A
This is because, of the data output from the D converter 2, only data whose timing matches the output of the frequency divider is limited.

For example, if the frequency division ratio of the frequency divider is 1/2, the waveform data output from the A / D converter 2 is
Only the data of two times is stored in the waveform memory 3
Will be recorded. Therefore, the sample rate at the time of capturing the waveform is 5 Mc / s. This waveform is displayed on the CRT in a state where the waveform of FIG.

Next, the recording of the waveform of the signal input to CH2 will be described.

A CH2 input terminal corresponding to the input of CH1
It is assumed that the signal shown in FIG. According to this signal input, a preamplifier 13, an A / D converter
14, the waveform memory 15 and the address control circuit 16
The same operation as the preamplifier 1, A / D converter 2, waveform memory 3, and address control circuit 8 at the input is repeated.

However, the time at which the post counter is activated in the address control circuit 16 differs from the time at which the post counter is activated in the address control circuit 8, depending on how the address control circuit 16 or the trigger circuit 10 is set.

Now, the trigger circuit 10 outputs a trigger pulse to the delay timer 11 at the same time as the address control circuit 8, and the post counter of the address control circuit 16 ignores the trigger pulse directly input from the trigger circuit 10, It is assumed that it is set to be activated only by the delay pulse input from the delay timer 11.

The delay timer 11 is activated by a trigger pulse input from the trigger circuit 10, and generates a delay pulse after a set time has elapsed. The post counter of the address control circuit 16 is activated by this delay pulse. That is, this delay pulse functions as a trigger pulse for the address control circuit 8 of CH1.

Here, assuming that the numerical value set in the post counter of the address control circuit 16 is 1024 and the frequency division ratio of the frequency divider of the address control circuit 16 is 1, the post counter operates after the delay pulse is input. , Clock oscillator 7
The counting operation of the address counter of the address control circuit 16 is stopped after 1024 times the sample rate of 10 Mc / s (that is, 0.1 μs cycle), that is, 102.4 μs. As a result, the waveform memory 15 switches to an operation for holding the recording of the waveform data.

Since the waveform memory 15 has a memory length capable of storing 1024 data, the time interval of the waveform data that can be recorded and held is 102.4 μs. Therefore, the waveform data input from the A / D converter 14 is recorded and held within a period of 102.4 μs after the generation of the delay pulse. The period (T ₃ through T ₄ in FIG. 2) becomes the waveform recording period CH2. The delay time set in the delay timer 11 corresponds to T ₀ through T ₃ in FIG. 2.

The waveform data recorded and held in the waveform memory 15 is transferred to the data input bus of the display memory 4 via the data output bus and stored in the display memory 4. A part of the waveform data of A in FIG. 2 is already recorded in the display memory 4. Therefore, the data stored in the display memory 4 at this point is converted into an analog signal by the X signal generator 5 and the Y signal generator 9, and then is converted to an analog signal on the CRT.
Display symptoms. FIG. 3 shows waveforms reproduced and displayed on the CRT based on these data as a and b.

When the trigger circuit 10 repeatedly generates a trigger pulse, it is possible to capture waveform data of an input signal in CH1 and CH2 based on different trigger pulses.

In this case, the trigger circuit 10 is set so that the first trigger pulse is output to the address control circuit 8 and the next trigger pulse is output to the delay timer 11. The address control circuit so that the post counter of the address control circuit 16 is not sensitive to the trigger pulse directly input from the trigger circuit 10 and is activated only by the delay pulse input from the delay timer 11.
Set 16

Therefore, the first trigger pulse generated by the trigger circuit 10 is input to the address control circuit 8, and the waveform memory 3 holds the waveform of the input signal of CH1 in the procedure described above. Subsequent trigger pulses generated by the trigger circuit 10 are input to the delay timer 11, and the delay timer 11
Restarts each time and generates a delay pulse after a certain delay time has elapsed.

The post counter of the address control circuit 16 is activated by the delay pulse of the delay timer 11,
After counting a certain number of clocks, the recording and updating of the waveform memory 15 is stopped, and the waveform memory 15 switches its operation to hold the waveform data.

Thus, the waveform memory 15 can capture the waveform of the signal input to CH2 based on the second trigger pulse.

In this case, the trigger circuit 10 does not switch the output destination of the trigger pulse, and the address control circuit 16 does not activate the post-counter with the first input delay pulse, and the second delay pulse The same result can be achieved by setting the post counter to start only when

Now, for the signal input to the input terminal 93 of CH3, the preamplifier 17, A / D converter 18, waveform memory 19 and address control circuit 20 perform preamplifier 1, A / D converter 2, The same operation as that of memory 3 and address control circuit 8 is performed.

However, the address control circuit 20 is a trigger circuit
When 10 is set to switch the output destination of the trigger pulse, the post-counter is started based on the delay pulse output second from the delay timer 11, and the trigger circuit 10 outputs the trigger pulse. When the output destination is not set to be switched, the post counter is set to be activated based on the third output delay pulse.

As a result, when the trigger circuit 10 generates a trigger pulse after the waveform data has been fetched into the waveform memories 3 and 15 of CH1 and CH2, the delay timer 11 is restarted, and the delay time elapses after the delay time has elapsed. Generate a pulse,
The post counter of the address control circuit 20 is activated by the delay pulse.

When the value set in the post counter of the address control circuit 20 is 1024, similarly to the post counter of the address control circuit 16, and when the division ratio of the frequency divider is 1, the waveform memory 19 is waveform memory 15
Similarly, the waveform for 102.4 μs after the input of the delay pulse is held. In FIG. 2, the waveform input to CH3 is C
In also represents a waveform recording period CH3 at T ₅ through T _6.

The waveform data recorded and held in the waveform memory 19 is transferred to the display memory 4 and stored. A part of the waveform data of A and B in FIG. 2 is already recorded in the display memory 4. Therefore, when the data stored in the display memory 4 is converted into an analog signal by the X signal generator 5 and the Y signal generator 9 and then displayed on the cathode ray tube 6, as shown in FIGS. Three phenomena are displayed.

In this waveform recording apparatus, a trigger circuit
When 10 successively output trigger pulses, the post-counters of the address control circuits 16 and 20 in CH2 and CH3 are sequentially activated by these trigger pulses.
A so-called "re-trigger mode" can also be set.

In the retrigger mode, the post counter of the address control circuit 16 prepares for counting with the first delay pulse from the delay timer 11, and starts counting with the trigger pulse input thereafter. The address control circuit 16 is set, and the address counter is controlled so that the post counter of the address control circuit 20 prepares for counting with the next delay pulse from the delay timer 11 and starts counting operation with the trigger pulse input thereafter. Set the circuit 20.

Therefore, the post counters of the address control circuits 16 and 20 are activated by the designated delay pulse of the delay timer 11, but the start of counting is delayed until the trigger pulse is received after the occurrence of the delay pulse. When the trigger pulse is input, the post counter stops counting operation of the address counter after counting the set number.

As a result, the input signal waveform of CH1 is recorded based on the first trigger pulse, the input signal waveform of CH2 is recorded based on the second trigger pulse, and the input signal waveform of CH3 is recorded on the third trigger pulse. Is recorded based on the trigger pulse of. The recorded signal waveforms are displayed on one screen on the CRT 6.

In this case, if a signal output from the same circuit portion of the electronic device is input to each of CH1, CH2, and CH3, a temporal change of a signal passing through the circuit portion can be observed.

The address control circuits 16 and 20 for CH2 and CH3 can be set so as to keep operating alternately in response to the generation of a trigger pulse.

Next, the operation of analyzing the waveform data in the waveform recording apparatus of the embodiment will be described. In this waveform recording apparatus, it is possible to compare and analyze the waveforms of the signals input from the respective channels. Further, in order to perform the comparison and the analysis, the sample rate in the waveform recording of each signal can be adjusted.

The adjustment of the sample rate is performed using the frequency divider of the address control circuits 8, 16, and 20 described above.

For example, when the signal shown in FIG. 4D is input to CH1 and the signal shown in FIG.
The frequency division ratio of the frequency divider in the address control circuit 8 of H1 is 1
/ 2, and the frequency division ratio of the frequency divider in the address control circuit 16 of CH2 is set to 1.

In the CH 1, only the data of one time out of the waveform data output from the A / D converter 2 is recorded in the waveform memory 3 in chronological order. Thus, the sample rate of the time waveform incorporation 5Mc / s, and the waveform recording period will 204.8μs (T ₇ ~T ₉ in FIG. 4). The waveform data obtained at this time is displayed on the screen of the CRT 6 as shown in FIG.
Is displayed as d in FIG.

On the other hand, in CH2, since the frequency division ratio of the frequency divider of the address control circuit 16 is 1, the waveform data output from the A / D converter 14 is recorded in the waveform memory 15 as it is. Accordingly, the sample rate becomes 10 Mc / s, and the waveform recording period is 102.4 μm after the generation of the delay pulse.
It becomes s (T ₈ ~T ₁₀ in FIG. 4). This waveform data is displayed on the screen of the cathode ray tube 6 as shown in FIG.

As described above, in the waveform recording apparatus of the embodiment,
By changing the frequency division ratio of the frequency divider included in the address control circuits 8, 16, and 20, the sample rates of the waveform data recorded in the waveform memories 3, 15, and 19 of the respective channels are changed. The recording time can be set for each channel.

The arithmetic circuit 21 inputs waveform data of a desired channel among a plurality of waveform data stored in the display memory 4 via a data transfer bus, and executes arithmetic operations such as four arithmetic operations. The calculation result is transferred again to the display memory 4 via the data transfer bus. As a result, the calculated waveform data is displayed on the screen of the CRT 6. FIG. 5E shows the result of subtracting the waveform d from the waveform e as an example of the calculation.

In this waveform recording apparatus, the data recorded in each of the waveform memories 3, 15, and 19 is not only displayed on the CRT 6 but also transmitted from the memory corresponding to the display memory 4 to other devices. Alternatively, a configuration in which data is directly transferred from a waveform memory to an external device may be employed. In the latter case, the waveform analysis work can be assigned to an external device.

Further, it is also possible to convert the data of a plurality of waveforms stored in the display memory into another display method, for example, data such as a video signal and display the waveform.

In the embodiment, the case where the number of channels is 3 has been described. However, it is clear from the description of the operation of the embodiment that the number of channels does not matter. When the number of channels is set to n, the waveform input operation is stopped when the waveform data of the n-channel input signal is obtained, so that the delayed waveforms for n channels can be displayed on the screen of the same CRT 6. it can.

[0068]

As is clear from the above description of the embodiment, the waveform recording apparatus of the present invention has the following effects. 1. Waveform observation can be performed on signals under measurement applied to a plurality of channels with reference to different time points. 2. By calculating waveform data at different points in time, waveform analysis can be performed beyond the concept of time. In particular, it is possible to provide an analysis means suitable for correcting a time delay, for example, analyzing a signal to be measured in a transmission system having a time delay, executing an operation represented by a difference signal, and analyzing the signal. 3. The sample rate of the waveform data to be recorded can be set for each channel, and the waveforms can be displayed on the same time axis in a form that allows easy comparison. Therefore, it is possible to provide waveform observation means suitable for a technical experiment such as time compression.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a waveform recording apparatus according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a signal input to each channel of the waveform recording apparatus.

FIG. 3 is a waveform diagram displayed on a screen of the waveform recording device;

FIG. 4 is another waveform diagram showing a signal input to the waveform recording device;

FIG. 5 is a waveform diagram displayed on a screen after being processed by the waveform recording device.

[Explanation of symbols]

 1, 13, 17 Preamplifier 2, 14, 18 A / D converter 3, 15, 19 Waveform memory 4 Display memory 5 X signal generator 6 CRT 7 Clock oscillator 8, 16, 20 Address control circuit 9 Y signal generator 10 Trigger Circuit 11 Delay timer 21 Arithmetic circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-364471 (JP, A) JP-A-4-143666 (JP, A) JP-A-61-93963 (JP, A) JP-A-2- 9950 (JP, A) JP-A-55-147743 (JP, A) JP-A-56-74658 (JP, A) Actual development Sho-56-170599 (JP, U) "Introduction to Digital Oscilloscopes" by Yoshinori Furuichi, Ohmsha Published, pp. 72-74 (58) Fields investigated (Int. Cl. ⁶ , DB name) G01R 13/00-13/42

Claims (3)

(57) [Claims] An A / D converter having a plurality of channels and A / D converting a signal input to each channel,
A waveform recording device for recording waveform data of a D-converted input signal, wherein a trigger generating means for outputting a trigger pulse based on a level of the signal input to a reference channel; and A delay pulse generating means for generating a delay pulse after a lapse of a set time from a base point, and an address control means for controlling recording of waveform data in the waveform memory of each channel based on the trigger pulse or the delay pulse; A waveform recording apparatus, wherein each of the control means is set so as to perform the control based on a different trigger pulse or a delayed pulse generated based on a different trigger pulse. 2. The waveform recording apparatus according to claim 1, wherein the sample rate of the waveform data recorded in the waveform memory can be changed by the address control means. 3. The waveform recording apparatus according to claim 1, further comprising an arithmetic unit that performs an arithmetic operation using the waveform data recorded in each of the waveform memories.