JP2573226B2 - Signal time measurement device - Google Patents

Description

The present invention relates to a signal time measuring device used for a device for automatically measuring a time difference between output signal waveforms of a semiconductor device, for example.

(Prior Art) This kind of conventional signal time measuring device for, for example, two channels is configured as shown in FIG. That is, 6
0 and 70 are coaxial cables for input signals, 61 and 71 are signal input terminals, 62 and 72 are input impedance matching resistors, 63 and 73 are input buffer amplifiers, 64 is a level comparator for start, and 65 is a start trigger level setting. Circuit, 74 is a stop level comparator, 75 is a stop trigger level setting circuit, 66 and 76 are slope selection circuits, 67 is a gate pulse generation circuit, 68 is a gate circuit, 69 is a master clock generation circuit, and 77 is a clock pulse counter. It is.

In the above apparatus, an input terminal of a first channel system
The operation will be described for the case where the input signal S1 of 61 and the input signal S2 of the input terminal 71 of the second channel are synchronized as shown in FIG. 7 and the case where they are asynchronous as shown in FIG. . Input signal S1 is a start trigger level setting circuit
When the positive slope (the rising slope of the waveform) selected by the slope selection circuit 66 crosses the start trigger level set by 65, it is converted to a trigger signal. Also,
The input signal S2 sets the stop trigger level set by the stop trigger level setting circuit 75 to the slope selection circuit 76.
Is set to a trigger signal when the negative slope (falling slope of the waveform) selected by (1) crosses. Then, a time difference T1, T2, between the two waveforms according to the timing difference between the two binarizations.
The gate pulse having T3,.
In occurs, the pulse width of the gate pulse is counted by the clock pulse counter 77 by the master clock period t _0, the count output N (N1, N2, N3, ...) and t ₀ the time difference by multiplying the T1, T2, T3 ... are required. In this case, if the input signals S1 and S2 are synchronized, accurate measurement is possible because T1 = T2 = T3 =...
T3 ... varies (in this example, T1TT2, T3 ≠ T4, T1 = T3, T2
= T4), there is a problem that the measured values vary, and if the signal waveform is further complicated, the above-described measurement becomes impossible.

(Problems to be Solved by the Invention) As described above, the present invention solves the problem that the time difference between waveforms cannot be accurately measured for an asynchronous input signal, and measurement cannot be performed for a complex waveform. It is an object of the present invention to provide a signal time measuring device capable of accurately measuring a time difference between waveforms of an asynchronous input signal and measuring a complicated waveform.

[Structure of the Invention] (Means for Solving the Problems) The signal time measuring device of the present invention is determined by a predetermined trigger level by either a rising slope or a falling slope of the waveform of an input signal in each of a plurality of channels. Output of a clock pulse counter provided in common to each channel to a clock data memory in which a trigger signal is generated at a timing and an address is specified according to the cumulative number of trigger signals generated each time the trigger signal is generated. And the clock pulse counter is supplied with a number of master clocks corresponding to the elapsed time from the generation of a specific trigger signal in one reference channel as a count input. I do.

(Operation) The time data relating to the trigger signal generation timing for the input signal of each channel is fetched into the memory in real time, and this data is used to calculate the time such as the cycle of the input signal waveform or the phase difference between the two waveforms. A wide variety of parameters can be easily obtained by calculation. Therefore, not only two synchronized input signals,
It is possible to obtain a phase difference between waveforms of two asynchronous input signals and time data of a complicated input signal waveform.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a signal time measuring device for n-channel, 1 ₁ to 1 _n is the input signal S ₁ to S _n of the first to n-channel
Is a coaxial cable that leads In the signal time measuring device, the two _first input terminal for the first channel, 3 ₁ connected impedance matching resistor between the input terminal 2 ₁ and a ground terminal, 4 ₁ of the input terminal 2 ₁ input buffer amplifier for amplifying an input signal, 5 ₁ the amplifier 4 ₁ of the output signal is compared type comprising level comparator, ₆₁ is set trigger level for generating a trigger level as the reference input of the level comparator 5 ₁ circuit,
7 ₁ slope selection circuit for selecting in response the positive slope of the level comparator 5 ₁ of the output signal waveform (rising slope) or negative slope (the falling slope) in the slope selection control signal input, 8 ₁ the slope trigger signal generating circuit for converting an output signal of the selection circuit ₇₁ to the trigger signal, 9 ₁ address for generating address data for clock data memory 11 ₁ which will be described later by counting the trigger output of the trigger signal generating circuit 8 ₁ the counter circuit 10 ₁ is a clock data load signal generating circuit for generating a clock data load signal of the clock data memory 11 for ₁ based on the trigger output of the trigger signal generating circuit 8 _1. Clock data memory 11 ₁
The content of the clock pulse counter 12 described later is written to the address specified by the address data by the load signal.

Similar to the first channel of the system, also in the system of the second channel to the n-channel, the input terminal 2 ₂ to 2 _n,
Impedance matching resistor 3 ₂ to 3 _n, the input buffer amplifier 4 ₂ -
4 _n, level comparator 5 ₂ to 5 _n, sets the trigger level circuit 6 ₂ -
6 _n, the slope selection circuit 7 ₂ to _7-n, the trigger signal generating circuit 8 ₂ -
8 _n, the address counter circuit 9 ₂ to 9 _n, the clock data load signal generating circuit 10 ₂ to 10 _n, the clock data memory 11 _2-1
1 _n are provided. Furthermore, in common to each channel system, start trigger selection for selecting a trigger signal of a single channel to be a reference in accordance with the trigger signal TRG ₁ ~TRG _n is input to the start trigger select control signal input of each channel systems A circuit 13, a master clock generation circuit 14 for generating a master clock (period t ₀ ), a clock pulse gate circuit 15 for opening a gate in synchronization with the output of the start trigger selection circuit 13 and passing the master clock,
The said clock pulse counter 12 the output pulse train is counted up by the generating a clock data to be written to one of the clock data memory 11 ₁ to 11 _n of the clock pulse gate circuit 15 is provided.

Next, the operation of the signal time measuring device will be described with reference to FIG. Input buffer amplifier in each channel system
4 ₁ to 4 _n set trigger level as shown in FIG. 2 for each output signal and of the slope selection is made, and, for example, if the trigger signal TRG ₁ of the first channel is selected as a reference, ready to clock pulse gate circuit 15 is opened in the first shot first trigger signal TRG ₁ of the first channel, the passage of the master clock starts. Accordingly, the count value N of the clock pulse counter 12 at the time the trigger signal TRG ₁ ~TRG _n generated in the respective channels
Corresponds to the time (= count value × t ₀ ) from the first generation timing of the trigger signal TRG ₁ of the first channel selected as the reference, and the count value N is set for each channel. Clock data memory 11 ₁ to ₁ controlled to be written by a load signal generated based on a trigger signal
_Written to one of 1 _n . In this example, the count value N when the trigger signal TRG ₁ of the first channel is generated
5, N7, N10 ... respectively written in the clock data memory 11 ₁ which is addressed by the address counter circuit 9 _first output at each time point, similarly, the count value to the clock data memory 11 of the _second channel N3 , N8, N12... Are respectively written, and the clock data memory of the n-th channel is written.
11 counts the _n values N1, N2, N4, N6, N9, N11 ... are written, respectively.

As described above, the time data of the input signal S ₁ to S _n of each channel available in real time, it is possible to calculate a variety of waveform parameters by the calculation circuit which is not shown based on this data.

For example, the average value T ₀ of the waveform period of the input signals S ₁ of the first channel, if the data acquisition count of the clock data memory 11 ₁ and n And the frequency f ₀ of the input signal S ₁ is 1 / T ₀ . Also, the balance η of the adjacent periods in the input signal S ₁
Is Becomes The time difference between the waveforms of each channel is
N3 × t ₀ between the first and second channels, N1 × t ₀ between the first and n-th channels,
(N3−N1) × t ₀ between the channel and the n-th channel
It can be obtained by a simple calculation such as

In a signal time measuring device for two channels,
As shown in FIG. 3, the input signals S ₁ and S ₂ are completely synchronized, and a positive slope is selected in the first channel, a negative slope is selected in the second channel, and the first channel is used as a reference. When the count values N ₁ ... Are obtained as shown, various parameters such as the phase (time interval) of the input signal can be obtained as shown below. For example, the falling edge of the input signal S ₂ from the rising edge of the input signals S _1, the Gives the time interval for each cycle, and the average value T _{0 for} n cycles is Becomes Similarly, the rising edge of the input signals S ₁ from the falling of the input signal S ₂ is Gives the time interval for each cycle, and the average value T _{0 for} n cycles is Becomes

In a signal time measuring device for two channels,
As shown in FIG. 4, the input signals S ₁ and S ₂ are not synchronized,
When a positive slope is selected in the first channel, a negative slope is selected in the second channel, and a count value N1 is obtained with reference to the first channel as shown in FIG.
As shown below, various parameters such as the phase (time interval) of the input signals S ₁ and S ₂ can be obtained.

For example, the time from the rising of the input signals S ₁ to the fall of the input signal S _2, for each cycle The average values T ₀ (1) and T ₀ (2) for n odd-numbered cycles and even-numbered cycles are respectively Becomes Similarly, the time from the falling of the input signal S ₂ to the rising of the input signals S _1, for each cycle The average values T ₀ (1) and T ₀ (2) for n odd-numbered cycles and even-numbered cycles are respectively Becomes

In a signal time measuring device for two channels,
Input signals S ₁ and S ₂ having a complex waveform (for example, a damped oscillation waveform as shown in FIG. 5) are input in synchronization with each channel.
When the trigger level of each channel is set to the same value, the positive slope is selected for the first channel, the negative slope is selected for the second channel, and the count value is obtained based on the first channel as shown in the figure. Also, various parameters can be obtained by calculation in the same manner as described above.

In the above embodiment, the master clock determines the time resolution that can be measured. If a time resolution of 10 ns is required, a master clock of t ₀ = 10 ns (100M
Hz) is required. In correspondence to this, the clock data memory 11 ₁ to 11 _n are, for example, may be used which has a capacity capable of storing about 10 to 20 bits of the clock data 16K words.

[Effects of the Invention] As described above, according to the signal time measuring device of the present invention,
Since the time data of the input signal of each channel can be fetched into the memory in real time, various parameters relating to the time of the input signal waveform can be easily calculated by using the data of the memory. In this case, since the time difference between the waveforms of the asynchronous two-input signals and the time data of the complex input signal waveforms as well as the synchronized two-input signals can be obtained, the apparatus of the present invention is used in many signal time measurement fields. It becomes possible to do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the signal time measuring device of the present invention, FIG. 2 is a diagram showing signal waveforms and timings for explaining an operation example in the device of FIG. 1, and FIGS. FIG. 5 is a diagram showing different operation examples in the signal time measuring device for two channels, FIG. 6 is a block diagram showing a conventional signal time measuring device, and FIGS. FIG. 7 is a diagram shown for explaining different operation examples in the apparatus of FIG. 6; 5 _{1 to} 5 _n ... Level comparator, 6 _{1 to} 6 _n ... Trigger level setting circuit, 7 _{1 to} 7 _n ... Slope selection circuit, 8 ₁ to 8 _n ... Trigger signal generation circuit, 9 _{1 to} 9 _n: Address counter circuit, 10 ₁
1010 _n …… Clock data load signal generation circuit, 11 ₁ 1111
_n: Clock data memory, 12: Clock pulse counter, 13: Start trigger selection circuit, 14: Master clock generation circuit, 15: Clock pulse gate circuit.

Claims (2)

(57) [Claims] 1. A trigger signal is generated in each of a plurality of channels at a timing determined by a predetermined trigger level according to either a rising slope or a falling slope of a waveform of an input signal, and a trigger signal is generated every time the trigger signal is generated. The output of a clock pulse counter provided in common for each channel is written to a clock data memory whose address is specified according to the cumulative number of occurrences of the clock pulse counter. A signal time measuring device characterized in that a number of master clocks corresponding to an elapsed time from the generation of a specific trigger signal in one channel are provided as count inputs. 2. A circuit according to claim 1, further comprising a circuit for calculating a predetermined parameter based on a plurality of time data respectively written in the clock data memory of each channel. The signal time measuring device according to the above.