JP2674016B2 - Frequency measuring device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency measuring device that measures the period of a signal under measurement by counting a reference clock and obtains the frequency of the signal under measurement from this period. SUMMARY OF THE INVENTION The present invention provides a frequency measuring apparatus that measures a period of a signal under measurement by counting a reference clock and obtains a frequency of the signal under measurement from this period, based on a target frequency and a permissible error. By appropriately setting the division ratio of the measurement signal, the measurement time is shortened. [Prior Art] A frequency measuring device for inspecting whether an output signal of a desired oscillation frequency from the circuit is obtained or a signal of a desired frequency is input when adjusting an electronic device. Is used. As such a frequency measurement device, the signal under measurement is waveform-shaped, the number of repetitions of the pulse signal per constant time is counted to obtain the frequency, or the frequency of the signal under measurement is obtained by counting the reference clock, A method of obtaining a frequency from this cycle is often used. That is, as shown in FIG. 3, a predetermined time T ₁₀ for example,
A gate pulse GP ₁₀ having a length of 1 second is formed as shown in FIG. 3A, the gate pulse GP _{10 is used} to open the gate, and the measured signal S ₁₀ having a waveform shaped through the gate.
(Fig. 3 B) was fed to a counter, for counting the number of pulses of the measured signal S ₁₀ which is the waveform shaping per predetermined time T _10. When this count value and K _10, the frequency f ₁₀ of the signal S ₁₀ to be measured, As required. Further, as shown in FIG. 4, to open the gate between the rising point t ₁₁ of the measurement signal S ₁₁ which is waveform-shaped (Fig. 4 A) until the next rising time t _12, the time t ₁₁ ~t ₁₂ Until then, the reference clock RCK ₁₁ (FIG. 4B) is supplied to the counter through the gate, and the reference clock RCK ₁₁ during the time points t _{11 to} t ₁₂ is counted. From this count value, the period of the signal under measurement S ₁₁ can be known, and thus the frequency of the signal under measurement S ₁₁ can be known. That is, the frequency of the reference clock RCK ₁₁ is fck.
₁₁ and the number of counts is K ₁₁ , the frequency of the signal under test S ₁₁
f ₁₁ is Is required. [Problems to be Solved by the Invention] By the way, as shown in FIG. 4, when the gate is opened between time points t ₁₁ and t ₁₂ and the reference clock is counted during this period to obtain the frequency, Assuming that the frequency of the reference clock is constant, as the frequency of the signal under measurement becomes higher, its cycle becomes shorter, resulting in a larger measurement error. Therefore, in the conventional frequency measuring device, the signal under measurement can be divided and the gate can be opened by the divided signal. That is, if the frequency of the signal under measurement is divided by N, the cycle is N times, and the measurement accuracy is improved accordingly. However, if the frequency of the signal under measurement is divided by N in this way, a long measurement time is required accordingly. A target frequency and a permissible error are determined when the electronic device is adjusted. For example, in the case of adjusting the circuit that outputs the signal of NTSC color subcarrier frequency, if the target frequency is 3.579545MHz and the allowable error is ± 10Hz, the output signal of that circuit is 3.5795.
Adjust between 5MHz and 3.579535MHz. Therefore, it is sufficient for the frequency measuring device to be displayed with an accuracy corresponding to this. However, in the conventional frequency measuring device, the division ratio N is increased by increasing the measurement time to increase the measurement accuracy. Therefore, if the frequency is displayed with an accuracy within the allowable error, an extra digit is displayed. There is a problem that the frequency is displayed up to the number, and the measurement time is wasted. When adjusting a large number of electronic devices, the waste of measurement time per unit becomes a serious problem. Therefore, an object of the present invention is to provide a frequency measuring device capable of shortening the measurement time by optimally setting the frequency division ratio N according to the target frequency and the allowable error. [Means for Solving the Problems] The present invention is to open a gate by a frequency divider for dividing a signal under measurement and a signal divided by the frequency divider, and to open a reference clock while the gate is open. A counter that counts, a frequency calculation unit that obtains the frequency of the signal under measurement from the output of the counter, a maximum value of the target frequency, a permissible error, and an optimum division ratio that is determined according to the frequency of the reference clock. Frequency division ratio calculation means, the frequency division ratio calculation means, when the maximum value of the target frequency is f _max , the allowable error is f _unit , and the frequency of the reference clock is f _ck , (f _max / f _min ) This is a frequency measuring device configured to calculate a frequency division ratio N of the frequency divider by calculating ² and converting it into an integer, and dividing this by the reference clock frequency f _ck . [Operation] The maximum value of the target frequency is f _max , and the allowable error is
Let f _{unit be} the reference clock frequency and f _ck be the division ratio N By setting to, measurement can be performed without wasting the measurement time, and the display within the allowable error range can be accurately performed. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 1 designates an input terminal, and the signal under test S ₁ as shown in FIG. 2A is supplied to the input terminal 1. The measured signal S ₁ is shaped by the waveform shaping circuit 2 as shown in FIG. 2B, and the output of the waveform shaping circuit 2 is supplied to the frequency dividing circuit 3. The frequency dividing ratio N is given from the arithmetic circuit 7 to the frequency dividing circuit 3. As will be described later in detail, the frequency division ratio N is the maximum value f _max of the target frequency supplied from the terminal 8 and the allowable error f.
Determined based on _unit . The output of the waveform shaping circuit 2 is divided by 1 / N (1/2 in FIG. 2) as shown in FIG. 2C, the output of the frequency dividing circuit 3 is supplied to the counter 4, and the latch circuit 6 is supplied. And to the arithmetic circuit 7. The reference clock RCK shown in FIG. 2D is supplied to the counter 4 from the reference clock generation circuit 5. Counter 4
Counts this reference clock RCK. The value of the counter 4 at the rising of the output of the frequency dividing circuit 3 shown in FIG. 2B is supplied to the latch circuit 6 and the arithmetic circuit 7.
At the next rise of the output of the frequency dividing circuit 3, the output of the latch circuit 6 is supplied to the arithmetic circuit 7. For example, when the count value at time t ₂ is supplied from the counter 4 to the arithmetic circuit 7, the latch circuit 6 outputs the count value of the counter 4 at time t ₁ . The count value of the counter 4 in the arithmetic circuit 7 at time t ₁ from the count value of the counter 4 at the time t ₂ is subtracted, the count value from the time t ₁ to time t ₂ is determined.
The cycle of the output signal of the frequency dividing circuit 3 is obtained from this count value, and the cycle of the signal under measurement S ₁ is obtained by further dividing the cycle of the frequency dividing circuit 3 by 1 / N. By taking the reciprocal of the period of the measured signals S _1, the frequency f ₁ of the measured signal S ₁ is obtained. Point words, the frequency f ₁ of the measured signals S _1, the frequency division ratio N, the frequency of the reference clock RCK f _ck, from time t ₁
If the count value up to t ₂ is K, Is required. The frequency f ₁ obtained by the arithmetic circuit 7 is taken out from the output terminal 9 and displayed on a display device (not shown). In addition,
In the case where the signal under test S ₁ contains jitter, etc., an average value of the obtained frequencies for each predetermined number of times is obtained, and this average value is displayed on the display device. In order to obtain the frequency f ₁ of the signal under measurement S ₁ with high accuracy, it is advantageous to set the frequency division ratio N to a large value if the frequency of the reference clock RCK is constant. However, if the frequency division ratio N is set to a large value, a long measurement time is required. Therefore, in this embodiment, the optimum frequency division ratio N is calculated from the maximum value f _max of the target frequency and the allowable error f _unit ,
The frequency dividing ratio N is set in the frequency dividing circuit 3. As a result, there is no unnecessary time for measurement, and
It is possible to measure up to a desired tolerance. That is, when the maximum value of the target frequency is f _max , the allowable error is f _unit , and the reference clock frequency is f _ck , the division ratio N
But Is set to As a result, measurement can be performed without wasting the measurement time. When calculating the division ratio based on the above equation, (f _max
/ f _unit ) ² is not always an integer, so (f _max / f
_unit ) ² is calculated, then converted to an integer, and the clock frequency f
Divide by _ck . [Effect of the Invention] According to the present invention, since the frequency division ratio is optimally set based on the target frequency and the allowable error, the frequency measurement can be performed in the shortest time with the measurement accuracy of the allowable error. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a waveform diagram used for explaining one embodiment of the present invention, and FIGS. 3 and 4 are conventional frequency measurement. It is a waveform diagram used for description of an apparatus. Description of main symbols in the drawings 1: Input terminal, 3: Frequency divider circuit, 4: Counter, 7: Arithmetic circuit.

Claims (1)

(57) [Claims] A divider that divides the signal under measurement and a gate that opens with the signal divided by the divider,
A counter that counts the reference clock while the gate is open, a frequency calculation unit that obtains the frequency of the signal under measurement from the output of the counter, the maximum value of the target frequency, the allowable error, and the reference clock Frequency division ratio calculating means for obtaining an optimum frequency division ratio according to the frequency, and the frequency division ratio calculating means determines the maximum value of the target frequency by f
_{If max is} the allowable error, f _{unit is} the reference clock frequency, and f _ck is the reference clock frequency, (f _max / f _unit ) ² is calculated and divided by the reference clock frequency f _ck to divide the frequency by the frequency divider. A frequency measuring device adapted to obtain the ratio N.