JPS63135870A - Frequency measuring apparatus - Google Patents

Abstract

PURPOSE:To achieve a shorter measuring time, by setting a frequency division ratio optimally according to a target frequency and allowable errors. CONSTITUTION:A signal S1 to be measured from an input terminal 1 is supplied to a frequency dividing circuit 3 via a waveform shaping circuit 2. A computing circuit 7 determines a frequency division ratio N based on the max. of a target frequency inputted at a terminal 8 and an allowable error to be supplied to the circuit 3. To determine the frequency of the signal S1 with a high accuracy, it is advantageous to set a frequency division ratio to a larger value with the frequency of a reference clock RCK fixed as supplied from a reference clock generation circuit 5. But the setting of the frequency division ratio at a larger value unavoidably requires a longer measuring time. So, the optimum frequency division ratio N is determined with the circuit 7 from the max. of the target frequency and the allowable error to be set in the circuit 3 thereby enabling a reduction in the measuring time and moreover, measurement is possible to the extent of a desired allowable error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency measuring device that measures the period of a signal under test by counting a reference clock and determines the frequency of the signal under test from this period.

[Summary of the invention]

The present invention provides a frequency measuring device that measures the period of a signal under test by counting a reference clock and calculates the frequency of the signal under test from this period, in which the frequency of the signal under test is divided based on a target frequency and a tolerance. By setting the ratio optimally, the measurement time can be shortened.

[Conventional technology]

When adjusting an electronic device, a frequency measuring device is used to check whether an output signal of a desired oscillation frequency is being obtained from the circuit, and whether a signal of the desired frequency is being input. As such a frequency measuring device,
It is better to waveform shape the signal under test and calculate the frequency by counting the repetition of the pulse signal over a certain period of time, or to calculate the period of the signal under test by counting the reference clock and calculate the frequency from this period. It is used.

That is, as shown in FIG. 3, for a certain period of time T1°, for example,
Gate pulse G P + of 1 second duration. is formed as shown in FIG. 3A, the gate is opened by this gate pulse GP1°, and the waveform-shaped measured signal 5IO (FIG. 3B) is supplied to the counter through this gate, and the signal is Waveform-shaped signal under measurement S, per TIO. Count the number of pulses.

This count value. Then, the signal under test S,.

The frequency f,. teeth, It is required as.

Further, as shown in FIG. 4, the gate is opened from the rising time t11 of the waveform-shaped signal under test Sa+ (FIG. 4 A) to the next rising time t1□, and the gate is opened from the time tll to the next rising time t1□.
Until t+z, the reference clock RCKI.

(B in FIG. 4) is supplied to the counter via the gate, and the reference clock RCK +
Count +. From this count value, the signal under test S,
From this, the frequency of the signal under test S11 can be found. In other words, the frequency of the reference clock RCK■ is f
ck,...If the count number is K11, then the signal under test S
The frequency f11 of No. 11 is IKth fz fCk.

It is required as.

[Problem that the invention seeks to solve]

By the way, as shown in the above-mentioned FIG.
If the gate is opened until t and the frequency is determined by counting the reference clock during this time, assuming that the frequency of the reference clock is constant, as the frequency of the signal under test increases, its period will become shorter. , the measurement error increases. Therefore, in conventional frequency measuring devices, the frequency of the signal to be measured is divided, and the gate can be opened using the frequency-divided signal. That is, if the signal to be measured is frequency-divided by N, the period is multiplied by N, and the accuracy of the dorsal side determination is improved. However, if the signal under test is frequency-divided by N in this way, the measurement time will be longer.

When adjusting electronic equipment, the target frequency and tolerance are determined. For example, when adjusting a circuit that outputs a color subcarrier frequency signal of the NTSC system, the target frequency is 3.579545 M. Hz,
If the tolerance was set at ±10Hz, the output signal of the circuit would be 3.579MHz from 3.57955MHz.
It is sufficient to adjust the frequency between 535MHz and 535MHz. Therefore, it is sufficient that the frequency measurement device can display the display with a precision corresponding to this.

However, with conventional frequency measuring devices, the frequency division ratio N is increased by increasing the measurement time to increase measurement accuracy. There is a problem in that the frequency is displayed up to a number, which wastes measurement time. When adjusting a large number of electronic devices, wasted measurement time per device becomes a major problem.

Therefore, an object of the present invention is to provide a frequency measuring device that can shorten measurement time by optimally setting the frequency division ratio N according to the target frequency and tolerance.

[Means for solving problems]

The present invention provides a frequency measuring device that divides the frequency of a signal under test, opens a gate using the divided signal, and calculates the frequency of the signal under test by counting a reference clock while the gate is open. This is a frequency measurement device that determines the gate opening time based on a target frequency and an allowable error.

[Effect]

The maximum value of the target frequency is fms*, and the tolerance is f
When the reference clock frequency u, . . . i is fck, by setting the frequency division ratio N to , it is possible to perform measurements without wasting measurement time, and to display accurately within the range of allowable errors.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Fig. 1, 1 indicates an input terminal, and a second terminal is connected to input terminal 1.
A signal under test Sl as shown in FIG. A is supplied. This signal under test S1 is waveform-shaped by the waveform shaping circuit 2 as shown in FIG.
supplied to

The frequency dividing circuit 3 is given a frequency division ratio N from the arithmetic circuit 7 . This frequency division ratio N is determined by the maximum value f□8 of the target frequency supplied from the terminal 8 and the tolerance f
Determined based on uni&.

The output of the waveform shaping circuit 2 is divided by l/N (divided by A in FIG. 2) as shown in FIG. circuit 7
supplied to

The counter 4 is supplied with a reference clock RCK shown in the second diagram from the reference clock generation circuit 5.

Counter 4 counts this reference clock RCK. The value of the counter 4 at the rising edge of the output of the frequency dividing circuit 3 shown in FIG. The output of the circuit 6 is supplied to the arithmetic circuit 7. For example, when the count value at time t2 is supplied from the counter 4 to the arithmetic circuit 7, the latch circuit 6 supplies the count value at time 1. The count value of counter 4 at is output. The arithmetic circuit 7 calculates the value of the counter 4 at time t from the count value of the counter 4 at time t8.
The count value is subtracted, and the count value from time t1 to time 1t is obtained. The period of the output signal of the frequency dividing circuit 3 is determined from this count value, and the period of the signal under test SI is determined by further dividing the period of the frequency dividing circuit 3 by 1/N. By taking the reciprocal of the period of the signal under test SI, the frequency f of the signal under test S can be found. In other words, the frequency f1 of the signal under test S1 is calculated from time t to time t2 with the frequency division ratio being N and the frequency of the reference clock RCK being fek.
Letting the count value up to K be determined as an input.

The frequency f determined by the arithmetic circuit 7 is taken out from the output terminal 9 and displayed on a display device (not shown). In addition,
In cases where the signal under test S1 includes jitter, an average value of the determined frequencies is determined every predetermined number of times, and this average value is displayed on the display device.

In order to obtain the frequency f of the signal under test Sl with high accuracy, if the frequency of the reference clock RCK is constant, the frequency division ratio N
It is advantageous to set the value to a large value. However, if an attempt is made to set the frequency division ratio N to a large value, a long measurement time will be required.

Therefore, in this embodiment, the optimum frequency division ratio N is determined from the maximum value f□8 of the target frequency and the tolerance f01.
This frequency division ratio N is set in the frequency division circuit 3. This way, no time is wasted on measurements, and
Measurements can be made to desired tolerances.

That is, if the maximum value of the target frequency is f□8, the tolerance is f□5, and the reference clock frequency is fck, then the frequency division ratio N is set to f C11ll . This allows measurement to be performed without wasting measurement time.

〔Effect of the invention〕

According to this invention, the frequency division ratio is optimally set based on the target dark wave number and the allowable error, so frequency measurement can be performed in the shortest time with the measurement accuracy of the allowable error.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a waveform diagram used to explain an embodiment of the invention, and Figs. 3 and 4 are waveform diagrams used to explain a conventional frequency measuring device. It is. Explanation of main symbols in the drawings 1: Input terminal, 3: Frequency divider circuit, 4: Counter, 7:
Arithmetic circuit. Agent Patent Attorney Tadashi Sugiura Diagram 1, L-shaped illustration Mt.
Illustration engraving I package, tffl flow number 1 average finding figure 4

Claims (1)

[Claims of Claims] A frequency in which the frequency of the signal under test is divided, a gate is opened by the divided signal, and a reference clock is counted while the gate is open to find the frequency of the signal under test. A frequency measuring device, wherein the time to open the gate is determined based on a target frequency and a tolerance.