JP2007010593A - Frequency measurement circuit, and vibration sensor type differential pressure/pressure transmitter using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain influence due to noise and jitters generated accompanying acceleration, while improving the frequency measuring resolution of a signal to be measured, without making the standard clock frequency high. <P>SOLUTION: The system comprises a comparison signal generation circuit which generates a comparison signal of the frequency that is close to the frequency to the frequency to be measured, a heterodyne circuit which generates a differential frequency signal that inputs the signal to be measured and the comparison signal, a frequency counter which counts the standard clock where the passage is controlled by the differential frequency signal, and a calculating circuit which calculates the frequency of the signal to be measured, based on the counted value of the frequency counter and the frequency of the comparison signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a frequency measurement circuit capable of measuring the frequency of a signal under measurement with high speed and high resolution without increasing the speed of a reference clock, and a vibration sensor type differential pressure / pressure transmitter using the frequency measurement circuit. is there.

  FIG. 4 is a functional block diagram showing a basic configuration of a frequency measurement circuit used in a conventional vibration sensor type differential pressure / pressure transmitter. The vibration type pressure / differential pressure sensor 1 outputs a measured signal Fp having a frequency corresponding to the measurement pressure or the differential pressure. A reference clock generator 2 generates a reference clock CLK having a frequency higher than the frequency of the signal under test Fp.

  The signal to be measured Fp is input to the synchronization circuit 31 of the frequency counter 3 and converted into a signal Fs synchronized with the rising edge of the reference clock CLK. The signal Fs and the reference clock CLK are input to the counter 32. The counter 32 counts the reference clock CLK for one period of the signal Fs or an integer multiple thereof, and measures the frequency of the signal under measurement Fp. This frequency data is input to the arithmetic circuit 4 realized by the function of the CPU, and the differential pressure or pressure is calculated. Reference numeral 5 denotes an internal bus of the CPU.

  FIG. 5 is a time chart of the synchronization circuit 31. The reference clock CLK shown in (A) is a pulse signal having a constant frequency. The signal under measurement Fp shown in (B) is a signal having a frequency considerably lower than that of the reference clock CLK, and is not synchronized with the reference clock. The synchronization circuit 31 samples the signal under measurement Fp at the rising edge of the reference clock CLK. Therefore, the output Fs of the synchronization circuit 31 changes in synchronization with the rising edge of the reference clock CLK as shown in (C). The gate time represents a unit period during which the counter 32 counts the signal Fs and the reference clock CLK.

  In such a basic configuration, when the gate time is shortened for the purpose of speeding up the transmitter, the frequency of the reference clock CLK must be increased in order to ensure the same resolution. Since the power consumption increases when the frequency is increased, it is difficult to apply to a two-wire differential pressure / pressure transmitter. FIG. 3 is a functional block diagram of the frequency measurement circuit disclosed in Patent Document 1. In FIG. The feature of this circuit is that high speed is realized without increasing the frequency of the reference clock CLK.

  The synchronization circuit 6 has the same function as the synchronization circuit 31 in FIG. Reference numeral 7 denotes a time difference detection circuit which receives the signal to be measured Fp of the vibration type pressure / differential pressure sensor 1 and the output Fs of the synchronizing circuit 6 and becomes low level at the rising edge of the signal to be measured Fp. A signal Tin that becomes high level at the rising edge is output. That is, the output Tin of the time difference detection circuit 7 is a signal having a pulse width corresponding to the time difference between the signals to be measured Fp and Fs.

  Reference numeral 8 denotes a time width expansion circuit which receives the output Tin of the time difference detection circuit 7 and outputs a signal Tout having a pulse width of the output Tin, that is, a pulse width obtained by expanding the low level period by a predetermined magnification.

  Reference numeral 9 denotes a first counter, which counts the reference clock CLK for one period of the output Fs or an integral multiple thereof. That is, the counter 9 performs the same operation as the counter 32 described with reference to FIG.

  Reference numeral 10 denotes a second counter that receives the output Tout of the time width expanding circuit 8 and the reference clock CLK, and counts the reference clock CLK during a period when the pulse width of the output Tout, that is, Tout is low. The arithmetic circuit 4 realized by the CPU function acquires the count values of the first counter 9 and the second counter 10 via the bus 5.

  The arithmetic circuit 4 divides the count value of the second counter 10 by the magnification by which the time width expansion circuit 8 expands the pulse width of the input signal, and adds this division result to the count value of the first counter 9 to thereby generate vibration. The frequency of the signal to be measured Fp of the pressure / differential pressure sensor 1 is calculated. Moreover, a pressure value is calculated from this frequency.

  Prior art documents related to a frequency measurement circuit and a vibration sensor type differential pressure / pressure transmitter using the frequency measurement circuit include the following.

JP 2004-198393 A

The configuration according to the prior art has the following problems.
(1) In the basic configuration shown in FIG. 4, when the frequency of the reference clock is increased in order to increase the speed, power consumption increases and it is difficult to apply to a two-wire differential pressure / pressure transmitter. .

(2) With the configuration shown in FIG. 3, it is possible to speed up the measurement without increasing the frequency of the reference clock. However, since the gate time is shortened as the speed is increased, noise and jitter superimposed on the signal under measurement increase the influence of deteriorating measurement accuracy, but this influence cannot be suppressed.

  Therefore, the problem to be solved by the present invention is to improve the frequency measurement resolution of the signal under measurement without increasing the frequency of the reference clock, and to suppress the influence of noise and jitter that accompany the increase in speed. The object is to realize a possible frequency measurement circuit and a vibration sensor type differential pressure / pressure transmitter using the same.

In order to achieve such an object, the configuration of the present invention is as follows.
(1) a comparison signal generation circuit for generating a comparison signal having a frequency close to the frequency of the signal under measurement;
A heterodyne circuit that inputs the signal under measurement and the comparison signal and generates a differential frequency signal of both;
A frequency counter that counts a reference clock whose passage is restricted by the differential frequency signal;
An arithmetic circuit for calculating the frequency of the signal under measurement based on the count value of the frequency counter and the frequency of the comparison signal;
A frequency measurement circuit comprising:

(2) The frequency measurement circuit according to (1), wherein the comparison signal generation circuit generates a comparison signal obtained by dividing the reference clock.

(3) The frequency measurement circuit according to (1) or (2), wherein the heterodyne circuit includes a low-pass filter.

(4) a comparison signal generating circuit for generating a comparison signal having a frequency close to the frequency of the signal under measurement from the vibration type differential pressure / pressure sensor;
A heterodyne circuit that inputs the signal under measurement and the comparison signal and generates a differential frequency signal of both;
A frequency counter that counts a reference clock gated with the differential frequency signal;
An arithmetic circuit for calculating the frequency of the signal under measurement based on the count value of the frequency counter and the frequency of the comparison signal;
A vibration sensor type differential pressure / pressure transmitter characterized by comprising:

(5) The vibration sensor type differential pressure / pressure transmitter according to (4), wherein the comparison signal generating circuit generates a comparison signal obtained by dividing the reference clock.

(6) The vibration sensor differential pressure / pressure transmitter according to (4) or (5), wherein the terodyne circuit includes a low-pass filter.

As is apparent from the above description, the present invention has the following effects.
(1) Using a heterodyne circuit, a differential frequency signal between the frequency of the signal under measurement and the frequency of the comparison signal is generated, and the frequency to be measured is based on the value obtained by counting the reference clock regulated by the differential frequency signal and the frequency of the comparison signal. By calculating the frequency of the measurement signal, high speed and high resolution can be realized without increasing the frequency of the reference clock.

(2) With respect to noise and jitter, the high-frequency component of jitter can be removed by a low-pass filter in the heterodyne circuit, so that the influence of noise and jitter superimposed on the signal under measurement deteriorating measurement accuracy can be suppressed. .

(3) As for the frequency of the comparison signal, it is possible to generate an accurate frequency signal by dividing the reference clock by a predetermined ratio, and it is possible to ensure calculation accuracy.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a functional block diagram showing an embodiment of a frequency measuring circuit to which the present invention is applied and a vibration sensor type differential pressure / pressure transmitter using the same. The same elements as those in the conventional circuit described with reference to FIG. Hereinafter, the characteristic part of the present invention will be described.

  In FIG. 1, reference numeral 100 denotes a heterodyne circuit that forms a feature of the present invention. This heterodyne circuit includes a multiplier 101, a low-pass filter 102, and a binarizer 103.

  Reference numeral 200 denotes a comparison signal generation circuit. In this embodiment, the comparison signal generation circuit 200 includes a frequency division circuit 201, which generates a comparison signal Fc having a frequency CLK / n obtained by dividing the reference clock CLK by a predetermined frequency division ratio n to the heterodyne circuit 100. Output.

  The multiplier 101 of the heterodyne circuit 100 inputs the signal to be measured Fp and the comparison signal Fc, and generates a sum component (Fp + Fc) and a difference component (Fp−Fc) of both frequencies. Since the input to the multiplier 101 is a digital signal, the multiplier 101 is composed of an element for exclusive OR operation.

  The output of the multiplier 101 is input to the low pass filter 102. The low-pass filter 102 is an analog filter for extracting only the difference component from the sum and difference components of the frequencies generated by the multiplier 101.

  The difference component of the analog signal extracted by the low-pass filter 102 is returned to the digital signal by the binarizer 103 again. The binarizer 103 is a comparator. If the frequency of the output signal is the difference frequency Fd and the frequencies of the signals Fs and Fc are Fs and Fc, the difference frequency Fd is Fd = (Fp−Fc). This difference frequency Fd is input to the frequency counter 3.

  The frequency counter 3 has the same function as the conventional circuit described with reference to FIG. 4, and the differential frequency Fd is synchronized with the reference clock CLK by the synchronization circuit 31, and the passage of the reference clock CLK is regulated by the synchronization signal by the counter 32. The reference clock CLK is counted. The count result is taken into the arithmetic circuit (CPU) 4 through the bus 5.

  When the frequency dividing circuit 201 of the comparison signal generating circuit 200 employs a configuration that divides the reference clock CLK and generates the comparison signal Fc input to the heterodyne circuit 100 as in the embodiment, the frequency division ratio n is commanded from the CPU 4 through the bus 5. The frequency division ratio n is set in advance so as to be a predetermined differential frequency Fd based on the frequency span of the signal under measurement Fp from each sensor.

  The arithmetic circuit (CPU) 4 gives a command of the frequency division ratio n to the frequency dividing circuit 201 and compares the difference frequency Fd of the heterodyne circuit 100 calculated by taking in the data from the frequency counter 3 and the comparison signal generating circuit 200. From the signal frequency Fc, the frequency Fp of the signal under measurement is calculated by Fp = (Fd + Fc).

  In general, the frequency that can be measured by the frequency counter 3 is determined by the time resolution of the frequency counter 3 and the measurement time. If the frequency of the reference clock CLK is sufficiently higher than the input frequency of the frequency counter 3, the number of effective digits of the measurement result can be regarded as constant regardless of the input frequency.

  This means that a signal having a lower frequency can be measured to a smaller order. Therefore, the frequency Fp of the original signal under measurement obtained by adding the measurement result of the frequency counter that has measured the differential frequency Fd that is lower than the original signal frequency Fp through the heterodyne circuit 100 and the known frequency Fc. The number of effective digits of the measurement result is increased compared to when the heterodyne circuit is not used, and as a result, the frequency resolution is improved.

  When the frequency span of the signal under measurement Fp is 120 to 130 kHz, when the frequency of the comparison signal Fc is selected to be 110 kHz, the differential frequency Fd is 10 to 20 kHz. The resolution improvement effect expected at this time is approximately 10 to 5 times.

  FIG. 2 is a functional block diagram showing the configuration of another embodiment of the present invention. The feature of this configuration is a combination configuration in which the differential frequency Fd of the heterodyne circuit 100 of the present invention described in FIG. 1 is used as the input of the frequency measurement circuit disclosed in Patent Document 1 described in FIG. With such a combination configuration, the resolution can be further improved.

  The function of the low-pass filter 102 in the heterodyne circuit 100 introduced in the present invention is in addition to the function as an analog filter for extracting only the difference component from the sum and difference components of the frequencies generated by the multiplier 101. Thus, it has a function of suppressing the influence of noise and jitter generated with the increase in speed, and can solve the problems of the prior art disclosed in Patent Document 1 described in FIG.

  In the embodiment of FIG. 1, the frequency dividing circuit 201 that divides the reference clock CLK is exemplified as means for generating the comparison signal Fc. However, the frequency dividing circuit 201 is not limited to this configuration, and stable oscillation that outputs a known frequency signal is possible. It is also possible to employ a circuit.

It is a functional block diagram showing one embodiment of a frequency measuring circuit to which the present invention is applied and a vibration sensor type differential pressure / pressure transmitter using the same. It is a functional block diagram which shows the structure of other embodiment of this invention. 2 is a functional block diagram of a frequency measurement circuit disclosed in Patent Document 1. FIG. It is a functional block diagram which shows the basic composition of the frequency measurement circuit used with the conventional vibration sensor type differential pressure / pressure transmitter. It is a time chart of a synchronous circuit.

Explanation of symbols

1 Vibrating Pressure / Differential Pressure Sensor 2 Reference Clock Generator 3 Frequency Counter 31 Synchronous Circuit 32 Counter 4 Arithmetic Circuit (CPU)
5 Internal Bus 100 Heterodyne Circuit 101 Multiplier 102 Low Pass Filter 103 Binarizer 200 Comparison Signal Generation Circuit 201 Frequency Dividing Circuit

Claims (6)

A comparison signal generating circuit for generating a comparison signal having a frequency close to the frequency of the signal under measurement;
A heterodyne circuit that inputs the signal under measurement and the comparison signal and generates a differential frequency signal of both;
A frequency counter that counts a reference clock whose passage is restricted by the differential frequency signal;
An arithmetic circuit for calculating the frequency of the signal under measurement based on the count value of the frequency counter and the frequency of the comparison signal;
A frequency measurement circuit comprising:   The frequency measurement circuit according to claim 1, wherein the comparison signal generation circuit generates a comparison signal obtained by dividing the reference clock.   The frequency measurement circuit according to claim 1, wherein the heterodyne circuit includes a low-pass filter. A comparison signal generation circuit for generating a comparison signal having a frequency close to the frequency of the signal under measurement from the vibration type differential pressure / pressure sensor;
A heterodyne circuit that inputs the signal under measurement and the comparison signal and generates a differential frequency signal of both;
A frequency counter that counts a reference clock gated with the differential frequency signal;
An arithmetic circuit for calculating the frequency of the signal under measurement based on the count value of the frequency counter and the frequency of the comparison signal;
A vibration sensor type differential pressure / pressure transmitter characterized by comprising:   5. The vibration sensor type differential pressure / pressure transmitter according to claim 4, wherein the comparison signal generation circuit generates a comparison signal obtained by dividing the reference clock. The vibration sensor type differential pressure / pressure transmitter according to claim 4, wherein the terodyne circuit includes a low-pass filter.

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