JP3204175B2 - Clock phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit for generating a clock phase-locked to an input signal.
The present invention relates to a clock phase synchronization circuit that processes a phase comparison result as a digital value.

[0002]

2. Description of the Related Art In this kind of clock phase synchronization circuit,
As a clock phase synchronization circuit for processing a phase comparison result as a digital value, for example, there is a circuit disclosed in Japanese Patent Application Laid-Open No. 63-46814 as a first prior art.
FIG. 6 is a block diagram showing a typical embodiment of the conventional clock phase synchronization circuit. In FIG. 5, an input signal dividing circuit 2 divides an input signal 200 to a phase comparison frequency and outputs a reference comparison clock 201 to a phase comparison circuit 6 described later. The frequency dividing circuit 3 divides an output signal 1201 of the reference signal frequency dividing circuit 12 described later to a phase comparison frequency and outputs a comparison clock 301 to the phase comparing circuit 6 described later. The phase comparison circuit 6 includes the reference comparison clock 201
And a phase comparison signal 301, and outputs a phase comparison signal 601. The division number control circuit 11 outputs a divided signal 1101 to a reference signal division circuit 12 described below according to an output phase comparison signal 601 of the phase comparison circuit 6 and an output dead band control signal 1301 of a dead band control circuit 13 described below.
Is output. The reference oscillator 14 is a reference signal 14 serving as an original signal of an output signal 1201 of a reference signal dividing circuit 12 described later.
01 is output. The reference signal dividing circuit 12 divides the above-described reference signal 1401 from the reference oscillator 14 according to the above-mentioned divided signal 1101 of the dividing number control circuit 11 and outputs it as an output signal 1201 and also outputs the phase information 1201.
2 is output to the dead zone control circuit 13 described later. The dead zone control circuit 13 generates a dead zone control signal 1301 from the output phase information 1202 of the above-described reference signal frequency dividing circuit 12,
Output.

Next, the operation will be described. In the first prior art clock phase locked loop circuit shown in FIG.
The reference signal 1401 output from the reference oscillator 14 is used as a reference, and the reference signal dividing circuit 12 divides the frequency to generate an output signal 1201. The number of divisions performed by the reference signal dividing circuit 12 is determined by the following control. The phase comparison circuit 6 detects the phase difference between the reference comparison clock 201 obtained by dividing the input signal 200 and the comparison clock 301 obtained by dividing the output signal 1201 of the reference signal dividing circuit 12. This phase difference is treated as a digital value, and the frequency division number is changed by the frequency division number control circuit 11 so that the phase synchronization between the input signal 200 and the output signal 1201 is established. At this time, the division number control circuit 11 detects a minute stationary phase difference generated between the input signal 200 and the output signal 1201 and changes the division number, which may cause jitter. For this reason, a dead zone control circuit 13 is provided to keep the frequency division number unchanged when the phase difference between the input signal 200 and the output signal 1201 is within a certain range.

The above-mentioned first prior art clock phase synchronization circuit obtains a desired clock frequency by changing the frequency division number of the output of the reference oscillator. On the other hand, there is a conventional clock phase locked loop circuit that uses a voltage controlled oscillator that controls the frequency of an output signal with a voltage that is an analog signal and uses the phase difference information as a digital value.

FIG. 7 is a block diagram showing a second prior art clock phase locked loop circuit used in a voltage controlled oscillator. In FIG. 7, an input signal dividing circuit 2
0 to the phase comparison frequency, and
1 is output to a phase comparison circuit 6 described later. The frequency dividing circuit 3 divides an output signal 401 of a voltage controlled oscillator 4 described later into a phase comparison frequency, and outputs a comparison clock 301 to a phase comparison circuit 6 described later. The phase comparison circuit 6 detects a phase difference between the above-described reference comparison clock 201 and the above-described comparison clock 301, and outputs a phase comparison signal 601 to a phase difference sampling circuit 8 described later. The phase difference detection oscillator 15 outputs a phase difference detection signal 1501 as a reference for phase difference detection.
Is output. In accordance with the control signal generating circuit 16 the phase difference detection signal 1501 described above, the sampling clock 1601 having a frequency (f _s) of N times the phase comparison frequency (f _r) (N is an integer of 2 or more), the phase comparison period Latch signal 1
602 is output. In other words, the relationship of f _s = Nf _r holds. The phase difference sampling circuit 8 converts the above-described phase comparison signal 601 into the above-described sampling clock 1601.
And outputs the sampled digital value as a digital phase comparison signal 801 to a phase control information latch circuit 10 described later. The phase control information latch circuit 10 latches the above-described digital phase information 801 at the cycle of the latch signal 1602 and outputs it as digital phase comparison information 1001. The D / A conversion circuit 9 is a circuit for converting the above-mentioned digital phase comparison information 1001 into a phase comparison voltage 901 which is an analog value. The loop filter 7 suppresses the above-mentioned harmonic components of the phase comparison voltage 901 and forms a secondary loop of the clock phase synchronization circuit. The voltage controlled oscillator 4 is a circuit that changes the frequency of the output signal 401 according to the control voltage 701 from the loop filter 7 described above.

Next, the operation will be described. 7, a reference comparison clock 201 obtained by dividing an input signal 200 to a phase comparison frequency and a comparison clock 301 obtained by dividing an output signal 401 of a voltage controlled oscillator 4 to a phase comparison frequency. Is detected by the phase comparison circuit 6, and a phase comparison signal 601 is output. The phase comparison signal 601 is counted by the sampling clock 1601 generated in the control signal generation circuit 16, and a digital phase comparison signal 801 is generated.
By latching the digital phase comparison signal 801 with the latch signal 1602 having the same frequency as the phase comparison frequency, the phase difference between the reference comparison clock 201 and the comparison clock 301 detected by the phase comparison circuit 6 can be compared with the digital phase comparison information 10.
01 can be output. The digital phase comparison information 1001 is converted into a phase comparison voltage 90 by the D / A conversion circuit 9.
After being converted to 1 and passing through the loop filter 7, it is input to the voltage controlled oscillator 4 as a control voltage 701. The voltage controlled oscillator 4 receives the input signal 20 according to the control voltage 701.
The frequency of the output signal 401 is controlled so that phase synchronization with 0 is established, and the output signal 401 is output.

Further, the detailed operation will be described with reference to a time chart. FIG. 8 is a time chart for explaining a change in digital value when the phase comparison signal changes in the clock phase synchronization circuit according to the second prior art shown in FIG. In FIG. 7, the sampling clock 16
01 is a signal having the waveform shown in FIG. FIG. 8B shows a waveform when the phase comparison signal 601 fluctuates slightly for one cycle or less of the sampling clock 1601.
(C), (d) and (e) show. FIG. 8F shows a waveform when the phase comparison signal 601 fluctuates for one cycle or more of the sampling clock 1601. The phase difference sampling circuit 8 samples the portion where the phase comparison signal 601 is "1", and sets the number as a digital value.
Since the frequency of the sampling clock 1601 is N times the phase comparison frequency, FIGS.
In (d) and (e), the sampled digital values of all the phase comparison signals 601 are n (n is 0 < n <N).
Is an integer). Further, in FIG. 8F, since the phase comparison signal 601 fluctuates for one cycle or more of the sampling clock 1601, the sampled digital value becomes (n-1).

An operation of latching a sampled digital value will be described with reference to FIG. FIG.
5 is a time chart showing latch intervals of digital values in a conventional clock phase detection circuit. In FIG. 9, the latch signal 1602 is represented by a waveform shown in FIG. In the conventional clock phase synchronization circuit, the frequency of the latch signal 1602 is the same as the phase comparison frequency. However, since the circuit configuration does not guarantee phase synchronization, the phase comparison signal 601 is generated as shown in FIGS. As shown in FIG. 9C, the case where all "1" portions of the phase comparison signal 601 are included in the latch cycle of the latch signal 1602 (FIG. 9B).
There are two types of phase relationships: a case where all the “0” portions of the phase comparison signal 601 are included (FIG. 9B). Here, the period of the phase comparison signal is represented by a, and the duty is 5
0%. Further, the latch cycle is set to b. The phase comparison period a and the latch period b are not exactly equal. FIG. 4 (b)
In the case of the phase relationship shown by, the period during which the phase comparison signal in the latch cycle is "1" is (a / 2), and in the case of the phase relationship shown in FIG. 9C, the phase comparison signal in the latch cycle is " The period of 1 "is (ba / 2). In the phase control information latch circuit 10 of FIG. 7, the digital value sampled during the above-described period is used as digital phase comparison information 1001.
Output.

In the second prior art clock phase locked loop circuit shown in FIG. 7 described above, in order to convert the phase comparison result into a digital value, it is possible to carry out digital processing while holding this digital value. , An LSI or the like.

[0010]

A first problem is that it is difficult to obtain a high-stability output signal without jitter and wander in a steady state.

The reason is that, in the clock phase synchronization circuit of the first prior art as shown in FIG. 6, in order to improve the accuracy of the output signal, the number of divisions which can be changed by the reference signal division circuit 12 is increased. Need to do so, the reference oscillator 14
However, it is difficult to create a high-frequency reference oscillator 14, which causes jitter and wander in the output signal. Furthermore,
This is because the division control in the synchronous state is slowed down by the dead zone control circuit 13, so that the detection of the minute phase fluctuation is delayed, and wander is generated in the output signal.

Also, in the second prior art clock phase synchronization circuit as shown in FIG. 7, when the phase comparison signal 601 fluctuates minutely within one cycle of the sampling clock 1601, as described in FIG. Another reason is that jitter and wander occur in the output signal due to a quantization error that cannot detect fluctuation as a digital value. Further, when the result of the phase difference sampling is latched, as described with reference to FIG. 9, the output signal is generated by the difference generated in the digital phase information generated due to the existence of two types of phase relationships between the phase comparison signal 601 and the latch signal 1602. Another reason is that jitter and wander components occur.

[0013] The second problem is that the circuit configuration becomes complicated.

The reason is that, in the conventional clock phase synchronization circuit as shown in FIG. 6, if the number of frequency divisions which can be changed by the reference signal frequency division circuit 12 is increased, the circuit scale increases.
Another reason is that when the frequency of the reference oscillator 14 is increased, the operating frequency of the circuit is increased, which complicates the circuit configuration and makes implementation difficult.

In the conventional clock phase synchronization circuit as shown in FIG. 7, when the frequency of the sampling clock is increased to reduce the quantization error, the operation frequency of the phase difference sampling circuit 8 is increased, and the circuit scale is reduced. Increase,
Another reason is that it is difficult to realize a circuit.

As described above, an object of the present invention is to provide a clock phase synchronization circuit capable of reducing jitter and wander of an output signal without increasing a circuit operating frequency.

[0017]

According to the present invention, there is provided a clock phase locked loop circuit which receives an input signal and generates a clock phase-locked by a digital phase locked loop (PLL). , The result of the phase comparison between the input signal and the PLL output is represented by the sampling clock frequency fs ′ and the phase comparison frequency.
Assuming that the number is fr and the frequency deviation of the input signal is α, Nfr (1 + α) <fs ′ <(N + 1) fr (1-α) or (N−1) fr (1 + α) <fs ′ <Nfr (1-α The sampling is performed at a sampling clock frequency offset so that (N is an integer of 2 or more) .

A frequency dividing means for dividing an input signal into a comparison signal to generate a reference comparison clock, and a reference clock obtained by dividing the reference comparison clock and an output signal, and detecting a phase difference therebetween. Phase comparing means, a phase difference detecting signal oscillating means for outputting a phase difference detecting signal with an offset as a reference for phase difference detection , and sampling based on the output of the phase difference detecting signal with the offset and the phase comparing means. Clock frequency fs', phase comparison cycle
Assuming that the wave number is fr and the frequency deviation of the input signal is α, Nfr (1 + α) <fs ′ <(N + 1) fr (1-α) or (N−1) fr (1 + α) <fs ′ <Nfr (1-α ) (phase difference N is to the pseudo sync control signal generating means, an output of said phase comparing means to enter the offset-sampling clock sampling to output an integer of 2 or more) the offset-sampling clock and the pseudo sync latch signal Sampling means; phase control information latch means for latching the output of the phase difference sampling means based on the period of the pseudo-synchronous latch signal; and D / A conversion means for converting the output of the phase control information latch means to an analog value. Oscillating means for receiving the output of the D / A conversion means via a loop filter and generating the output signal.

The sampling clock frequency f _s ′
, The phase comparison frequency of f _r, When the frequency deviation of the input signal _{α, Nf r (1 + α} ) <f s'<(N + 1) f r (1-α)
Or _{(N-1) f r (} 1 + α) <f s'<Nf r (1-α) (N is an integer of 2 or more), wherein the given said offset frequency such that.

Since the phase fluctuation smaller than the sampling interval can be detected by the sampling clock with offset, and the voltage controlled oscillator is controlled based on the digital control information corresponding thereto, jitter and wander of the output signal can be reduced.

Since the phase relationship between the pseudo-synchronous latch signal and the phase comparison signal is fixed by the pseudo-synchronous latch signal that is pseudo-synchronized with the phase comparison signal, it is possible to prevent the digital control information from changing as the phase relationship changes. Thus, jitter and wander of the output signal of the voltage controlled oscillator can be reduced.

[0022]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating an embodiment of a clock phase synchronization circuit according to the present invention.

In FIG. 1, an input signal dividing circuit 2 divides an input signal 200 to a phase comparison frequency and outputs a reference comparison clock 201. The frequency dividing circuit 3 divides an output signal 401 of a voltage controlled oscillator 4 described later to a phase comparison frequency and outputs a comparison clock 301. The phase comparison circuit 6
The reference comparison clock 201 and the comparison clock 301 described above.
And outputs a phase comparison signal 601.
The phase difference detection oscillator with offset 1 outputs a phase difference detection signal with offset 101 serving as a reference for phase difference detection. This offset will be described below.

[0024] This offset is relative to the reference frequency f _r with the phase difference detection signal 1501 of the phase difference detection oscillator 15 shown in FIG. 7, remembering a predetermined frequency offset in accordance with the frequency deviation of the input signal 200 That means.

That is, the frequency of the input signal 200 is f
_Assuming that there is a frequency deviation of α with respect to _r , the reference frequency _fr ′ of the offset-added phase difference detection signal 101 has the following equation: _fr (1−α) < _fr ′ < _fr (1 + α) (1) Have a relationship.

The frequency deviation α of the input signal is determined by extracting the clock frequency component of the input signal in advance and actually measuring the frequency, or based on the maximum value of the reference clock frequency stability of the input signal if known. You can know by doing. The quasi-synchronous control signal generation circuit uses the above-described comparison clock 301 and uses the above-described phase comparison signal 601 according to the above-described phase difference detection signal with offset 101.
Sampling clock 501 with an offset for sampling data and a digital phase comparison signal
A pseudo-synchronous latch signal 502 for latching 1 in the phase comparison cycle is output. Assuming that the frequency of the offset-added sampling clock is f _s ′, the frequency does not become an integral multiple of f _s ′. This relationship will be described with reference to the drawings.

FIG. 2 is a diagram for explaining the sampling clock frequency. F _s in the figure shows the sampling clock frequency when not having a conventional offset, have a relationship of f _s = Nf _r.

In order to determine the sampling clock f _s ′ of the present invention, an integer multiple frequency (N−1) before and after f _s is determined.
f _r, it is necessary to take into account the (N + 1) f _r.

[0029] Then, in the figure, the sampling clock _{(N-1) f r,} Nf r, with respect to (N + 1) f _r, the case where the offset error of the input signal is present, are illustrated. As a result, the setting region of the sampling frequency f _s ′ with offset of the present invention is the frequency region shown in the region before and after f _s .

[0030] That is, for the region _{(N-1) f r (} 1 + α) <f s '<Nf r (1-α) (2) Nf r (1 + α) is the region _{<f s'<(N +} 1) f _r (1−α) (3) The phase difference sampling circuit 8 samples the above-described phase comparison signal 601 with the above-described sampling clock with offset 501, and outputs the sampled digital phase comparison signal 801 to the phase control information latch circuit 10 described later. The phase control information latch circuit 10 latches the above-described digital phase comparison signal 801 at the period of the pseudo-synchronous latch signal 502, and outputs digital phase comparison information 1001. D / A conversion circuit 9
Converts the digital phase comparison information 1001 into a phase comparison voltage 901 which is an analog value and outputs the same. The loop filter 7 removes the harmonic component of the phase comparison voltage 901 described above, forms a secondary loop of the clock phase locked loop, and outputs the control voltage 701. The voltage controlled oscillator 4 receives the input signal 200 according to the control voltage 701 described above.
Output signal 401 whose frequency is controlled so as to be phase-synchronized with
Is output.

Next, the operation will be described. FIG. 3 is a time chart showing the steady state operation in FIG. 1 and 3, the input signal dividing circuit 2 divides the input signal 200 into a phase comparison frequency and outputs a reference comparison clock 201 with a waveform shown in FIG. The frequency dividing circuit 3 outputs a comparison clock 301 obtained by dividing the output signal 401 to a phase comparison frequency with a waveform shown in FIG.
The phase comparison circuit 6 compares the phases of the reference comparison clock 201 and the comparison clock 301, and a phase comparison signal 601 representing the phase difference as a duty ratio as shown in FIG.
Is output. The offset-added phase difference detection oscillator 1 outputs the offset-added phase difference detection signal 1 serving as a reference for detecting the phase difference.
01 is output. The pseudo-synchronous control signal generating circuit 5 outputs the sampling clock with offset 501 used in the phase difference sampling circuit with the waveform shown in FIG.
In accordance with the phase difference detection signal 10 with offset, a pseudo-synchronous latch signal 502 which is pseudo-synchronized with the phase comparison frequency with the waveform shown in FIG. The phase difference sampling circuit 8 samples the phase comparison signal 601 using a sampling signal with an offset, and samples the digital value. As shown in FIG. 3 (f), the digital phase comparison signal 801 counts up by the sampling clock with offset when the phase comparison signal 601 is "1", and counts off when the phase comparison signal 601 is "0". Is the digital value of the result. The phase control information latch circuit 10 latches the digital phase comparison signal 801 at the period of the pseudo-synchronous latch signal 502 which is pseudo-synchronized with the phase comparison period shown in FIG. The digital phase comparison information 1001 is output with the waveform shown in FIG. The digital phase comparison information 1001 is D /
The signal is converted into a voltage that is an analog value by the A conversion circuit 9 and output as a phase comparison voltage 901. Phase comparison voltage 901
Is input to the voltage-controlled oscillator 4 as the control voltage 701 after the harmonic component is removed by the loop filter 7. The voltage controlled oscillator 4 operates at a frequency corresponding to the control voltage 701 as shown in FIG.
An output signal 401 shown in (h) is output.

Hereinafter, a method for obtaining a highly accurate output signal in the clock phase synchronization circuit of the present invention will be described. First, the mechanism of phase difference detection will be described. FIG. 4 is a time chart illustrating a mechanism for detecting a phase difference without generating a quantization error in one embodiment of the clock phase synchronization circuit of the present invention. In FIG.
The sampling clock 501 with offset is shown in FIG.
It is represented by the waveform shown in FIG. 4 (b), (c),
(D) and (e) are phase comparison signals 601 having no duty fluctuation. Although the frequency of the sampling clock 1601 already described with reference to FIG. 7 is N times the phase comparison frequency, the sampling clock with offset 501 has a frequency offset greater than the frequency deviation of the input signal 200 on the frequency of the sampling clock 1601. In addition, even if the phase comparison signal 601 has the same duty, the phase relationship between the phase comparison signal 601 and the sampling clock 501 with offset is different. Thereafter, n is set to 0 ≦ n
An explanation will be given assuming that an integer satisfying ≤N, t is a sampling period, and α is a small phase fluctuation of t or less. FIG. 4 (b),
In (e), the digital value is (n + 1), and FIG.
In (c) and (d), the digital value is n. The ratio of the digital value between n and (n + 1) depends on the phase comparison signal 60
The time (nt + α) when 1 becomes “1” depends on α / t. For example, when α = t / 4, the ratio of the digital value to n is 75%, and the ratio of the digital value to (n + 1) is 25%. Therefore, for the latch cycle,
Considering a sufficiently long time, the digital control information can accurately detect the duty fluctuation of the phase comparison signal shorter than the sampling period.

Next, the pseudo-synchronous latch signal will be described. FIG. 5 is a time chart illustrating a mechanism for generating a latch signal in a pseudo-synchronous manner with a comparison clock in one embodiment of the clock phase synchronization circuit of the present invention. In FIG. 5, the phase difference detection signal with offset 101 is represented by the waveform shown in FIG. The comparison clock 301 is represented by a waveform shown in FIG. FIG.
In the pseudo-synchronous control signal generation circuit, a counter circuit is used to count up at the rising edge of the phase difference detection signal 101 with offset. At this time, when the comparison clock 301 becomes "1" as shown in FIG. 5C, the counter value of the counter circuit is set to 0. Thereafter, when the count-up is advanced and the count value becomes N, a convex pulse of the pseudo-synchronous latch signal 502 is output as shown in FIG. The value of N is, as shown in FIG.
Considering the period of the phase comparison signal 601, the phase comparison signal 6
The period is set so as to be a period of “0” of 01.
In the steady state, the duty cycle of the phase comparison signal 601 is almost 50%, and considering that there is no variation exceeding the frequency deviation of the input signal, the value of N is "0" in the phase comparison signal. Should be set to about 1/2 of the value. The rising edge of the pseudo-synchronous latch signal 502 generated as described above always exists in the "0" part of the phase comparison signal 602, and it can be said that the pseudo-synchronization latch signal 502 is pseudo-synchronized with the phase comparison signal. By using the pseudo-synchronous latch signal 502, it is possible to eliminate a sampling error caused by a change in the phase relationship between the latch signal 1602 and the phase comparison signal 601 described above.

[0034]

The first effect is that the jitter and wander of the output signal can be reduced.

The reason for this is that the phase difference sampling circuit can detect a phase fluctuation smaller than the period of the sampling clock, so that the voltage controlled oscillator can be controlled with high-precision digital phase control information corresponding thereto. is there. In addition, in the phase control information latch circuit, the phase relationship between the phase comparison signal and the latch signal does not change, and accurate phase control information can be always detected. This is because the oscillator can be controlled.

The second effect is that the circuit configuration is easy.

The reason is that it is only necessary to apply an offset of about the frequency deviation of the input signal to the sampling clock, and it is not necessary to operate the circuit at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a clock phase synchronization circuit according to the present invention.

FIG. 2 is a diagram illustrating a sampling clock frequency with offset in FIG. 1;

FIG. 3 is a time chart illustrating a steady state operation of the clock phase locked loop circuit of FIG. 1;

FIG. 4 is a time chart illustrating a mechanism for detecting a phase difference without generating a quantization error in the clock phase synchronization circuit of FIG. 1;

5 is a time chart for explaining a mechanism for generating a latch signal in a pseudo-synchronous manner with a comparison clock in the clock phase synchronization circuit of FIG. 1;

FIG. 6 is a block diagram illustrating a clock phase synchronization circuit according to a first related art.

FIG. 7 is a block diagram illustrating a clock phase synchronization circuit according to a second related art.

8 is a time chart illustrating a change in a digital value when a phase comparison signal changes in the clock phase synchronization circuit of FIG. 6;

FIG. 9 is a time chart for explaining a latch timing generated in the clock phase synchronization circuit of FIG. 6;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase difference detection oscillator with offset 2 input signal divider circuit 3 divider circuit 4 voltage controlled oscillator 5 pseudo-synchronous control signal generation circuit 6 phase comparison circuit 7 loop filter 8 phase difference sampling circuit 9 D / A conversion circuit 10 phase control information Latch circuit 11 Frequency division control circuit 12 Reference signal frequency division circuit 13 Dead zone control circuit 14 Reference oscillator 15 Phase difference detection oscillator 16 Control signal generation circuit 101 Phase difference detection signal with offset 200 Input signal 201 Reference comparison clock 301 Comparison clock 401 Output Signal 501 Sampling clock with offset 502 Pseudo-synchronous latch signal 601 Phase comparison signal 701 Control voltage 801 Digital phase comparison signal 901 Phase comparison voltage 1001 Digital phase comparison information 1101 Divide signal 1201 Reference signal divider circuit 12 The output signal 1202 phase information 1301 deadband control signal 1401 reference signal 1501 phase difference detection signal 1601 sampling clock 1602 latch signal

Claims (4)

(57) [Claims] 1. A clock phase locked loop circuit for receiving an input signal and generating a clock phase-locked by a digital phase locked loop (PLL), wherein a result of a phase comparison between the input signal and the PLL output is calculated.
The sampling clock frequency fs' and the phase comparison frequency are f
r, and the frequency deviation of the input signal is α, Nfr (1 + α) <fs ′ <(N + 1) fr (1−α) or (N−1) fr (1 + α) <fs ′ <Nfr (1−α) ( (N is an integer of 2 or more) . 2. The clock phase synchronization circuit according to claim 1, wherein said clock phase synchronization circuit has a latch signal which is pseudo-synchronized with an output of said phase comparison. 3. A frequency dividing means for dividing an input signal into a comparison signal to generate a reference comparison clock, and inputting the reference comparison clock and a comparison clock obtained by dividing an output signal, and detecting a phase difference between them. Phase difference detection means, phase difference detection signal oscillation means for outputting a phase difference detection signal with offset as a reference for phase difference detection , and sampling based on the output of the phase difference detection signal with offset and the phase comparison means. Clock frequency fs',
Let fr be the phase comparison frequency and α be the frequency deviation of the input signal.
Then, an offset of Nfr (1 + α) <fs ′ <(N + 1) fr (1-α) or (N−1) fr (1 + α) <fs ′ <Nfr (1-α) (N is an integer of 2 or more) Pseudo-synchronous control signal generating means for outputting a sampling clock and a pseudo-synchronous latch signal; phase difference sampling means for inputting and sampling the output of the phase comparing means with the offset sampling clock; output of the phase difference sampling means Phase information latching means for latching an output of the pseudo-synchronous latch signal, a D / A conversion means for converting the output of the phase control information latching means into an analog value, and a loop of the output of the D / A conversion means. A clock phase synchronizing circuit, comprising: an oscillating means for inputting via a filter and generating the output signal. Frequency deviation of claim 4 wherein said input signal is according to claim 1 or 3, characterized in that is predetermined based on the maximum value of the reference clock frequency deviation of the frequency measurement or input signal of the input signal clock phase Synchronous circuit.