JP2005244648A - Digital pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital PLL circuit capable of precisely generating synchronous frame signal for stable PLL operation that synchronizes with the inputted reference frame signal with no increase in scale of the circuit. <P>SOLUTION: The digital PLL circuit comprises a phase comparator 1 which compares the phase of the reference frame signal with that of the synchronous frame signal for outputting phase error signal, a digital filter 2 for filtering the phase error signal, an error signal conversion part 3 which divides the phase error signal that has been filtered with a sample number to output integer part and fraction of the error signal, a reference sampling cycle generator 4 for generating a reference sampling cycle, an adder 7 which adds the integer of the error signal to the reference sampling cycle for generating a sampling cycle, a sampling clock generator 5 which modulates the sampling cycle based on the fraction of the error signal, and a synchronous frame signal generator 6 which counts the modulated sampling clock with sample number for generating a synchronous frame signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital PLL circuit (phase-locked loop), and more particularly to a digital PLL circuit for generating a synchronized frame signal synchronized with a reference frame signal.

  In recent years, opportunities for transmitting and receiving video signals and audio signals between AV devices are increasing, and a PLL circuit is used to synchronize signals transmitted and received between AV devices. The PLL circuit is a circuit that generates a signal synchronized with an external input signal (reference signal).

  As shown in FIG. 12, the basic configuration of the PLL circuit includes a phase comparator 91, a loop filter 92 including an integrating circuit and a low-pass filter, and a voltage controlled oscillator (VCO) 93. In the PLL circuit, first, the phase comparator 91 compares the phases of the reference signal from the outside and the synchronization signal oscillated by the VCO 93 and outputs the phase difference component to the loop filter 92 as a pulsed phase difference signal. A high frequency component is removed from the phase difference signal by the loop filter 92 and the phase difference signal is input to the VCO 93. The VCO 93 adjusts the oscillation frequency of the synchronization signal based on the phase difference signal. As described above, the PLL circuit generates and outputs a synchronization signal synchronized with the phase and frequency of the reference signal. Note that matching the phase and frequency of the synchronization signal to the phase and frequency of the reference signal is called PLL lock.

  Some PLL circuits have frequency dividing means. The frequency dividing means divides the frequency of the synchronizing signal output from the VCO by 1 / N. As a result, the phase comparator compares the phase difference between the reference signal and the frequency-divided signal, and the PLL circuit can output a synchronization signal synchronized with a frequency obtained by multiplying the frequency of the reference signal.

Conventionally, an improved PLL circuit based on the basic configuration of the PLL circuit as described above has been proposed.
First, a conventional PLL circuit shown in FIG. 13 will be described (see Patent Document 1). The PLL circuit illustrated in FIG. 13 is a PLL circuit obtained by digitizing the PLL circuit illustrated in FIG. The digital PLL circuit includes a digital phase difference detection unit 101 that detects digital phase information of an input reference signal, and a digital voltage variable oscillator (digital) that varies the phase of an output signal synchronized with the reference signal based on the digital phase information. VCO) 102 and a digital low-pass filter 103 that performs a PLL logic operation.

  In this digital PLL circuit, the digital phase difference detection unit 101 divides one period of the reference signal by the system clock, and the number of system clocks included in the one period is changed from the second decimal place to the third decimal place. The counted integer part and decimal part are compared with the reference clock number of the system clock included in the input signal in advance. Then, the phase comparison results are added and output to the digital low-pass filter 103 as digital phase difference information. This digital phase difference information is fed back to the digital VCO 102 via the digital low-pass filter 103. As a result, it is possible to perform digital PLL processing on a reference signal input from the outside with clock accuracy equal to or lower than the system clock.

  Further, in the PLL circuit shown in FIG. 12, since it is necessary to synchronize not only the phase but also the frequency with the phase comparator 91, a means for detecting the frequency is also required. Therefore, as shown in FIG. 14, there has been proposed a PLL circuit capable of synchronizing the phase and the frequency only by the phase comparator without providing the frequency detecting means (see Patent Document 2). The digital PLL circuit shown in FIG. 14 divides the reference clock (FCK) input from the outside by M and outputs a REF signal based on the sampling frequency information (Fs), and a master clock (MCK). ) Is divided by N (N is a variable power of 2) and outputs a divided signal (VAR signal), and a phase comparator 112 that compares the phases of the VAR signal and the REF signal. A first synchronization detecting means 113 for detecting that the phase comparison result is in a predetermined range, and a second synchronization detecting means 114 for detecting that the phase comparison result is in the predetermined range twice in succession, Is provided. Then, based on the phase comparison result, the N frequency dividing unit 111 sets the frequency division ratio of the master clock to 2N or N / 2 to reduce the phase difference. Thus, by changing the frequency division ratio of the master clock from N / 2 times to 2 times according to the phase difference signal, the phase and frequency can be synchronized only by the phase comparator without the frequency detection means. A possible PLL circuit can be realized.

  In the PLL circuit shown in FIG. 12, the filter is composed of a large integration element. When the input of the reference signal is interrupted, the integration element is saturated, and when the reference signal is input again, the PLL lock state is established. There was a problem that it took time to complete. Therefore, a reference signal input detection circuit that monitors the input of the reference signal is provided to monitor the input of the reference signal, and when the input of the reference signal is interrupted, the information stored in the integral element in the filter is briefly initialized. A PLL circuit has been proposed (Patent Document 3). According to the PLL circuit described in Patent Document 3, even if the input of the reference signal is interrupted, a synchronization signal equivalent to the PLL lock state can be obtained, and the synchronization signal is synchronized with the reference signal after the input of the reference signal is restored. It is possible to shorten the time until the start, that is, the pull-in time to the PLL lock state.

In the PLL circuit shown in FIG. 12, when the reset operation is performed, it takes a long time until the PLL is locked after the reset is released and the reference signal is input. Had. Therefore, there has been proposed a PLL circuit that generates a mask signal for the synchronization signal first input to the phase comparator after reset cancellation and aligns the reference signal and synchronization signal input to the phase comparator after reset cancellation. (Patent Document 4). According to the PLL circuit described in Patent Document 4, it is possible to shorten the time until the synchronization signal is synchronized with the reference signal after the reset is released, that is, the pull-in time to the PLL lock state.
Japanese Patent Laid-Open No. 6-197014 (pages 3 to 6, FIGS. 1 and 2) JP-A-7-22943 (pages 3 to 5, FIGS. 1 and 4) JP-A-2-14618 (pages 4 to 5, FIG. 1) JP-A-6-232858 (pages 2 to 3, FIG. 1)

The conventional PLL circuits described in Patent Documents 1 to 4 have the following problems.
First, in the PLL circuit described in Patent Document 1, one period of the reference signal is divided by the system clock, and the number of system clocks included in the one period is counted from the second decimal place to the third decimal place. Then, the counted integer part and decimal part are compared with the reference clock number of the system clock included in the reference signal in advance. For this reason, it is necessary to detect the decimal part of the phase difference signal and to perform numerical arithmetic processing on the integer part and the decimal part of the phase difference signal to vary the oscillation output of the digital VCO. For this reason, the digital phase difference detection unit 101 and the digital VCO 102 require a plurality of adders and registers. As a result, there arises a problem that the circuit scale of the entire PLL circuit is increased.

Further, in the PLL circuit described in Patent Document 2, since it is necessary for the N dividing means to control the dividing ratio of the master clock to 2N or N / 2 according to the phase comparison result, the circuit configuration of the N dividing means As a result, there is a problem that the circuit scale of the entire PLL circuit is increased.
Further, in the PLL circuit described in Patent Document 3, when the input of the reference signal is interrupted, it is necessary to initialize the information stored in the integral element in the filter. For this reason, when the cycle of the reference signal is changed and the integral element of the filter has a constant bias value in the PLL locked state, there is a problem that it takes time until the integral element reaches the constant bias value from the initial state. occured.

  Further, in the PLL circuit described in Patent Document 4, a mask signal that masks the synchronization signal input to the phase comparator first after reset release is generated, so that the phase is adjusted by determining whether or not the reference signal is input. There has been a problem that it cannot be applied to a PLL circuit.

  Therefore, the present invention solves the problems of the above-described conventional PLL circuit, and can generate a synchronization signal synchronized with the input reference signal with high accuracy and execute a stable PLL operation without increasing the circuit scale. An object is to provide a digital PLL circuit.

  It is another object of the present invention to shorten the time until the synchronization signal is synchronized with the reference signal and enters the PLL locked state when the reference signal is interrupted and input again.

  It is another object of the present invention to shorten the time from when the reference signal is input after the reset is released until the synchronization signal is synchronized with the reference signal to enter the PLL locked state.

  In order to solve the above problems, a digital PLL circuit according to claim 1 of the present invention generates a sampling clock synchronized with a reference frame signal, and generates a synchronized frame signal synchronized with the reference frame signal based on the sampling clock. A phase comparator that detects a phase difference by comparing phases of the reference frame signal and the synchronization frame signal and outputs a phase error signal; a digital filter that filters the phase error signal; The phase error signal filtered by the digital filter and the number of samples information in one frame included in the reference frame signal are input, the phase error signal is divided by the number of samples in one frame, and the phase error signal is Error signal conversion unit that outputs an integer part and a fraction part, and a predetermined number of system clocks A reference sampling period generator for generating a reference sampling period, an adder for adding the integer part of the phase error signal and the reference sampling period to generate a sampling period of the sampling clock, and a phase error signal A sampling clock generation unit that generates a sampling clock by modulating the sampling period based on the value of the fraction part, and a synchronization frame signal generation unit that generates a synchronization frame signal by counting the sampling clock by the number of samples. It is characterized by providing.

  A digital PLL circuit according to a second aspect of the present invention is the digital PLL circuit according to the first aspect, further comprising a sampling period limiting unit that limits the sampling period, wherein the reference sampling period generation unit Input mode information for determining the sampling period, generate a reference sampling period consisting of a predetermined number of system clocks according to the mode, and the sampling period limiting unit inputs the mode information and the reference sampling period, The upper limit value and the lower limit value of the sampling period are determined according to the limit value, the sampling period is limited by the upper limit value and the lower limit value to generate a limited sampling period, and the sampling clock generation unit performs sampling from the limited sampling period. A clock is generated.

  A digital PLL circuit according to a third aspect of the present invention is the digital PLL circuit according to the second aspect, wherein a reference frame input determining unit that determines whether or not the reference frame signal is input and generates reference frame input information. A selector that selects one of the synchronization frame signal and the reference frame signal based on the reference frame input information and outputs the selected frame signal as a selection frame signal; and a limited sampling period from the limited sampling period generator And a sampling period holding register for holding the input, and the phase comparator generates a phase error signal indicating a phase difference between the selected frame signal and the synchronization frame signal, and the sampling period limiting unit includes: Based on the reference frame input information, the sampling period is set as a limited sampling period. Wherein the selecting and outputting one of the sampling period held in the holding register and the sampling period from the adder.

  A digital PLL circuit according to a fourth aspect of the present invention is the digital PLL circuit according to the second aspect, further comprising a reference frame input determining unit that determines input of the reference frame signal and generates reference frame input information. And the sampling period limiting unit selects one of a sampling period from the adder and a reference sampling period from the reference sampling period generation unit as a limiting sampling period based on the reference frame input information The synchronization frame signal generation unit generates a synchronization frame signal using either the number of samples or a preset number of reference samples based on the reference frame input information. Features.

  The digital PLL circuit according to claim 1 of the present invention generates a sampling clock synchronized with a reference frame signal, and generates a synchronized frame signal synchronized with the reference frame signal based on the sampling clock, A phase comparator that outputs a phase error signal by detecting a phase difference by comparing a phase of a frame signal and the synchronization frame signal, a digital filter that filters the phase error signal, and a phase that is filtered by the digital filter An error signal and sample number information in one frame included in the reference frame signal are input, the phase error signal is divided by the number of samples in one frame, and the phase error signal is divided into an integer part and a fraction part. Output error signal converter and reference sampling frequency consisting of a predetermined number of system clocks A reference sampling period generation unit that generates the sampling error, an adder that adds the integer part of the phase error signal and the reference sampling period to generate a sampling period of the sampling clock, and a fractional part value of the phase error signal Based on this, a sampling clock generation unit that modulates the sampling period to generate a sampling clock and a synchronization frame signal generation unit that generates a synchronization frame signal by counting the sampling clock by the number of samples are provided.

  Thereby, by modulating the pulse width of the sampling period signal generated according to the value of the decimal part of the error signal, the precision of the period of the generated synchronization frame can be increased, and the PLL operation can be stabilized.

  A digital PLL circuit according to a second aspect of the present invention is the digital PLL circuit according to the first aspect, further comprising a sampling period limiting unit that limits the sampling period, wherein the reference sampling period generation unit Input mode information for determining the sampling period, generate a reference sampling period consisting of a predetermined number of system clocks according to the mode, and the sampling period limiting unit inputs the mode information and the reference sampling period, The upper limit value and the lower limit value of the sampling period are determined according to the limit value, the sampling period is limited by the upper limit value and the lower limit value to generate a limited sampling period, and the sampling clock generation unit performs sampling from the limited sampling period. A clock was generated.

  As a result, the sampling cycle of the sampling clock can be limited for each mode, and the frequency of the sampling clock can be limited to 1/2 to 2 times the reference frequency in each mode. As a result, it is possible to configure a digital PLL circuit with a small circuit scale by eliminating the frequency circulator circuit.

  A digital PLL circuit according to a third aspect of the present invention is the digital PLL circuit according to the second aspect, wherein a reference frame input determining unit that determines whether or not the reference frame signal is input and generates reference frame input information. A selector that selects one of the synchronization frame signal and the reference frame signal based on the reference frame input information and outputs the selected frame signal as a selection frame signal; and a limited sampling period from the limited sampling period generator And a sampling period holding register for holding the input, and the phase comparator generates a phase error signal indicating a phase difference between the selected frame signal and the synchronization frame signal, and the sampling period limiting unit includes: Based on the reference frame input information, the sampling period is set as a limited sampling period. Select one of the sampling period held in the holding register and the sampling period from the adder and to output.

  As a result, when the input of the reference frame signal is lost, a sampling clock is generated at the sampling period in the PLL lock state immediately before the input of the reference frame signal is lost, and the synchronization frame signal is sent to the phase comparator instead of the reference frame signal. By inputting, the phase error signal output from the phase comparator becomes 0, so that the value of the integrator in the digital filter can be maintained in the same state as in the PLL lock state. As a result, when the reference frame signal is input again, the time until the PLL is locked can be shortened.

  A digital PLL circuit according to a fourth aspect of the present invention is the digital PLL circuit according to the second aspect, further comprising a reference frame input determining unit that determines input of the reference frame signal and generates reference frame input information. And the sampling period limiting unit selects one of a sampling period from the adder and a reference sampling period from the reference sampling period generation unit as a limiting sampling period based on the reference frame input information The synchronization frame signal generation unit generates a synchronization frame signal using either the number of samples or a preset reference sample number based on the reference frame input information. did.

  As a result, the phase of the synchronization frame signal can be matched with the reference frame signal that is input first after the reset is released, so that the time until the PLL is locked can be shortened.

The best mode for carrying out the present invention will be described below with reference to the drawings.
(Embodiment 1)
The digital PLL circuit according to Embodiment 1 of the present invention is a circuit that receives a reference frame signal and generates a synchronization frame signal synchronized with the reference frame signal, and synchronizes the synchronization frame signal with the reference frame signal at a frame level. Generating a sampling clock for the purpose.

  FIG. 1 is a configuration diagram of a digital PLL circuit according to the first embodiment. As shown in FIG. 1, the digital PLL circuit includes a phase comparator 1, a digital filter 2, an error signal conversion unit 3, a reference sampling period generation unit 4, a sampling clock generation unit 5, and a synchronization frame signal 6. And an adder 7. The phase comparator 1 performs phase comparison between a reference frame signal input from the outside and a synchronization frame signal generated in the digital PLL circuit, and outputs a phase error signal indicating a phase difference. The digital filter 2 filters the phase error signal to remove unnecessary components. The error signal conversion unit 3 inputs the phase error signal filtered by the digital filter 2 and the sample number information in the frame included in the reference frame signal, divides the phase error signal by the number of samples (the number of sampling data), The phase error for each sampling clock is calculated. Then, the calculated phase error is divided into an integer part and a decimal part and output as an error signal integer part and an error signal decimal part. The error signal integer part is represented by the number of system clocks. The reference sampling cycle generation unit 4 generates a reference sampling cycle in which a preset reference sampling cycle is represented by a system clock count. The adder 7 adds the error signal integer part and the reference sampling period. This addition result is the number of system clocks indicating the sampling period, that is, the period of the sampling clock. The sampling clock generation unit 5 generates a sampling clock based on the sampling period. The synchronization frame signal generation unit 6 receives sample information included in the reference frame signal, and generates a synchronization frame signal by counting the sampling clock by the number of samples.

  The operation of the digital PLL circuit configured as described above will be described. First, the operation when the error signal decimal part output from the error signal conversion unit 3 is 0 will be described with reference to FIG.

  First, the phase comparator 1 inputs the reference frame signal and the synchronization frame signal from the synchronization frame signal generation unit 6, and generates a phase error signal. Unnecessary components are removed from the phase error signal by the digital filter 2 and input to the error signal converter 3.

  Next, the error signal converter 3 divides the phase error signal filtered by the digital filter 2 by the number of samples, and calculates a phase error for each sampling clock. At this time, since the calculated phase error is only the integer part, only the error signal integer part is output.

  Next, the adder 7 adds the system clock number indicating the reference sampling period and the system clock number indicating the error signal integer part to generate a sampling period. That is, as shown in FIG. 2, the sampling period is generated by adding the system clock number of the error signal integer part to the system clock number of the reference sampling period. That is, the error signal integer part is added to the sampling period from the rising edge of the sampling clock to the next rising edge. When the error signal integer part is an even number, the high part and the low part of the sampling clock have the same length, so as shown in FIG. 2, 1/2 of the error signal integer part is added to the high part and the low part. The However, when the error signal integer part is an odd number, the length added by the High part and the Low part is different by 1 clock because it cannot be divided. The sampling cycle generated in this way is input to the sampling clock generator 5. The sampling clock generator 5 generates a sampling clock having the sampling period.

  The generated sampling clock is input to the synchronization frame signal generation unit 6. The synchronization frame signal generation unit 6 generates a synchronization frame signal by counting the sampling clocks for the number of samples based on the sample number information indicating the number of samples in one frame.

  Next, an operation when the error signal decimal part output from the error signal conversion unit 3 is not 0 will be described with reference to FIGS. 1 and 3. FIG. 3 is a diagram showing a detailed configuration of the digital filter 2 and the error signal converter 3.

  As shown in FIG. 3, the digital filter 2 includes a bit extension unit 8, multipliers 9 and 10, adders 11 and 12, and an integrator 13. The Kbit phase error signal input from the phase comparator 1 is expanded by the bit expansion unit 8 and the fractional part corresponding to Lbit is expanded, and then filtered by the multipliers 9 and 10, the adders 11 and 12, and the integrator 13. Calculated. The K + Lbit phase error signal filtered by the digital filter 2 is input to the error signal converter 3. The error signal converter 3 divides the K + Lbit phase error signal by the number of samples in the frame. The divided phase error signal is divided into an integer part and a decimal part and output. The error signal integer part is added to the reference sampling period as described above, and is input to the sampling clock generation part 5. On the other hand, the error signal decimal part is input to the sampling clock generator 5.

  The sampling clock generation unit 5 modulates the sampling period according to the value of the error signal decimal part and generates a sampling clock. Hereinafter, the modulation operation of the sampling period will be described in detail with reference to FIGS. FIG. 4 is a diagram showing the configuration of the sampling clock generation unit 5. FIGS. 5 and 6 are timings when the sampling period is modulated using the first decimal place and the second decimal place of the error signal decimal part. FIG.

  As illustrated in FIG. 4, the sampling clock generation unit 5 includes a sampling period addition unit 41, a counter 42, a sampling period counter 43, and a sampling clock generation unit 44. The sampling period adding unit 41 inputs the sampling period (FS) from the adder 7, the error signal decimal part, and the count value from the counter 42. Since the counter 42 counts at the rising edge of the sampling clock and repeatedly counts values from 0 to 3, the sampling period adding unit 41 inputs any value from 0 to 3 from the counter 42. The sampling period adding unit 41 inputs the sampling period (FS), the error signal decimal part, and the count result of the counter 42, and uses the sampling period as it is from the error signal decimal part and the counter result, or uses the system clock as the sampling period. Is added for one clock, and an additional sampling period is output. The sampling period counter 43 performs a counting operation for the additional sampling period output from the sampling period adding unit 41. The sampling clock generation unit 44 generates a sampling clock based on the count result of the sampling period counter 43.

  Hereinafter, the additional sampling period when the first decimal place and the second decimal place of the error signal decimal part are used will be described with reference to FIGS. First, when the first decimal place = 0 and the second decimal place = 0, the additional sampling period is output without being modulated. On the other hand, when the first decimal place = 0 and the second decimal place = 1, as shown in FIG. 5, the count result of the counter 42 is a value of 3 and the sampling clock period is one clock of the system clock. become longer.

  Further, as shown in FIG. 6, when the first decimal place is 1 and the second decimal place is 0, when the count result of the counter 42 is 1 and 3, the sampling period is increased by one clock with the system clock, In the case of the first place = 1 and the decimal second place = 1, when the count result of the counter 42 is 1, 2 and 3, the sampling period becomes longer by one system clock. In other words, the modulation period when using up to the Nth decimal bit is 2 to the Nth power, and the larger the value of the decimal part, the higher the proportion of the system clock added to the sampling period.

  By counting the sampling clock generated as described above for the number of samples in one frame, the synchronization frame signal generation unit 6 generates a synchronization frame signal synchronized with the reference frame signal.

  As described above, according to the digital PLL circuit according to the first embodiment, the phase error signal between the reference frame signal and the synchronization frame signal is divided by the number of samples of the reference frame, and the fraction of the phase error signal obtained by the division is obtained. Since the sampling clock is modulated according to the value of the part and the synchronization frame signal is generated by the modulated sampling clock, the synchronization frame signal can be synchronized with the reference frame signal at the frame level.

  Further, since the digital PLL circuit according to the first embodiment obtains the error signal fraction part by expanding the phase error signal, the phase error signal is not provided with a circuit for detecting the fraction part of the phase error signal. The sampling clock can be modulated in accordance with the value of the decimal part. As a result, a synchronized frame signal synchronized with the reference frame signal can be generated with high accuracy using the decimal part of the phase error signal without increasing the circuit scale.

(Embodiment 2)
Hereinafter, a digital PLL circuit according to Embodiment 2 of the present invention will be described with reference to FIG. In FIG. 7, the same or corresponding components as those in the digital PLL circuit shown in FIG.

  In the digital PLL circuit according to the first embodiment, since the phase comparator 1 compares not only the phase but also the frequency, it is necessary to provide a frequency pull-in circuit in the phase comparator 1.

  Therefore, the digital PLL circuit according to the second embodiment is characterized in that the phase and frequency are synchronized without having a frequency pull-in circuit by newly including a sampling period limiting unit 14 as shown in FIG. And The sampling period limiting unit 14 determines an upper limit value and a lower limit value of the sampling period based on the mode information, and generates a limited sampling period in which the sampling period is limited.

  Further, the reference sampling period generation unit 4 receives mode information for determining the sampling period, counts a reference sampling period set in advance according to the mode with the system clock, and outputs the number of clocks. For example, if the digital PLL circuit inputs a video frame signal and applies a PLL to synchronize video (video) and audio (sound), the mode information is information indicating an audio sampling frequency. become.

  The operation of the digital PLL circuit according to the second embodiment configured as described above will be described. In the digital PLL circuit according to the second embodiment, the reference sampling period generation unit 4 outputs a reference sampling period set in advance for each mode based on the mode information. The adder 7 adds the reference sampling period changing for each mode and the error signal integer part from the error signal converter 3 and outputs the addition result to the sampling period limiter 14 as a sampling period. The sampling period limiting unit 14 inputs mode information and limits the sampling period by an upper limit value and a lower limit value determined based on the mode information. FIG. 8 is a graph showing the limited sampling period with respect to the phase error. The sampling period limiter 14 limits the upper limit of the sampling period to less than twice and the lower limit of the sampling period to 1/2 or more with respect to the reference sampling period that changes for each mode. That is, the sampling period is limited to ½ to 2 times the reference sampling period. Then, the sampling clock generation unit 5 generates a sampling clock based on the limited sampling period. The synchronization frame generator 6 generates a synchronization frame signal using the sampling clock generated as described above.

  As described above, the digital PLL circuit according to the second embodiment includes the sampling period limiting unit 14 and limits the sampling period to ½ to 2 times the reference sampling period, thereby achieving a target PLL lock. It is possible to prevent the PLL from being locked when the frequency is twice or more or 1/2 or less. As a result, it is possible to configure a digital PLL circuit with a small circuit scale without providing a frequency peripheral pull-in circuit.

(Embodiment 3)
Hereinafter, a digital PLL circuit according to Embodiment 3 of the present invention will be described with reference to FIG.
FIG. 9 is a block diagram showing a configuration of a digital PLL circuit according to the third embodiment. The digital PLL circuit according to the third embodiment shown in FIG. 9 is different from the digital PLL circuit according to the second embodiment shown in FIG. 7 in that a selector 17, a sampling period holding register 15, and a reference frame input determination unit 16 are newly added. Prepare for. The reference frame input determination unit 16 determines whether or not a reference frame signal is input, and generates reference frame input information. The selector 17 selects either the synchronization frame signal or the reference frame signal based on the reference frame input information, and outputs the selected frame signal. The sampling period holding register 15 receives and holds the sampling period for each frame from the sampling period limiting unit 14.

  In addition, the sampling period limiting unit 14 selects which of the value held in the sampling period holding register and the value of the sampling period from the adder 7 is used as the sampling period based on the reference frame input information. To do.

  The operation of the digital PLL circuit according to the third embodiment configured as described above will be described. First, a case where the reference frame signal is continuously input will be described. When the reference frame signal continues to be input, the selector 17 selects the reference frame signal based on the reference frame input information generated by the reference frame input determination unit 16 and outputs it to the phase comparator 1. The sampling period holding register 15 holds a sampling period for each frame in the PLL locked state. Since other operations are the same as those of the second embodiment, description thereof is omitted.

  Next, the operation when the input of the reference frame signal is interrupted will be described. When the reference frame signal is no longer input, the sampling period limiter 14 outputs the sampling period in the PLL lock state, which is held in the sampling period holding register 15 and immediately before the input of the reference frame signal is stopped, as the limited sampling period. The selector 17 selects a synchronization frame signal and outputs it as a selection frame signal. As a result, the selection frame signal and the synchronization frame signal input to the phase comparator 1 become the same synchronization frame signal, so that the phase error output by the phase comparator 1 becomes zero.

  As described above, the digital PLL circuit according to the third embodiment generates a sampling clock at the sampling period in the PLL lock state immediately before the input of the reference frame signal when the input of the reference frame signal is lost, Since the synchronization frame signal is input to the phase comparator 1 instead of the reference frame signal and the phase error signal output from the phase comparator 1 is set to 0, the value of the integrator of the digital filter 2 is set to the PLL locked state. It can be kept in the same state as time. As a result, when the reference frame signal is input again, the time until the PLL is locked can be shortened.

(Embodiment 4)
Hereinafter, a digital PLL circuit according to Embodiment 4 of the present invention will be described with reference to FIG.
FIG. 10 is a block diagram illustrating a configuration example of a digital PLL circuit according to the fourth embodiment. The digital PLL circuit according to the first embodiment illustrated in FIG. 10 newly includes a reference frame input determination unit 16 in addition to the digital PLL circuit according to the second embodiment illustrated in FIG. The reference frame input determination unit 16 receives a reset signal that becomes High when the PLL circuit is reset and then reset is released. When the reset signal becomes High, the reference frame input determination unit 16 determines the input of the first reference frame signal after the reset is released, and generates reference frame input information.

  Based on this reference frame input information, the sampling period limiter 14 selects and outputs either the reference sampling period from the reference sampling period generator 4 or the sampling period from the adder 7 as the limited sampling period.

  The operation of the digital PLL circuit according to the fourth embodiment configured as described above will be described. Since the operation when the reference frame signal is input is the same as that of the digital PLL circuit according to the second embodiment, the description thereof is omitted.

Hereinafter, the operation when the digital PLL circuit is reset and then the reset is released will be described.
The reference frame input determination unit 16 generates reference frame input information when detecting the input of the first reference frame signal after reset is released. The reference frame input information is input to the sampling period limiting unit 14. When the reference frame input information is input, the sampling period restriction unit 14 selects and outputs the reference sampling period from the reference sampling period generation unit 4 as the restriction sampling period.

  The sampling clock generation unit 5 generates a sampling clock at a reference sampling period.

  The reference frame input information is also input to the synchronization frame signal generation unit 6. When receiving the reference frame input information, the synchronization frame signal generation unit 6 counts the sampling clock by a preset number of reference samples to generate a synchronization frame signal. By the operation as described above, as shown in FIG. 11, a synchronized frame signal synchronized with the reference frame signal that is input first after reset is released can be generated.

  As described above, the digital PLL circuit according to the fourth embodiment adjusts the phase of the synchronization frame signal to the reference frame signal that is input first after the reset is released when the reset is applied and then the reset is released. Therefore, it is possible to shorten the time until the PLL is locked.

  The present invention is useful as a digital PLL for synchronizing signals transmitted and received between AV devices when transmitting and receiving video signals and audio signals between AV devices.

1 is a block diagram illustrating a configuration of a digital PLL circuit according to a first embodiment of the present invention. It is a timing diagram of the sampling clock which the digital PLL circuit concerning Embodiment 1 of the present invention generates. It is a block diagram which shows the internal structure of the digital filter part and error signal conversion part of the digital PLL circuit which concern on Embodiment 1 of this invention. It is a block diagram which shows the internal structure of the sampling clock generation part of the digital PLL circuit which concerns on Embodiment 1 of this invention. It is a timing diagram of the sampling clock which the digital PLL circuit concerning Embodiment 1 of the present invention generates. It is a timing diagram of the sampling clock which the digital PLL circuit concerning Embodiment 1 of the present invention generates. It is a block diagram which shows the structure of the digital PLL circuit which concerns on Embodiment 2 of this invention. It is a graph which shows the relationship between the limiting sampling period which the digital PLL circuit which concerns on Embodiment 2 of this invention produces | generates, and a phase error. It is a block diagram which shows the structure of the digital PLL circuit which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the digital PLL circuit which concerns on Embodiment 4 of this invention. It is a timing diagram of the synchronous frame signal which the digital PLL circuit which concerns on Embodiment 4 of this invention produces | generates. It is a block diagram which shows the structure of the conventional PLL circuit. It is a block diagram which shows the structure of the conventional digital PLL circuit. It is a block diagram which shows the structure of the conventional digital PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Digital filter 3 Error signal conversion part 4 Reference sampling period generation part 5 Sampling clock generation part 6 Synchronization frame signal generation part 7 Adder 8 Bit expansion part 9, 10 Multiplier 11, 12 Adder 13 Integrator 13 Integrator 14 Sampling period limiting unit 15 Sampling period holding register 16 Reference frame input determining unit 17 Selector 41 Sampling period adding unit 42 Counter 43 Sampling period counter 44 Sampling clock generating unit 91 Phase comparator 92 Loop filter 93 VCO
101 Digital phase detector 102 Digital VCO
103 Digital low-pass filter 110 M frequency dividing means 111 N frequency dividing means 112 Phase comparator 113 First synchronization detection means 114 Second synchronization detection means

Claims (4)

In a digital PLL circuit that generates a sampling clock synchronized with a reference frame signal and generates a synchronized frame signal synchronized with the reference frame signal based on the sampling clock,
A phase comparator that detects a phase difference by comparing phases of the reference frame signal and the synchronization frame signal, and outputs a phase error signal;
A digital filter for filtering the phase error signal;
The phase error signal filtered by the digital filter and the number of samples information in one frame included in the reference frame signal are input, the phase error signal is divided by the number of samples in one frame, and the phase error signal is An error signal converter that outputs an integer part and a fraction part; and
A reference sampling period generator for generating a reference sampling period composed of a predetermined number of system clocks;
An adder that adds the integer part of the phase error signal and the reference sampling period to generate a sampling period of the sampling clock;
A sampling clock generator that modulates the sampling period to generate a sampling clock based on the value of the fractional part of the phase error signal;
A digital PLL circuit comprising a synchronization frame signal generation unit that generates a synchronization frame signal by counting the sampling clock by the number of samples. The digital PLL circuit according to claim 1,
A sampling period limiter that limits the sampling period;
The reference sampling period generation unit inputs mode information for determining the sampling period, generates a reference sampling period composed of a predetermined number of system clocks according to the mode,
The sampling cycle limiter inputs the mode information and the reference sampling cycle, determines an upper limit value and a lower limit value of the sampling cycle according to a mode, and limits the sampling cycle by the upper limit value and the lower limit value. To generate a limited sampling period,
The digital PLL circuit, wherein the sampling clock generation unit generates a sampling clock from the limited sampling period. The digital PLL circuit according to claim 2,
A reference frame input determination unit that determines whether or not the reference frame signal is input and generates reference frame input information;
A selector that selects one of the synchronization frame signal and the reference frame signal based on the reference frame input information and outputs the selected frame signal as a selection frame signal;
A sampling period holding register that receives and holds a limited sampling period from the limited sampling period generation unit;
The phase comparator generates a phase error signal indicating a phase difference between the selection frame signal and the synchronization frame signal;
The sampling period limiting unit selects either a sampling period held in the sampling period holding register as a limiting sampling period or a sampling period from the adder based on the reference frame input information A digital PLL circuit characterized by outputting. The digital PLL circuit according to claim 2,
A reference frame input determining unit that determines input of the reference frame signal and generates reference frame input information;
The sampling period limiting unit selects and outputs either a sampling period from the adder or a reference sampling period from the reference sampling period generation unit as a limiting sampling period based on the reference frame input information And
The synchronization frame signal generation unit generates a synchronization frame signal using either the number of samples or a preset number of reference samples based on the reference frame input information. PLL circuit.

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