JP2600668B2 - Clock regeneration circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit used for reproducing digital data.

2. Description of the Related Art A phase synchronizing circuit is used as a clock recovery circuit in the conventional digital data reproduction. A block diagram is shown in FIG. 5 and a timing waveform diagram is shown in FIG. 50
Is a multiplier that multiplies the input digital data to produce a pulse of a certain width, 51 is a voltage controlled oscillator (hereinafter referred to as VCO), 52
Denotes a phase comparator (hereinafter, referred to as PC), and 53 denotes a charge pump including an LPF. In the clock recovery circuit configured as described above, when the input digital data is input to the multiplier 50, a multiplied pulse having a width D that is half the minimum pulse width T of the input data is generated as shown in FIG. create. The multiplied pulse enters the PC52 together with the positive and negative phase outputs of the VCO 51.
Phase comparisons as shown in 5 and 6 are performed, and the ratio of both pulse widths is converted into a voltage value in the charge pump 53, and VC
As a control voltage of O51, a loop was formed.

However, in the above configuration, the phase comparison is performed within the multiplied pulse of the pulse width D created from the input data, and as a result, the synchronization point between the input data and the clock of the negative-phase output Q of the VCO 51 is obtained. However, the clock side is delayed not by π / 2 of the optimum extraction point but by D / 2 therefrom. Therefore, a delay device for externally delaying input data by D / 2 is required to set the synchronization point to π / 2. Therefore, the synchronization point may shift from π / 2 due to the temperature characteristics of the loop or the D / 2 delay device. Therefore, according to the present invention, the phase relationship at the time of synchronization between the input data and the clock in the phase synchronization circuit is always π / 2, that is, the optimum extraction point regardless of the input data rate, and the deviation of the extraction point due to temperature is small. It is another object of the present invention to provide a clock recovery circuit having a simple configuration.

Means for Solving the Problems The present invention provides an edge detector for detecting an edge of input digital data, a voltage-controlled oscillator for generating a clock, and forming a pulse from output signals of the edge detector and the voltage-controlled oscillator. A first flip-flop, a second flip-flop for generating a pulse from the output signal of the first flip-flop and the voltage-controlled oscillator, and a ratio of the output pulse width of the first and second flip-flop to the voltage A charge pump for converting the voltage to a control voltage of the control oscillator, wherein the first flip-flop is set at an edge of the edge detector and is set at a rise or fall of an output signal of the voltage control oscillator. The interval is output as a pulse width, and the second flip-flop is set by the first flip-flop. The first flip-flop is reset at a timing opposite to the reset timing of the first flip-flop by a signal input from the voltage controlled oscillator and set at a timing of resetting after the reset, and outputs a pulse width during the reset. Clock recovery circuit.

According to the present invention, when digital data is input, an edge is detected first, and a pulse is generated by the first flip-flop based on the edge and the output signal of the voltage-controlled oscillator. A pulse is generated by the second flip-flop from the output signal of the voltage-controlled oscillator and the flip-flop. Then, the ratio of the width of the two pulses is converted into a voltage by a charge pump, and the control voltage of the voltage controlled oscillator is input to form a loop. The loop then synchronizes at the point where the widths of the two pulses are equal. Therefore, since the sum of the widths of the two pulses is equal to the minimum pulse width of the input data, and the pulse width of the output of the voltage controlled oscillator is half of the minimum pulse width of the input data, the input data and the output of the voltage controlled oscillator are used. The phase relationship at the time of synchronization with a certain clock is independent of the input data rate in the loop,
It always becomes π / 2, that is, the optimal sampling point.

FIG. 1 is a block diagram showing the overall structure of a first embodiment of the present invention, and FIG. 2 is a timing waveform diagram thereof.

In FIG. 1, reference numeral 10 denotes an edge detector for detecting an edge of input digital data, 11 denotes a voltage controlled oscillator (hereinafter referred to as VCO) for generating a clock, and 12 denotes an edge detector and a VCO.
A first flip-flop (hereinafter referred to as FF (1)) for generating a pulse from the output signal of 11 and a second flip-flop (hereinafter referred to as 13) for generating a pulse from the output signal of FF (1) 12 and VCO11
FF (2)) and 14 are charge pumps that convert the ratio of the width of the pulse output from FF (1) 12 and FF (2) 13 into a voltage for use as a control voltage for the pump of VCO11. The operation of the clock recovery circuit of the present embodiment configured as described above will be described below. First, when input to the digital data edge detector 10, an edge as shown in FIG. 2 (2) is detected. Next, the edge and the output Q of VCO11 are FF
(1) When input to 12, the pulse is set at the rising edge of the edge and set at the rising edge of the output Q of the VCO 11 as shown in FIGS. Subsequently, when the negative-phase output of the fourth pulse and the output Q of the VCO 11 are input to the FF (2) 13, they are set at the rising of the negative-phase output of the FF 2 as shown in 5 and 6 and at the rising of the output Q of the VCO 11. The pulse shown in FIG. 7 is set. Then, the ratio of the pulse widths of 4 and 7 is converted into a voltage by the charge pump 14 and given as a control voltage of the VCO 11, a loop is formed, and synchronization is performed at the point where the pulse widths of 4 and 7 are equal. As described above, according to this embodiment, the sum of the pulse widths of 4 and 7 is equal to the minimum pulse width of the input data, and the output pulse width of the VCO 11 is equal to half of the minimum pulse width of the input data. As shown in (1) and (3), it is possible to set π / 2 of the input data to the optimum extraction point in the loop.

FIG. 3 is a block diagram of a clock recovery circuit showing a second embodiment of the present invention, and FIG. 4 is a timing waveform diagram thereof. In FIG. 3, 10 is an edge detector and 12 is
FF (1) and 13 are FF (2) and 14 are charge pumps, and the above is the same as the configuration of FIG. The difference from the configuration of FIG. 1 is that the VCO 30 is composed of an oscillating unit 31 and a frequency dividing unit 32. The operation of the clock recovery circuit of the second embodiment configured as described above will be described below.

The operation of the edge detector 10, FF (1) 12, FF (2) 13, and charge pump 14 is the same as that in FIG. The difference is that the oscillating unit 31 in the VCO 30 oscillates at a frequency four times the maximum frequency of the input data by the voltage output from the charge pump 14,
The point is that the frequency is divided and applied to FF (1) and FF (2) to form a loop. As described above, according to the present embodiment, the oscillation unit 31 of the VCO 30 oscillates at a frequency four times the highest frequency of the input data, and divides it by で in the frequency dividing unit 32, so that the output of the VCO 30 becomes A waveform with a complete duty of 50% is obtained, and its pulse width is completely half of the minimum pulse width of the input data. As a result, FIGS. 4 (1) and (4)
As shown in the figure, the synchronization point becomes π / 2, which is the optimum extraction point, and the accuracy is further improved as compared with the first embodiment.

Effect of the Invention As described above, according to the present invention, input data and
The phase relationship with the clock, which is the output of the VCO, is always π
/ 2, that is, the optimum extraction point, the deviation of the extraction point due to the temperature can be suppressed only in the loop, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock recovery circuit according to a first embodiment of the present invention, FIG. 2 is a timing waveform diagram of the same embodiment, and FIG. 3 is a block diagram of a clock recovery circuit of a second embodiment of the present invention. FIG. 4 is a timing waveform chart of the embodiment.
FIG. 5 is a block diagram of a conventional clock recovery circuit, and FIG. 6 is a timing waveform diagram of the clock recovery circuit. 10 ... edge detector, 11 ... voltage controlled oscillator, 12 ... first flip-flop, 13 ... second flip-flop, 14 ... charge pump, 30 ... voltage controlled oscillator, 31
…… oscillator, 32… divider, 50… multiplier, 51… VC
O, 52: Phase comparator, 53: Charge pump.

Claims (2)

(57) [Claims] An edge detector for detecting an edge of input digital data; a voltage controlled oscillator for generating a clock; a first flip-flop for generating a pulse from an output signal of the edge detector and the voltage controlled oscillator; A second flip-flop for generating a pulse based on the output signal of the first flip-flop and the voltage controlled oscillator;
A charge pump for converting a ratio of the width of the output pulse of the second flip-flop into a voltage for use as a control voltage of the voltage-controlled oscillator, wherein the first flip-flop is set at the edge and the voltage is The output signal of the control oscillator is set at the rising or falling of the output signal, and a pulse width is output during that time. The second flip-flop is set at a reset timing after the first flip-flop is set, and the voltage-controlled oscillator is set. A clock recovery circuit characterized in that the signal is reset at an edge of a timing opposite to the reset timing of the first flip-flop by a signal input from the first flip-flop, and a pulse width is output during the reset. 2. The maximum frequency of input digital data of 4
Oscillator that generates twice the frequency, and the generated frequency
2. The clock recovery circuit according to claim 1, further comprising a voltage-controlled oscillator having a frequency divider that reduces the frequency by half.