JPS62154877A - Pll circuit - Google Patents

Abstract

PURPOSE:To improve following performance and to prevent mislock by locking a VCO in a PLL circuit at an input burst phase and controlling the oscillation frequency of the VCO based on a phase error between the output of the VCO and an input horizontally synchronizing signal. CONSTITUTION:Monostable multivibrators 2, 3 are trigger type vibrators and the VCO 1 is forcedly locked at an input burst phase by injecting a burst signal obtained from an input video signal through a burst separating circuit 6 and a comparator 6 into the VCO 1 through an OR gate 5. The output of the VCO 1 is multiplied by 4 times e.g. by a multiplier 8 and extracted as a clock fCK. The clock fCK is dropped down to horizontal frequency fH by a frequency divider 9 and then compared with an input horizontally synchronizing signal obtained from a synchronizing separator circuit 10 by a phase comparator 11. The phase error voltage is applied to CR time constant circuits in the vibrators 2, 3 to control the oscillation frequency of the VCO 1. Consequently, the phase is locked at the input burst phase with the frequency following jitter (variance of horizontal phase).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL circuit that generates a clock synchronized with a jittery video signal such as a VTR playback signal.

[Summary of the invention]

Configure a VCO with a retrigger type monomulti, inject an input burst into its trigger input to synchronize the phase, and then
This is a PLL circuit that controls the oscillation frequency of the VCO based on the phase difference between the oscillation output and the input horizontal synchronization signal, and has good sinter followability with respect to the input video and fast pull-in speed.

[Conventional technology]

The time base collector, which corrects time axis fluctuations (jitter) etc. in the output of a VTR, creates a clock synchronized with the input video signal, performs A/D conversion and writes to memory based on this clock, and uses it as a reference. Reading from memory and D/A conversion are performed based on the clock.

4 and 5 show a clock generation circuit using a conventional PLL circuit. In FIG. 1, a horizontal synchronization signal H in an input video signal is separated by a synchronization separation circuit 20, and this horizontal open! The phase comparator 21 compares the tIl signal with a signal obtained by reducing the output of the VCO 22 to the horizontal frequency fo using the frequency divider 23, controls the VCO 22, and selects a clock few (for example, 4 of the subcarrier) that follows the input jitter. double frequency 4
f+c) is obtained.

In FIG. 5, the burst signal is separated from the input video signal by the burst separation circuit 24, and the same as in FIG. 4 (VCO 22
The phase comparator 21 compares the frequency-divided outputs in the burst gate period to control the VCO 22.

[Problem that the invention seeks to solve]

Since the clock generation circuit shown in FIG. 4 performs synchronization at the water cycle, there are problems in that the tracking speed is slow and the output phase changes in response to noise in the horizontal synchronization signal or changes in the slice level. The clock generation circuit shown in FIG. 5 has fewer malfunctions due to noise, but since it uses a burst signal for each IH, the tracking speed is slow, and there is a problem in that it only tracks jitter within one wave of the burst wave1. I
If there is a jitter of just the width (360°) of the burst wave at intervals of H, the phase cannot be discriminated in the phase comparator 21 as a phase misplastering, and the PLL mislocks.

The present invention solves this problem and improves tracking performance (retraction performance).
To provide a PLL circuit which has good performance, does not cause mislock, and can be easily integrated into an IC using an hour wheel.

[Means for solving problems]

As shown in FIG. 1, the PLL circuit of the present invention is equipped with retrigger type mono multi-vibration brakes MM2 and MM3 as oscillation elements, and a vcot which is locked to the phase by injecting a burst of an input video signal into the trigger input.
Equipped with: A phase comparison circuit 11 compares the phase of a pulse obtained by frequency-dividing the output of the VCOI to the horizontal synchronization frequency and a horizontal synchronization signal of the input video signal, and controls the oscillation frequency of the VCOL based on the phase comparison output.

[For production]

CO is injection-locked to the input burst, so it has good phase locking performance (followability) for the input video, and the frequency is controlled to follow the phase error with the horizontal synchronization signal, so burst waves whose phase is difficult to distinguish 360 of
It is possible to obtain a clock with a frequency that follows degrees of deviation (jitter).

〔Example〕

FIG. 1 is a block diagram of a PLL circuit to which the present invention is applied.
The monomulti pipe lakes 2.3 are connected in cascade, and the subsequent stage output is fed back from the OR gate 5 to the preceding stage monomulti 2 via the differentiating circuit 4 to form a VCOI. The monomulti 2.3 is a retrigger type, and by injecting a burst signal obtained from the input video signal through the burst separation circuit 6 and the comparator 7 into the vcoi through the OR gate 5, the vcoi is forcibly locked to the input burst phase. The output (fsc) of the VCOI is multiplied by 4, for example, by a multiplier 8, and taken out as a clock.

This clock is reduced to a horizontal frequency f by a frequency divider 9, and then compared with an input horizontal synchronization signal obtained from a synchronization separation circuit 10 in a phase comparator circuit 11.

The phase error voltage is applied to the monomulti 2.3 CR time constant circuit to control the oscillation frequency of the VCOL. As a result, a clock whose phase is locked to the input burst phase and whose frequency follows jitter (horizontal phase fluctuation) can be obtained.

Since a retrigger type injection oscillator is used for the VCOI in this way, it has good followability to the input phase, and even when the input video is intermittent due to jog search during tape editing, synchronization can be quickly pulled in. Furthermore, since the oscillation frequency is controlled based on the phase error with respect to the input horizontal synchronization, there is an advantage that the problem of misclocking as shown in FIG. 5 does not occur. It is also easy to convert the VCOI into an IC.

Figures 2 and 3 are VCOL operation time charts,
FIG. 2 shows a case where the input burst phase leads the oscillation output, and FIG. 3 shows a case where it lags.

As shown in FIG. 2, when input burst pulse B is input to monomulti 2 as shown in C through OR gate 5,
When the rising trigger is applied, the frequency f, which is synchronized with the input burst as shown in D, is approximately f. (3.58MHz), an output with a duty of 50% can be obtained. This output is mono multi 3
As shown in FIG. 2E, a falling trigger is applied and a pulse output with a frequency f and a duty of 50% is obtained. This pulse E is differentiated as shown by A in the falling differentiation circuit 4, and is re-inputted to the monomulti 2 through the OR gate 5, so that the pulse E is differentiated as shown in FIG. An oscillation output whose injection is locked to the target phase is obtained. The oscillation frequency is adjusted by the horizontal phase error.

When the input burst has a delayed phase as shown in FIG. 3, the front stage monomulti 2 is re-triggered at the rising edge of the input burst immediately after being triggered by the differential output A, as shown in the third diagram. Therefore, the subsequent oscillation phase of VCO1 is locked to the input burst.

〔Effect of the invention〕

As described above, the present invention locks the VCO of the PLL circuit to the input burst phase and controls the VCO oscillation frequency using the phase error between its output and the input horizontal synchronizing signal. This prevents the inconvenience of mislocking due to inability to distinguish a one-way shift.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PLL circuit showing an embodiment of the present invention, FIGS. 2 and 3 are time charts, and FIGS. 4 and 5 are block diagrams of a conventional PLL circuit. In addition, in the symbols used in the drawings, 1・・・・・−・・−・−・・−・−・VCO2, 3・
−・・・・・−・・Mono multi 4・−・・・・・・・−・
−11−−−Differential circuit 5・−・−・・・・−・−−−−
---OR gate 6------------Burst separation circuit 7---------------Comparator 8------------ −・・・・− Multiplier 9・
−・−・・・−・・−Frequency divider 10−−−−−・−・−・−・−・Synchronization separation circuit 11−
・−・−・−・・− Phase comparator circuit.

Claims (1)

[Claims] The VCO is equipped with a retrigger type mono multivibrator as an oscillating element and is locked to the phase of a burst of input video signal by injecting it into the trigger input, and a pulse obtained by dividing the output of the VCO to the horizontal synchronization frequency. A PLL circuit characterized in that the phase of an input video signal is compared with a horizontal synchronizing signal, and the oscillation frequency of the VCO is controlled based on the phase comparison output.