JPS63287216A - Phase locked oscillation circuit - Google Patents

Abstract

PURPOSE:To prevent the phase of an output clock signal from being fluctuated even if missing of pulse exists in an input clock signal by applying self-running to a voltage controlled crystal oscillator succeedingly in the control state just before the occurrence of missing of pulse at the detection of missing of pulse. CONSTITUTION:A missing pulse detection circuit 10 detects missing of pulse in an input clock signal A and a gate signal generating circuit 11 receiving a detection signal E generates a gate signal F after the missing of pulse is finished and a period of a prescribed bit or over in the output clock signal B elapses. A charge pump circuit 12A is kept to a high impedance state to bring the voltage controlled crystal oscillator 16 into the self-running state, and the phase of the output clock signal B obtained by applying frequency- division 17 to the oscillation output for a period where missing of pulse is consecutive is kept to the phase before the missing of pulse takes place. Thus, even if missing of pulse takes place in the input clock signal, the stable output clock signal without phase fluctuation is outputted succeedingly.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an LC
This relates to a phase-locked oscillator circuit that generates a stable output clock signal that is bit-synchronized with an input clock signal extracted by a tuning circuit or the like. [Prior Art] Figure 4 shows a conventional phase-locked oscillator circuit. Diagram,
In the figure, 1 is an input terminal for an input clock signal, 2 is an output terminal for an output clock signal, 3 is a comparator, 12 is a charge pump circuit, 15 is a low-pass filter, 16 is a voltage-controlled crystal oscillator, and 17 is a voltage-controlled crystal oscillator. 16. Next, the operation will be explained.

The input clock signal inputted from the clock signal input terminal 1 is frequency-divided by an appropriate frequency division ratio N in the first frequency dividing circuit 3 and then inputted to the phase comparator 5. On the other hand, the clock signal from the voltage-controlled crystal oscillator 16 is frequency-divided by a suitable frequency division ratio M in a frequency division circuit 17 to become an output clock signal, which is further divided by a frequency division ratio N in a frequency division circuit 4. The signal is input to the phase comparator 5. The phase comparator 5 compares the falling phases of the output signals from the frequency dividing circuits 3 and 4, outputs two phase error signals corresponding to the phase lead and lag, and drives the charge pump circuit 12. . The charge pump circuit 12 outputs high-level and low-level signals depending on the phase lead or lag, and the low-pass filter 15 converts this output signal into an F wave.
A DC voltage that controls the oscillation frequency of the voltage controlled crystal oscillator 1B is obtained. Here, if the phase of the output clock signal lags behind the phase of the input clock signal, the phase comparator 5 outputs a phase error signal of a magnitude corresponding to the phase lag of the output clock signal, and charges Pump circuit 12
The DC component of the output signal increases. Therefore, the level of the output voltage of the low-pass filter 15 increases, and the oscillation frequency of the voltage-controlled oscillator 16 increases, so that the phase difference between the input clock signal and the output clock signal becomes smaller. On the other hand, when the phase of the output clock signal is ahead of the phase of the input clock signal, the phase comparator 5 outputs a phase error signal of a magnitude corresponding to the phase lag of the input clock signal, and the charge pump The DC component of the output signal of circuit 12 is reduced. Therefore, the level of the output voltage of the low-pass filter 15 decreases, and the oscillation frequency of the voltage-controlled oscillator 16 decreases, so that the phase difference between the input clock signal and the output clock signal decreases. By repeating the above operations, an output clock signal that is bit-synchronized with the input clock signal is obtained at the output terminal 2.

[Problem that the invention seeks to solve]

Since the conventional phase synchronized oscillator circuit is configured as described above, when a pulse drop occurs in the input clock signal, a phase error signal with a length corresponding to the number of dropped pulses is output from the phase comparator 5. The charge pump circuit 12. The control voltage of the voltage controlled crystal oscillator 16 changes via the low pass filter 15. For this reason, there is a problem in that whenever a pulse drop occurs in the input clock signal, a phase fluctuation occurs in the output clock signal.

This invention was made to solve the above problems, and even if a pulse drop occurs in the input clock signal,
An object of the present invention is to obtain a phase synchronized oscillation circuit that can continuously output a stable output clock signal without phase fluctuation.

[Means for solving problems]

The phase synchronized oscillation circuit according to the present invention detects a pulse dropout of an input clock signal using a pulse dropout detection circuit, and upon detecting the pulse dropout, changes the clock operation of the second frequency dividing circuit to the second frequency dividing circuit.
The gate circuit is controlled by the first gate circuit.
The charge pump circuit is placed in a high output impedance state by opening the gate, and the voltage controlled crystal oscillator that outputs the output clock pulse is placed in the control state immediately before the pulse dropout occurs.
It was designed to continue to run on its own.

[For production]

The pulse dropout detection circuit in this invention detects a pulse dropout over several time slots of the input clock signal as an input cutoff, and upon receiving this detection signal, the gate signal generation circuit generates an output clock signal after the pulse dropout ends. The output clock is obtained by emitting a gate signal until a period longer than a predetermined bit has elapsed, keeping the charge pump circuit at high impedance during this period, making the voltage-controlled oscillator free-running, and dividing the oscillation output during the period when the pulse continues to be missing. It acts to maintain the phase of the signal at the phase before pulse dropout occurs.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an input terminal for an input clock signal, 2 is an output terminal for an output clock signal, 3 is a second frequency dividing circuit that divides the output clock signal by N, and 5 is a digital phase comparison circuit in the form of a sequential circuit. 6 is a shift register that applies a 3-bit delay to the phase error signal output from the phase comparator 5 when a pulse drop occurs in the input clock signal, and T is a second shift register.
An OR gate as a second gate is connected between the enable terminal that controls the clock operation of the frequency divider circuit 4 and the shift register 7, and 8 and 9 are first gates that cut off the phase error signal when detecting a pulse dropout. Noah Gate as, 1
0 is a pulse missing detection circuit, 11 is a gate signal generation circuit that controls the OR gate 7 and the NOR gate 8.9, 12A
13 and 14 are charge pump circuits, 13 and 14 are 3-state buffers that constitute the charge pump circuit 12A, 15 is a low-pass filter, 16 is a voltage-controlled crystal oscillator, and 17 is a component for frequency-dividing the clock signal output from the voltage-controlled crystal oscillator 16. The circuit 18 is an inverter.

Next, the operation will be explained with reference to FIGS. 2 and 3.

First, the input clock signal A input to the input terminal 1 is input to the first frequency divider circuit 3, and the output clock signal B output from the output terminal 1 is input to the second frequency divider circuit 4.
The frequency is divided by R, respectively, and output signals C and D in FIG. 2 or 3 are obtained. The phase comparator 5 compares the falling phases of the output signals frequency-divided by the frequency dividing circuits 3 and 4. In the following explanation, a case where a pulse dropout occurs in the input clock signal A immediately before the phase where the falling edge is F (this will be referred to as Case 1), and a case where a pulse dropout occurs immediately after the phase where the falling edge is H (this will be referred to as Case 1) will be explained. This is called case 2).
Taking as an example the case where the frequency dividing ratio N=16 of frequency dividing circuits 3 and 4,
Explain the operation.

(A) Case 1 When a pulse drop occurs in the input clock signal A, a pulse drop detection signal E is sent from the pulse drop detection circuit 10 to the gate signal generation circuit 11. When the pulse dropout detection circuit 10 is assembled with a retriggerable monostable multivibrator,
As shown in Figure 2, the detection signal E is approximately 2.
Sent with a bit delay. The gate signal generation circuit 11 is
In order to block the propagation of the phase error signal G to the charge pump circuit 12A, and to transmit the phase error signal H delayed by 3 bits in the shift register 6 to the enable terminal that controls the clock operation of the frequency divider circuit 4. Then, a gate signal F is generated. The reason for applying a gate to the phase error signal H here is to control the clock operation of the frequency dividing circuit 4 only when a pulse dropout is detected. As shown in Fig. 2, the gate signal F is sent out with a delay of about 2 bits after the occurrence of a pulse dropout, so the phase error signal G is delayed by more than 2 bits in the shift register 6 before being sent out as an OR game).
is input to. Figure 2 shows the case where a 3-bit delay is applied.Furthermore, since the timing at which the phase error signal G is generated differs depending on the timing at which a pulse dropout occurs in the input clock signal A, the timing at which the phase error signal G is generated differs. In consideration of the case, as shown in Fig. 2, the gate signal F is sent out for a period of 18 bits or more even after the pulse omission is completed.This gate signal F causes the phase error signal to be The propagation of G to the charge pump circuit 12A is blocked, and the charge pump circuit 12A composed of three-state buffers 13 and 14 enters a high output impedance state.When the charge pump circuit 12A enters a high output impedance state, the voltage control crystal Although the oscillator 16 is in a free-running state, the control voltage of the voltage-controlled crystal oscillator 16 retains the value before free-running, so the output clock signal obtained by dividing the oscillation output by the third frequency dividing circuit 1T. The phase of B can maintain the phase before free running for a period of about several loom+s to 18 when pulse omission continues.On the other hand, the phase error signal H
is applied to the enable terminal for controlling the clock operation of the second frequency dividing circuit 4 via the OR gate 1 while the gate signal F is output, and the clock operation is stopped. Since the phase error signal H is a signal with a length corresponding to the period during which the pulse omission continues, the amount of delay applied to the output signal of the second frequency dividing circuit 4 is the same as that of the first frequency dividing circuit due to the pulse omission. This is equal to the amount of delay applied to the output signal C of No. 3. Therefore, as shown in FIG. 2, after the input clock signal A is restored, the phase comparator 5
Since the phases of the output signals C and D input to the clock signal coincide with each other, no unnecessary phase error signal is generated, and the phase of the clock signal does not fluctuate, and the clock signal continues to be output stably.

(b) Case 2 If a pulse dropout of the input clock signal A occurs immediately after the falling of the output signal C1D, the phase error signal G is divided by the frequency dividing circuit 3.4 as shown in FIG. Since the frequency ratio N=16, the number of missing pulses occurs 15 bits after the occurrence of the missing pulse, n=7 bits long. On the other hand, the pulse dropout detection signal E is n=7 from the pulse dropout occurrence.
Since it is output until after the bit, in order to transmit the phase error signal H, which is the phase error signal G delayed by 3 bits, to the enable terminal of the frequency divider circuit 4 via the OR gate T, the gate signal Ft-1 in FIG. As shown, it is necessary to create a signal that continues to be transmitted over 18 bits or more even after the pulse omission ends. That is, as in case 1, while the gate signal F is being output, the output clock signal B is
The phase is held in a free-running state, and the output signal of the frequency dividing circuit 4 is delayed by the amount of the missing pulse due to the phase error signal. Next, as shown in Figure 3, when the Ginoa gate 8.9 is opened by the gate signal F and the free-running state is released, the phases of the output signals C and D match, so there is no unnecessary phase error. No signal is generated, and the phase of the output clock signal B does not fluctuate and continues to be output stably.

In the above embodiment, the OR gate T is opened only when a pulse drop occurs in the input clock signal A, but the OR gate 7 is normally kept open and is controlled to close only when synchronization is pulled in. Good too. In this case, even if a 1-bit pulse drop that cannot be detected by the pulse drop detection circuit 10 occurs, the phase error signal G will be transmitted to the enable terminal of the frequency divider circuit 4, resulting in a 1-bit delay in the output signal. Therefore, the phase of the output clock signal B can be kept very stable.

〔Effect of the invention〕

As described above, according to the present invention, when a pulse dropout occurs in the input clock signal, the charge pump circuit is brought into a high output impedance state, thereby making the output clock signal free-running, and after dividing the output clock signal, the phase Since the configuration is such that the signal fed back to the comparator is delayed by the amount of the missing pulse, the phases of the input clock signal input to the phase comparator and the output clock signal can continue to match even after the pulse is missing. This makes it possible to prevent unnecessary phase error signals from occurring even after the input clock signal recovers. As a result, even if a pulse drop occurs in the input clock signal, the phase of the output clock signal does not change.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a phase-locked oscillation circuit according to an embodiment of the present invention, FIGS. 2 and 3 are time charts of signals of various parts of the circuit to explain the operation of the circuit shown in FIG. 1, and FIG. FIG. 2 is a circuit diagram of a conventional phase-locked oscillation circuit. 3 is a first frequency divider circuit, 4 is a second frequency divider circuit, 5 is a phase comparator, 7 is a second gate circuit, 8 and 9 are first gate circuits, 10 is a pulse omission detection circuit , 12A is a charge pump circuit, 15 is a low-pass filter, and 16 is a voltage-controlled crystal oscillator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A first frequency dividing circuit that divides the input clock signal by 1/N, a second frequency dividing circuit that divides the output clock signal by 1/N, the first frequency dividing circuit, and the second frequency dividing circuit. a phase comparator that detects the phase difference between each output signal of the frequency dividing circuit; a charge pump circuit that inputs a DC output corresponding to the output of the phase comparator to a low-pass filter; and a charge pump circuit that uses the output of the low-pass filter as a control voltage. , and a voltage-controlled crystal oscillator that oscillates the output clock signal of a frequency corresponding to this, and outputs an output clock signal that is bit-synchronized with the input clock signal. a first gate circuit that performs a gate operation based on the output of the pulse dropout detection circuit; and a second gate circuit that operates only when a pulse dropout is detected based on the output of the pulse dropout detection circuit.
and a second gate circuit for controlling the clock operation of the frequency dividing circuit, and during the pulse missing detection, the first gate circuit is opened to put the charge pump circuit in a high output impedance state, and the voltage is increased. A phase synchronized oscillation circuit characterized in that a controlled crystal oscillator is made to run freely in a controlled state immediately before a pulse dropout occurs. (2) The phase synchronized oscillation circuit according to claim 1, wherein the charge pump circuit has a three-state buffer configuration.