JPS58182324A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To generate a stable clock signal, by applying an output of a time window generator to a pulse generator which shapes the pulse width of the input data signal inputted to a phase comparator and preventing the disturbance of a phase locked loop output due to an input failure data signal generated at the outside of the time window region at the end of synchronism. CONSTITUTION:The time window generator 6 sets a time window signal S12 at the end of asynchronism with a time window switching signal S13 and generates a pulse S2 applying an input data signal S1 from a pulse generator 7 to a phase comparator 2 unconditionally, generates the S12 at the end of synchronism by switching the S13, and when a leading (a) of the input data signal S1 is at the outside of the region of a time window (g), a pulse generator 7 limits the generation of pulses, allowing to prevent phase difference signals S3, S4 of the phase comparator 2 from being generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronization circuit used in a digital magnetic recording device for a magnetic disk, drum, or magnetic tape device, and for a reproducing circuit.

A conventional phase-locked circuit has a configuration as shown in the circuit diagram of FIG. That is, the phase comparator 2 detects the phase difference between the pulse generator output 82 whose pulse width of the input data signal S1 is adjusted to the reference value by the pulse generation 411 and the output clock 86 of the voltage controlled oscillator 4, and the phase difference is detected by the phase comparator 2. Leading phase difference 83. Detected as a slow phase difference 84, filter 3
is converted into a voltage corresponding to the phase difference, and the control voltage S
5 to the voltage controlled oscillator 4.

Stable starting point signal S6 synchronized with input data signal 81
It is a turtle trying to generate.

In such a conventional phase synchronization circuit, when an abnormal input data signal occurs due to the influence of external noise upon completion of synchronization, the phase comparator 2 detects a phase difference outside the range used during normal synchronization.
2. There is a drawback that the black signal in synchronization with the normal input data signal causes disturbances in the signal.

It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide stable input data by generating a window with a width that allows the phase difference to be detected and limiting the generation of pulses due to abnormal data signals occurring outside this time window. An object of the present invention is to provide a phase-locked circuit that generates a torque in synchronization with a signal.

The phase synchronized circuit of the present invention includes: an input shaping circuit that selects an input signal using a time window signal of each predetermined period and outputs a shaped waveform; a phase comparator that compares the phases of the shaped output and the frequency-divided output; A filter that extracts a DC voltage from the output of the phase comparator, a voltage-controlled oscillator that outputs an oscillation signal corresponding to the output voltage of this filter, and a frequency-divided oscillation output of this voltage-controlled oscillator to extract the frequency-divided output. a time window generator for forming the time window signal from each output of the voltage controlled oscillator and the divider; and means for supplying the time window signal to the input shaping circuit upon completion of synchronization. .

According to the present invention, by eliminating the generation of pulses outside the normal synchronization usage range due to the input data signal of the time window generator, the output of the phase synchronization circuit due to the abnormal input data signal due to external noise etc. can be eliminated. Certain clock disturbances can be prevented.

Next, embodiments of the present invention will be described with reference to the drawings.

Fig. 2 is a block diagram of one embodiment of the present invention, and Fig. 3 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram illustrating the operation shown in FIG.

In the figure, the same numbers and symbols as in Fig. 1 indicate the same components as in Fig. 1, 5 is a frequency divider, 6 is a time window generator, 7 is a pulse generator, %810.811 is a frequency divider output, 812 is a time window signal, and 813 is a time window switching signal. The input data signal 8-1 is sent to the pulse generator 7 along with the time window signal 812.
is input. When a rising edge a of the input data signal occurs in a region g where the time window signal is at a high level, the pulse generator 7 outputs a pulse having a rising edge b and a falling edge C as shown in FIG. Occurs in S2.

When the phase comparator 2 receives the fall f)c of the output signal S2 of the pulse generator 197, it compares the phase with the time of the fall 9 of the frequency divider output 811. When the output S2 of the pulse generator 7 is advanced in phase with respect to the fall time of the output 811, it is advanced to the output of the phase comparator 2 and outputs the phase difference signal S3, and when it is delayed,
A delayed phase difference signal S4 is generated at the output of the phase comparator 2.

These phase difference signals 8B and 84tl are combined by a t filter 83.

Potential output 5 corresponding to phase difference by removing high frequency components
is supplied to a voltage controlled oscillator (hereinafter referred to as vCM) 4 to control this VCM 4. In this embodiment, at the time of synchronization, the VCM4 has a frequency four times that of the input data signal as shown in FIG.
is oscillating. The output of this VCM4 is supplied to the divider 5, the divided output 810 is supplied to the phase comparator, and the output 810.degree. 811 is supplied to the time window generator 6 together with the output S6 of the VCM4. This time window generator 6Fi, JI
As shown in figure a, 1 output 810 is low level, output 81
1 is at a high level, it generates a time window signal 812 (a signal that becomes a high level region at g) that is set at the falling edge d of the output S6 of VCMg and reset at the next falling edge e of the output of VCMg. In addition, the time window generator 6 sets the time window signal 812 to the time window switching signal 813 when the asynchronous operation is completed, and the pulse generator 7 unconditionally supplies the input data signal S1 to the phase comparator 2 with a pulse S2. When synchronization is completed, the L time window switching signal 813 is switched, and the time window signal 812 shown in FIG. 3 is generated.
When the rising edge a of the input data signal S1 arrives outside the time window g, the pulse generator 7 can limit pulse generation and prevent the phase difference signal 83, 84 of the phase comparator 2 from being generated. .

As explained above, the present invention provides an input for inputting the time window generator output to the phase comparator and a pulse generator for shaping the pulse radiation of the data signal. This has the effect of preventing disturbances in the output of the phase-locked circuit due to abnormal input data signals generated externally, and generating stable start and stop signals.

[Brief Description of the Drawings] Figure 1 is a block diagram of a conventional phase-locked circuit, Figure 2 is a program diagram showing an embodiment of the present invention, and Figure 3 is a timing diagram explaining the operation of Figure 2. It is a diagram. In the figure, 1, 7... pulse generator, 2°゛゛°. Phase comparator, 3...Filter, 4...
Voltage controlled oscillator, 5... Frequency divider, 6...
・It is a time window generation circuit.

Claims (1)

[Claims] An input shaping circuit that selects an input signal using a time window signal of each predetermined period and outputs a shaped waveform; a phase comparator that compares the phases of the shaped output and the frequency-divided output; and a DC voltage from the output of the phase comparator. a voltage-controlled oscillator that outputs an oscillation signal corresponding to the output voltage of the voltage-controlled oscillator; a frequency divider that divides the oscillation output of the voltage-controlled oscillator and extracts the frequency-divided output; A phase locked circuit comprising a time window generator forming said time window signal from respective outputs of a controlled oscillator and a frequency divider, and means for providing said time window signal to said input shaping circuit upon completion of synchronization.