JPS59117720A - Digital phase synchronization circuit - Google Patents

Abstract

PURPOSE:To generate a stable clock signal by adding limits to a phase difference signal functioning as an output of a phase comparator by an output of a time window generator to decrease the disturbance in a phase synchronization circuit output by a failed input data signal. CONSTITUTION:The phase comparator 4 detects a phase difference of falling time between an input data signal S6 and a frequency divider output S14 and generates a pulse corresponding to the phase difference. Phase difference signals S7, S8 are inputted to a gate 5 together with a time window signal S15. The gate 5 generates phase difference signals S9, S10 where the phase difference signals S7, S8 exceeding a high-level region of the time window signal S15 are eliminated. A synthesized and a high-frequency component are eliminated from S9, S10 serving as gate outputs by a filter 6 and the result is supplied to a VCM7 as a VCM control voltage. An output S12 of the VCM7 is supplied to a frequency divider 8, where the output is frequency-divided into S13, S14, which are supplied to a time window generator 9 together with the S12. The phase difference signals S7, S8 are limited by generating a time window to the time window signal S15, allowing to set limits to a phase difference signal exceeding the time window by the time window.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronization circuit used in a clock regeneration circuit of a digital magnetic recording device such as a magnetic recording device or a drum device.

Generally, as shown in FIG. 1, the phase synchronized circuit converts the phase difference between the input data signal S1 and the output clock S5 of the voltage controlled oscillator 3 into a phase difference S2 using the phase comparator 1.
, is detected as a lagging phase difference S3, is converted into a value corresponding to the phase difference by a filter 2, and is supplied to the voltage controlled oscillator 3 as a control voltage S4, thereby achieving a stable lock synchronized with the input data signal S1. Signal voltage controlled oscillator 3
It is intended to be generated from

In such conventional phase-locked circuits, if an abnormal input data signal occurs due to the influence of external noise etc. when synchronization is completed, the phase comparator detects an excessive phase difference compared to the phase difference during normal synchronization, and This method has the disadvantage that the clock signal which is in synchronization with the input data signal is disturbed.

An object of the present invention is to generate a time window with a width that allows the phase synchronization circuit to generate a normal phase difference of %a during normal synchronization, and to limit the supply of the phase comparator output to the filter by the time window. Reduces clock disturbances caused by abnormal data signals,
An object of the present invention is to provide a phase synchronization circuit that generates a clock synchronized with a stable input data signal.

The circuit of the present invention includes a phase comparator that detects the phase difference between the input data signal and the output of the heavy pressure controlled oscillator or a signal obtained by frequency-dividing the output, and a limiter (gate) that limits the phase difference at the completion of synchronization using a time window signal. ), a filter that removes high-frequency components of its output, a voltage controlled oscillator controlled by the filter output, and a time window generator that generates the time window upon completion of synchronization.

A feature of the present invention is that a time window generator is used to limit the phase difference detection output during normal synchronization, and by eliminating excessive phase difference output from being supplied to the filter, abnormal input data signals such as external noise can be detected. This reduces disturbances in the clock that is the output of the phase-locked circuit.

Next, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows a block diagram of an embodiment of the present invention, and FIG. 3 is a timing diagram explaining the operation of FIG.

In FIG. 2, 4 is a phase comparator, 5 is a gate, 6 is a filter, 7 is a voltage controlled oscillator (hereinafter referred to as VCM), 8
is a frequency divider, 9 is a time window generator, S6 is an input data signal,
S7 is a leading phase difference signal, S8 is a delayed phase difference signal, 89,
810 are leading and delayed phase difference signals limited by the time window signal, S11 is the filter output signal, S12
is a VCM output, 813 and 814 are frequency divider outputs, 815 is a time window signal, and 816 is a time window switching signal. Then the third
The operation shown in FIG. 2 will be explained with reference to the drawings.

The same signal names are used in FIGS. 2 and 3.

Input data signal S6 is output from frequency divider output 814 and phase comparator 4
is input. When the falling edge of the input data signal S6 is input, the phase comparator 4 detects the phase difference between the falling edge of the input data signal S6 and the falling edge of the frequency divider output S14. At this time, a pulse corresponding to the phase difference b is generated in the advanced phase difference signal S7. Similarly, when C is a slow phase, a pulse corresponding to the phase difference d is generated in the slow phase difference signal S8. The phase difference signals 87,88 are input to the gate 5 together with the time window signal 815. The gate 5 receives a phase difference signal S7 in which the time window signal 815 exceeds the high level region e.
, 88 are removed to generate phase difference signals 89, 810. The phase difference signals 89 and 810, which are the outputs of the gate 5, are synthesized by the filter 6 (synthesized by inverting one phase) and remove high frequency components, and are converted to VCM as a control voltage.
It is supplied to CM7. In this embodiment, during synchronization, the VCM 7 oscillates at a frequency four times that of the input data signal, as shown in FIG.

The output 5 of the VCM 7 is supplied to the ISU frequency divider 8, frequency-divided as shown at 813 and 814 in FIG. 3, and supplied to the time window generator 9 together with S12. As shown in FIG. 3, in the time window generator 9, when 812 falls when 813 and 814 are at the no-y level, a time window signal 815 is set, and is reset at the next falling edge of 812. A time window signal 815 in the level region e shown in the figure is generated. When the time window generator 9 is pulled in by the time window switching signal 816, the time window signal S15 is set to the noise level, and the 7 phase difference signal 87.88 is supplied to the filter 6 as 89.810 without any restriction.

Therefore, when the same quantity is completed, by switching the time window switching signal 816, a time window indicated by e is generated in the time window signal 815 shown in FIG. The phase difference signal that exceeds the window can be limited by the time window.

As explained above, the present invention applies a limit to the phase difference signal which is the time window generator output and the phase comparator output, so that the phase synchronization circuit outputs due to the abnormal theta signal occurring outside the time window region at the time of synchronization completion. This has the effect of reducing disturbances and generating a stable lock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a general phase synchronization circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram used to explain FIG. In the figure, 1, 4... Phase comparator, 2.6-゛... Filter, 3, 7... Voltage controlled oscillator, 5
...Gate, 8...Divider, 9...
...Time window generator. −゛・、Representative Patent Attorney Susumu Uchihara′

Claims (1)

[Claims] A digital phase-locked circuit having a voltage-controlled oscillator, a digital phase comparator, and a filter, comprising a time window generator, and supplying the output of the phase comparator to the filter upon completion of synchronization with a time window generator. A digital phase-locked circuit characterized in that it has means for restricting theft.