JP3272930B2 - Digital phase locked loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) circuit, and more particularly to a digital PLL circuit for a digital signal processing circuit, such as a video tape recorder (VTR) or a television receiver. It is used for

[0002]

2. Description of the Related Art In a television receiver, for example, a synchronizing signal (horizontal synchronizing signal, vertical synchronizing signal) included in a composite video signal is separated and taken out, but disturbance (noise, etc.) included in this signal is dealt with. For this purpose, this signal is input to a PLL circuit, and an output signal of an oscillation circuit of the PLL circuit synchronized with the input signal is used.

There are two types of PLL circuits: an analog PLL circuit using analog control and a digital PLL circuit using digital control.
As an example of the circuit, the circuit has a configuration as shown in FIG.
Reset type P that operates like the timing waveform shown in
LL circuits are known.

In FIG. 3, a differentiating circuit 31 differentiates a rising edge (leading edge) of a reference input pulse signal to generate a differentiated pulse signal, and then supplies it as a first input of a two-input AND circuit 32. The two-input AND circuit 32 receives a pulse signal for masking as a second input,
A reset pulse signal is output by AND processing of two inputs.

In this case, the two-input AND circuit 32
Masking is performed so that the reset pulse signal is not output while the masking pulse signal input is at the “L” level, and reset when the differentiated pulse signal is input while the masking pulse signal input is at the “H” level. Outputs a pulse signal.

On the other hand, the frequency dividing circuit 33 receives the reset pulse signal, is reset at its leading edge, and its frequency divided output falls ("L" level). The frequency output is inverted to “H” level, and the frequency output is supplied as the mask pulse signal.

Accordingly, the masking pulse signal is reset at the leading edge of the reset pulse signal and changes from "H" level (unmasked state) to "L" level (masked state).
After the clock signal input is counted by a predetermined number, it returns to the “H” level (unmasked state).
It is reset again at the rising edge (leading edge) of the reference input pulse signal.

The frequency dividing circuit 33 outputs an output pulse signal having a predetermined time width in synchronization with the fall of the frequency divided output. As described above, the digital PLL circuit of FIG. 3 uses the two-input AND circuit 32 to remove the noise even if the reference input pulse signal includes noise during the masking period when the masking pulse signal is in the “L” level state. Since the masking is performed, the reset input of the frequency dividing circuit 33 is not affected. As a result, a signal synchronized with the reference input pulse signal is obtained as the output pulse signal of the frequency dividing circuit 33.

However, if noise is added to the reference input pulse signal when the masking pulse signal is at the "H" level, the noise cannot be masked by the two-input AND circuit 32, and the noise is applied. The frequency dividing circuit 33 is reset, and as a result, the output pulse signal of the frequency dividing circuit 33 is generated in synchronization with the noise of the reference input pulse signal.

As a countermeasure, in order to make the mask period as close as possible to the cycle of the reference input pulse signal, the count number of the clock signal input in the frequency dividing circuit 33 is increased and the "L" level of the mask pulse signal is increased. The longer the period, the better.

However, in this case, considering the fluctuation of the reference input pulse signal, the responsiveness and the variation of the circuit characteristics,
It cannot be made extremely close, and the circuit configuration becomes relatively complicated, and the number of elements used increases.

[0012]

As described above, in the conventional reset type PLL circuit, when noise is added to the reference input pulse signal when the masking pulse signal is in a non-masked state,
The frequency divider is reset under the influence of this noise, and as a result, there is a problem that the output pulse signal of the frequency divider is generated in synchronization with the noise of the reference input pulse signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in view of the above. A digital phase locked loop capable of outputting a stable pulse signal synchronized with a reference input pulse signal without being affected by disturbance to the reference input pulse signal. It is an object to provide a loop circuit.

[0014]

According to the digital phase locked loop circuit of the present invention, a reference input pulse signal is input as a first input, and a 1 / N frequency-divided output signal is input as a second input. By performing AND operation on the two input signals,
A two-input AND circuit that outputs a clock sampling control pulse signal whose pulse width is determined , a clock signal input and the clock sampling control pulse signal are input, and the period of the sampling control pulse signal is the sampling control level. During the period when the extraction control pulse signal is at the extraction release level, a clock extraction gate circuit for passing the clock signal input and a passing clock signal passing through the clock extraction gate circuit are input. Clock signal input is 1 /
A frequency divider for dividing the frequency by N to output a 1 / N frequency-divided output signal and outputting an output pulse signal having a predetermined time width in synchronization with the leading edge of the 1 / N frequency-divided output signal. It is characterized by the following.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a digital PLL circuit according to a first embodiment of the present invention. FIG.
In the AND circuit (in this example, a two-input AND circuit)
Reference numeral 11 denotes a reference input pulse signal input as a first input, and 1 / N from a frequency dividing circuit 13 described later as a second input.
The frequency-divided output signal is input, and the two reference input pulse signals are logically processed to output a clock sampling control pulse signal described later.

The clock extraction gate circuit 12 receives the clock extraction control pulse signal and the clock signal input, and controls the extraction of the extraction control pulse signal.
The passage of the clock signal input is prohibited / permitted in accordance with the sampling release period. In this example, the operation is such that the passage of the clock signal input is inhibited (extracted) while the sampling control pulse signal is at the sampling control level “H”, and the clock signal input is passed during the period of the sampling canceling level “L”.

The clock sampling gate circuit 1
As one example, the inverter circuit 121 inverts the input of the clock sampling control pulse signal, and a two-input AND circuit 122 to which the output signal and the clock signal of the inverter circuit 121 are input.

The frequency dividing circuit 13 receives the passing clock signal passed through the clock extracting gate circuit 12 and divides the passing clock signal input by 1 / N to obtain 1 / N.
Outputs the divided output signal. Further, the frequency dividing circuit 13
An output pulse signal having a predetermined time width is output in synchronization with the rising edge (leading edge) of the 1 / N frequency-divided output signal.

FIG. 2 is a timing waveform showing an operation example of the digital PLL circuit of FIG. The above digital PLL
In the circuit, while the 1 / N-divided output signal is at the “L” level, the sampling control pulse signal output from the two-input AND circuit 11 is at the sampling canceling level “L” and passes through the clock sampling gate circuit 12. The passed clock signal thus input is input to the frequency dividing circuit 13, and the frequency dividing circuit 13 performs a frequency dividing operation (counting operation).

After the frequency dividing circuit 13 counts a predetermined number of frequency dividing inputs, the 1 / N frequency dividing output signal is inverted to "H" level. The 1 / N-divided output signal has a duty ratio of approximately 1: 1.

As described above, during the period when the reference input pulse signal is at the "H" level after the 1 / N frequency-divided output signal attains the "H" level, the sampling control pulse output from the two-input AND circuit 11 The signal becomes the sampling control level “H”, and the frequency division input of the frequency dividing circuit 13 is prohibited. After the reference input pulse signal falls to the "L" level and the sampling control pulse signal goes to the sampling release level "L", the frequency dividing circuit 13 receives the frequency dividing input and resumes the frequency dividing operation. I do.

In this case, assuming that the 1 / N frequency-divided output signal becomes "H" level earlier than the reference input pulse signal,
Since the period of the sampling control level “H” of the sampling control pulse signal is prolonged, and as a result, the start timing of the frequency division input of the frequency dividing circuit 13 is delayed, so that the 1 / N frequency-divided output signal becomes “H” level next. Control to delay the time.

On the other hand, if the 1 / N frequency-divided output signal becomes "H" level later than the reference input pulse signal, the sampling control level "H" period of the sampling control pulse signal is shortened. Since the start timing of the frequency division input of the frequency division circuit 13 is advanced, control is performed so that the point in time at which the 1 / N frequency-divided output signal becomes “H” level is advanced.

Therefore, the sampling control level "H" period of the sampling control pulse signal follows the period change of the reference input pulse signal, and the 1 / N-divided output signal and the output pulse signal are synchronized with the reference input pulse signal. I will be.

That is, in an operation state in which the feedback control of the closed loop in the digital PLL circuit is stable, the average value of the number of clock signal input samplings (the number of passage inhibition) by the sampling control pulse signal is represented by K, where 1 / N
The cycle T of the frequency-divided output signal and the output pulse signal has (K + N) clock signal input cycles t.

T = (K + N) t (1) Therefore, as a design condition of the digital PLL circuit, the maximum frequency H of the frequency divider 13 is larger than N · t, and the maximum sampling of the clock signal input is performed. The “H” level period of the reference input pulse signal for determining the number needs to be larger than K · t.

Actually, since K is an integer, jitter between K and K + 1 occurs, but this can be ignored if the output of the clock signal input is set high if necessary. According to the above embodiment, the reset function of the frequency dividing circuit 13 is not required, and the overall circuit configuration is simplified, so that the number of elements used can be reduced.

[0028]

As described above, according to the digital phase locked loop circuit of the present invention, a stable pulse signal synchronized with the reference input pulse signal can be output without being affected by disturbance to the reference input pulse signal. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an embodiment of a digital PLL circuit of the present invention.

FIG. 2 is a timing waveform chart showing an operation example of the digital PLL circuit of FIG.

FIG. 3 is a block diagram showing an example of a conventional digital PLL circuit.

FIG. 4 is a timing waveform chart showing an operation example of the digital PLL circuit of FIG. 3;

[Explanation of Symbols] 11: AND circuit, 12: Clock sampling gate circuit, 13: Frequency dividing circuit.

Claims (3)

(57) [Claims] 1. A reference input pulse signal and a 1 / N frequency-divided output signal are inputted, and these two input signals are logically processed.
And a two-input AND circuit that outputs a clock sampling control pulse signal whose pulse width is determined by the operation of the sampling sampling control pulse signal and the clock signal input, and controls sampling / cancellation of the sampling control pulse signal. And a clock extraction gate circuit for inhibiting / permitting the passage of the clock signal input corresponding to the period, and a passing clock signal passing through the clock sampling gate circuit being input, and dividing the input of the passing clock signal by 1 / N. To output a 1 / N frequency-divided output signal,
A frequency divider that outputs an output pulse signal having a predetermined time width in synchronization with a leading edge of the N-divided output signal. 2. The digital phase-locked loop circuit according to claim 1, wherein the reference input pulse signal is a signal obtained by separating and extracting a synchronization signal included in a composite video signal. circuit. 3. The digital phase-locked loop circuit according to claim 1, wherein a maximum frequency division cycle of the frequency division circuit is larger than a product N · t of a frequency division number N and a cycle t of the clock signal input. The period of the reference input pulse signal that determines the maximum number of clock signal input samplings is determined by the product of the average value K of the number of clock signal input samplings by the sampling control pulse signal and the clock signal input period t. Digital phase locked loop circuit characterized by being large.