KR200165753Y1 - Clock restration circuit of digital image decoder - Google Patents

Abstract

The present invention relates to a clock recovery circuit of a digital image decoder, and more particularly, to a clock recovery circuit of a digital image decoder for recovering a clock by approaching a counter in accordance with an applied synchronization signal.

The clock recovery circuit of the digital image decoder according to the present invention is synchronized with the system clock of the encoder by time information (PCR or SCR) contained in header information on a bit stream input at an arbitrary interval. In a clock recovery circuit of a digital image decoder for outputting a clock, a local clock generator for generating a local clock, and the reference clock is counted by varying the number of reference clocks according to an input control signal. A system counter for outputting a clock signal by varying the output level for each number, a PCR counter for outputting a prediction value (PCR ') by inputting the output signal of the system counter and the PCR value of the first header information, and the PCR counter A subtractor for comparing and subtracting the PCR of the predicted value PCR 'and the second header information, and an output of the subtractor as an input, when an error above the threshold occurs. A threshold detection unit for outputting a control signal to change the number of reference clocks of the system counter, a vertical and horizontal synchronization signal generator for dividing the output signal of the system counter to generate vertical and horizontal synchronization signals, and the local clock generator And a divider for dividing the output signal of ½ and outputting a pixel clock.

Description

Clock Restoration Circuit of Digital Image Decoder

1 is a block diagram of a general digital video decoder.

2 is a block diagram showing a conventional system clock recovery circuit.

3 is a block diagram showing a system clock recovery circuit of the present invention.

4 is a timing diagram showing an example of restoration of a system clock according to the present invention.

* Explanation of symbols for main parts of the drawings

30: threshold detection unit 31: system counter

32: local clock generator 33: divider

34: PCR counter 35: vertical and horizontal synchronous signal generator

36: subtractor

The present invention relates to a clock recovery circuit of a digital image decoder, and more particularly, to a clock recovery circuit of a digital image decoder for recovering a clock by approaching a counter in accordance with an applied synchronization signal.

In general, a digital video system carries time information (Program Clock Reference (PCR) or System Clock Reference (SCR)) for restoring vertical and horizontal synchronization signals on a bit stream.

Hereinafter, a clock recovery circuit of a conventional digital image decoder will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a general digital video decoder and FIG. 2 is a block diagram showing a conventional system clock recovery circuit.

First, as shown in FIG. 1, a general digital video decoder system depacketizes header information when a system bit stream is input through a transport channel, and outputs a pure video bit stream (at this time, although not shown in the drawing) A bit stream is also output.) The system decoder 1 extracts and outputs PCR or SCR information indicating a clock state from the header information, and receives and decodes the compressed bit stream of the system decoder 1. A video generator (2), a timing generator (4) for reproducing vertical and horizontal synchronization signals and a pixel clock by inputting SCR or PCR information of the system decoder (1), and the video NTSC signal that NTSC encoder processes and outputs the reconstructed video signal (RGB or YUV) in which the vertical and horizontal synchronization signals and the pixel clock are synchronized by the decoder 2 Is configured to include a processing unit (3). The reason for using the SCR or the PCR in the timing generator 4 is to synchronize the clocks of the encoder and the decoder. In an analog system, the encoder clock is directly restored from a time recovery circuit. This is because digital systems use end-to-end synchronization using time information between local clocks.

The reason for synchronizing the clock of the decoder with the clock of the encoder as described above is that if the speed of the decoder is different from the speed of the encoder, the number of frames of the reproduced video is different from that of the encoder, and thus the video decoder buffer (Video Decoder Buffer). ) Is overflowed or underflowed so that the lip-sync with the audio signal is broken.

Referring to FIG. 2, a conventional system clock recovery circuit 5 including the timing generator 4 in the decoder Docoder configured as described above will be described below.

When the SCR or PCR is received from the system decoder 1 and the initial value is loaded into the counter 23, the counter 23 receives the clock of the voltage controlled oscillator 22 and the value is 27 MHz. It will increase at a speed of (90KHz VCO for MPEG1).

The PCR or SCR input after the initial value is compared and subtracted by the subtractor 20 with the predicted value increased from the counter 23 to obtain an error.

If the clock in the encoder is faster, the + value is the result of the subtraction (which indicates that the encoder's phase is faster).

The subtraction result (Error) is input to the frequency of the VCO 22 through the LPF (Low Pass Filter) 21, the + value to increase the frequency of the VCO 22,-value is the VCO (22) Allow the frequency of to be reduced.

The VCO 22 changes the frequency according to the change of the input value to synchronize with the clock speed of the encoder.

Here, the VCO refers to a voltage controlled oscillator that changes the oscillation frequency by an external voltage without adjusting the coil or the baricon.

However, in the conventional system clock recovery circuit as described above, since the system clock recovery circuit is configured using the expensive VCO and LPF, there is a problem in that the manufacturing cost of the system configuration is high and the circuit is complicated.

The present invention was devised to solve the problems of the system recovery circuit of the conventional digital image decoder as described above. The circuit is simplified and the low cost configuration is achieved using only a counter and a gate without using an expensive VCO. It is an object of the present invention to provide a clock recovery circuit of a digital image decoder having improved practicality.

The clock recovery circuit of the digital video decoder of the present invention for achieving the above object is an encoder system by time information (PCR or SCR) contained in header information on a bit stream input at an arbitrary interval. In a clock recovery circuit of a digital video decoder for outputting a clock synchronized with a clock, a local clock generator for generating a local clock and a number of reference clocks are counted according to the input control signal to count the local clock. A system counter for outputting a clock signal by changing an output level for each reference clock number, a PCR counter for outputting a prediction value PCR 'by inputting an output signal of the system counter and a PCR value of first header information; A subtractor which compares and subtracts the predicted value PCR 'of the PCR counter with the PCR of the second header information, and an output of the subtractor as an input is equal to or greater than a threshold A threshold detector for changing a reference clock number of a system counter by outputting a control signal each time an error occurs; a vertical and horizontal synchronous signal generator for splitting an output signal of the system counter to generate vertical and horizontal synchronous signals; And a divider for dividing the output signal of the local clock generator by ½ to output a pixel clock.

Hereinafter, the clock recovery circuit of the digital image decoder of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing a system clock recovery circuit of the present invention.

First, the local clock is counted by varying the number of reference clocks of 300 Hz according to a local clock generator 32 generating a 27 MHz local clock and an input up / down control signal. A system counter 31 for outputting a clock signal of 90 KHz (which varies according to the change of the reference clock number) by varying an output level for each reference clock number, an output signal of the system counter 31, and a first header on a bit stream Comparing and subtracting a PCR counter 34 that outputs a prediction value PCR 'by inputting a PCR (Program Clock Reference) value of information, and a PCR of the predicted value PCR' and the second header information of the PCR counter. The subtractor 36 and the output of the subtractor 36 are inputted, and an up / down control signal is outputted to the system counter 31 whenever an error in the phase of the clock exceeds a threshold value. Changing the reference clock number of the system counter 31 The vertical and horizontal synchronous signal generators 35, which divide the output signal of the system counter 31 to generate vertical and horizontal synchronous signals, and the 27 MHz of the local clock generator 32, And a divider 33 for dividing the clock signal into two to output a pixel clock.

In the MPEG-accepting system, the system clock band is set to 90 KHz in MPEG I and 27 MHz in MPEG II. This is a basic 33 bit PCR or SCR field with a 90 KHz default resolution, and 9 bits in MPEG II. Expressed as 27MHz using Extension Code of.

The clock recovery circuit of the digital image decoder according to the present invention loads the PCR counter 34 when the SCR or PCR value extracted from the system decoder is the first value.

The PCR counter 34 is a system counter 31 that toggles the output level of the clock signal of 27 MHz of the local clock generator 32 to " 1 " and " 0 " states every 150 clocks in the steady state. ) Is connected to receive the input of 90KHz (27MHz divided by 300 clocks), the band of the system clock.

The 90 KHz clock output from the system counter 31 is output as a synchronous clock through the vertical and horizontal synchronous signal generators 35, and the 27 MHz clock of the local clock generator is divided in two by the divider 33. It will output at a pixel clock of 13.5MHz.

The predicted value PCR 'of the PCR counter 34 and the second PCR value detected in the second header information are compared and subtracted by the subtractor 36, and the threshold detection unit 30 converts the up or down control signal into a system counter ( 31).

The time interval in which the system counter 31 is zero is reduced or increased at 150 clocks.

The phase error range of the threshold detected by the threshold detector 30 varies depending on the application, but generally allows a duty rate of ± 10% and an error of a clock period.

Therefore, when an error of ± 10% occurs, the period of the system counter 31 is 300 clocks, so 30 clocks (calculated at 300 clocks x 0.1) are reduced or increased by the system counter 31.

That is, when the value of + is input to the threshold detector 30 (which means that the value of PCR is large and indicates that the clock phase of the encoder is fast), the system counter 31 becomes 120 reference clocks. After 120 clocks are counted and the output level is changed, the phase is pulled forward again to 150 clocks.

If a value of-is input, the system counter 31 becomes the reference clock number of 150 clocks and 150 clocks are counted to change the output level.

As shown in FIG. 4, which is a timing diagram showing an example of a system clock according to the present invention, "a" indicates a case where a phase value is faster in an encoder because the PCR value is larger than PCR 'and the phase error is 90 KHz. If the tolerance of the clock generated by the system counter is exceeded, the length of the '0' state of the output level is reduced by the up signal, and a rising edge (RE) occurs before the normal rising edge position (REP).

Therefore, the following RE shows that the phase is aligned.

"b" indicates the opposite case, which means that the PCR 'value is larger than the PCR and the phase is later in the encoder. The length of the' 0 'state of the output level is increased later than the normal REP due to the down signal. As the RE occurs, the phase is aligned in the next RE.

As described above, the clock recovery circuit of the digital image decoder of the present invention performs a clock recovery function using only a counter and a gate, thereby simplifying the circuit and reducing manufacturing cost with a low cost configuration.

Claims (1)

In a clock recovery circuit of a digital video decoder for outputting a clock synchronized with a system clock of an encoder by time information (PCR or SCR) contained in header information on a bit stream input at an arbitrary interval, Local clock generator for generating a local clock, and a system counter for counting the local clock by varying the number of reference clocks according to an input control signal, and outputting a clock signal by changing the output level for each reference clock. And a PCR counter for outputting the prediction value PCR 'by inputting the output signal of the system counter and the PCR value of the first header information, and comparing the PCR of the predicted value PCR' of the PCR counter with the second header information. A subtractor for subtracting and an output of the subtractor are inputted to output a control signal whenever an error exceeding a threshold occurs so as to change the reference clock number of the system counter. A threshold detector for dividing the output signal of the system counter to generate a vertical and horizontal synchronization signal, and a divider for dividing the output signal of the local clock generator to output a pixel clock. Clock recovery circuit of the digital video decoder, characterized in that it comprises a.