JPS6269791A - Clock signal reproducing device - Google Patents

Abstract

PURPOSE:To largely improve a recovery speed from a step out of a clock signal by dividing a frequency range of a step out period into two, suitably selecting processing methods of different speeds to perform a VCO control. CONSTITUTION:An FPP signal is extracted from an input composite video signal in a frame pulse point detecting circuit 2, an internal FPP signal is formed in an N1-adic counter 5 to obtain a phase difference between both the signals in a phase comparison circuit 6. Independent therefrom, by using an N2-adic counter 11, a signal having a shorter period than a frame period from a clock signal supplied from a VCO8. In a frequency detecting circuit 12, a frequency of an output clock signal formed in the VCO8 is detected, a switch 13 throws to an (a) side until the frequency enters the second frequency range and the VCO8 is controlled by an output signal of an up/down counter 7. As soon as the frequency of the clock signal is included in the second frequency range, the switch 13 throws to a (b) side, the counter 7 is operated by the output of the phase comparison circuit 6 and the VCO8 is controlled more accurately to perform the phase control of the clock.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a receiving device for a television signal that has been subjected to band compression processing. and a synchronizing signal for synchronizing frames equivalent to two horizontal scanning periods within a vertical blanking period, once per frame, are transmitted together with the image signal. It is.

Conventional technology When transmitting a wideband image signal such as a high-definition television signal, a method for reducing the signal bandwidth by sub-Nyquist sampling [MUSE (
Lucky Full “ke Nyquist Shift 1 Nongenin Coding”
Multiple Sub-NyquistSamp
It was proposed as a ling encoding method.

This method is called a motion-compensated multiplex sub-Nyquist sampling transmission method, and in detail, the sampling phase is offset between fields and frames, and processing is performed such that the sampling phase goes around in four fields. This is an analog transmission.

In addition, in this method, it is necessary to sample and digitize the input analog signal and supply a sampling clock signal (hereinafter abbreviated as clock signal) for digitally processing the video signal inside the receiver. , this clock signal must be phase-locked to the input synchronization signal. Therefore, it is necessary to generate this clock signal inside the receiver.

Conventional examples related to the present invention will be described below with reference to the drawings. FIG. 2 shows a clock signal regeneration circuit in the conventional MUSE system.

A television composite video signal containing a horizontal synchronization signal and a synchronization signal for synchronizing frames (this is defined as a frame pulse, hereinafter abbreviated as FP) is also input to the input terminal 1, and the frame pulse point detection circuit 2 and the phase error detection circuit 3.

The frame pulse point detection circuit 2 detects the FP in the input composite video signal, further detects the frame pulse point (hereinafter abbreviated as PPP) synchronized with the clock signal transmitted via the signal line 4, and compares the phase. At the same time, a signal with a horizontal scanning period synchronized with the PPP signal is sent to the phase error detection circuit 3. It should be noted that since the circuits of this conventional example are all composed of digital circuits, there are a frame pulse point detection circuit 2, a phase error detection circuit 3, and a frame pulse point detection circuit 3, which operate at the sampling clock cycle. N1 counter 6, phase comparator circuit 6. It is clear that all the digital low-pass filters 9 are supplied with an output clock signal generated by a voltage controlled oscillator (hereinafter abbreviated as VCO) 8 via the signal line 4.

As described in Japanese Patent Application Laid-open No. 59-221091, the phase error detection circuit 3 detects a value twice the signal level of the current sample point of the input composite video signal, two sample points before the current one, and two sample points after the current one. The frame pulse point detection circuit 2 constantly calculates the difference from the value obtained by adding the signal levels.
A phase error signal corresponding to each horizontal scanning period is extracted at a fixed position in the horizontal synchronizing signal period of the composite video signal using the signal sent from the composite video signal. The phase error signal is integrated by a digital low+hass filter 9 and fed back to the VCOs.

On the other hand, the frame pulse point detection circuit 2 detects a PPP signal (hereinafter referred to as a detected PPP signal) in the FP included in the input composite video signal, and the N1 counter 6 generates an oscillation output clock signal having the standard clock period of the VCOs. By lowering the frequency of the detected PPP signal, a signal (hereinafter referred to as an internal PPP signal) having a frequency equivalent to that of the detected PPP signal is formed. A phase comparison circuit 6 calculates the phase difference between the detected PPP signal and the internal PPP signal, and the output signal of the phase comparison circuit 6 causes an up/down counter 7 to be set in the direction of zeroing the phase difference between the two signals in a frame period. The output signal is converted into a voltage value, and vcos is controlled to control the phase of the clock signal.

The former loop composed of the phase error detection circuit 3, digital low-pass filter 9, and VCOs is a so-called phase-locked loop (hereinafter abbreviated as PLL), and the latter circuit constitutes an offset phase adjustment circuit. This was a two-stage clock signal regeneration circuit in which, when clock synchronization is lost, the offset phase adjustment circuit operates until the synchronization is within a range in which synchronization can be achieved, and the PLL operates in parallel once the synchronization is within the range.

Problems to be Solved by the Invention The conventional clock signal regeneration circuit controls the clock frequency in the horizontal scanning period using the horizontal synchronizing signal included in the composite video signal, and also controls the clock frequency at the horizontal scanning period using the horizontal synchronizing signal included in the composite video signal.
The clock phase is controlled at the frame period using P. Since the FP is sent only once per frame, phase control can only be performed at the frame cycle, and therefore it is controlled at the frame cycle for the entire period from a state in which the clock signal frequency is significantly deviated until it returns to the locked state. The problem is that it takes a considerable amount of time to complete the process.

Means for Solving the Problems In order to solve the above problems, in the present invention, a frequency range with an appropriate width is set around the desired frequency of the output clock signal of the oscillator, and the outside of this range is set as the first frequency. In addition to the conventional circuit, a frequency detection circuit and a counter with a shorter cycle than the counter provided in the conventional circuit are installed.The frequency detection circuit detects the oscillator output. While detecting the frequency of the clock signal, if the frequency of the output clock signal is within the first frequency range, a newly installed counter converts the oscillation output signal of the oscillator into a frequency-downgraded signal instead of the output signal of the phase comparison circuit. The output signal frequency of the oscillator is controlled in the direction of driving it into the second frequency range at high speed, and when the clock frequency is pulled into the second frequency range, it switches to frame period phase control using conventional FP. When the clock frequency is pushed into the range where PLL control operates, a three-stage clock signal regeneration circuit that operates in PLL1 mode is created.

If the frequency of the output clock signal of the oscillator is significantly different from the input synchronization signal and is in the first frequency range, first change the frequency of the output clock signal to the second frequency at a period shorter than the frame period, for example, the horizontal scanning period. By driving the clock signal into the frequency range at high speed, and then controlling the frequency of the clock signal within the range where synchronization can be achieved using the FP transmitted at the frame cycle, the clock signal regeneration circuit shown in the conventional example can be synchronized. It becomes possible to obtain a clock signal that is phase-synchronized with the input signal at a higher speed.

Examples Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows a clock signal reproducing device according to the present invention.

A television composite video signal containing a horizontal synchronizing signal and FP is input from input terminal 1 and sent to frame pulse point detection circuit 2.
and the phase error detection circuit 3. The frame pulse point detection circuit 2 detects the FP in the input composite video signal, further detects the PPP synchronized with the clock signal input via the signal line 4, and sends it to the phase comparison circuit 6. A signal with a horizontal scanning period synchronized with the PPP signal is sent to the phase error detection circuit 3. This signal is a pulse for extracting a phase error signal at a fixed position corresponding to each horizontal scanning period while the phase error detection circuit 3 constantly obtains a phase error in units of sampling clocks. It should be noted that, like the circuit of the conventional example, the circuit of this embodiment is entirely composed of digital circuits, so the frame pulse point detection circuit 29, phase error detection circuit 3, which operates at the sampling clock cycle. N1 counter 6, phase comparison circuit θ, digital low-pass filter 9. The N binary counter 11° frequency detection circuit 12 is all supplied with output clock signals generated by VCOs via the signal line 4.

The phase error detection circuit 3 calculates a value that is twice the signal level of the current sample point of the input composite video signal and a value obtained by adding the signal levels two sample points before and two sample points after the current one. The difference is determined and the frame pulse point detection circuit 3
Only the phase error signal at a predetermined position is sent out by the signal supplied from the controller. This phase error signal is integrated by a digital low-pass filter 9 and fed back to vcos.

On the other hand, a frame pulse point detection circuit 2 extracts a detected PPP signal from the input composite video signal, and an internal PPP signal is generated by an A,N,adic counter 6. A phase comparison circuit 6 determines the phase difference between the two signals. VCOs independent of the above circuits
A signal having a horizontal scanning period, for example, shorter than the frame period, is generated from the clock signal supplied by the N binary counter 11. The frequency detection circuit 12 detects the frequency of the output clock signal generated by the VCO 8, and switches the switch 13 to a until the frequency of the output clock signal enters a frequency range with a certain width around the desired frequency, that is, a second frequency range. The output signal of the N binary counter 11 is selected to be input to the up/down counter 7, and the output signal of the up/down counter 7 is used to control the VCOs.
When the phase difference between the detected FPP and the internal FPP approaches zero and the frequency of the clock signal falls within the second frequency range, the switch 13 is turned to the opposite side b and the output of the phase comparison circuit 6 is controlled. The up/down counter 7 is operated at a frame period using the up/down counter 7.
By controlling the VCOs more precisely using the output signal of , and controlling the phase of the output clock signal, an output clock signal whose phase is synchronized with the input synchronization signal is regenerated and taken out from the output terminal 10.

Effects of the Invention As is clear from the above explanation, according to the present invention, the frequency range during the out-of-synchronization period when the input synchronization signal and the internally generated clock signal are out of synchronization is divided into two, and the speed is increased. By appropriately selecting different processing methods to control the VCO, the speed of recovery from clock signal synchronization can be greatly improved, which has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a clock signal reproducing device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional clock signal generating device. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...Frame pulse point detection circuit, 3...Phase error detection circuit, 6...
...N1 decimal counter, 6...Phase comparison circuit, 7...Up/down counter, 8.
...Voltage controlled oscillator (VCO), 9...
Digital low-pass filter, 10...Output terminal, 11...N binary counter, 12...
- Frequency detection circuit, 13... switch. Name of agent: Patent attorney Toshio Nakao and one other person wI
2 figure

Claims (1)

[Claims] A clock signal reproducing device that generates a basic clock for a signal processing circuit by phase-synchronizing the output signal of an oscillator that oscillates at a clock cycle with a synchronization signal included in a transmitted television video signal. It includes a phase error detection circuit that detects a phase error from the included horizontal synchronization signal, a low-pass filter that integrates this phase error, and a phase-locked loop that includes an oscillator that generates a clock signal whose phase is controlled according to the phase error. With,
The frequency of the clock signal generated by the oscillator is detected by a frequency detection circuit, and when the frequency of the clock signal is outside a predetermined frequency range at a position where the frequency deviates significantly from the desired frequency, the frequency is controlled by the output of the frequency detection circuit. driving the frequency of the clock signal generated by the oscillator to near a desired number of cycles by selecting the output signal of a predetermined first signal generating means that generates a signal with a period shorter than the frame period with a switch formed by the oscillator; Within a predetermined frequency range where the clock frequency is close to a desired frequency, the first frame pulse detected from the input video signal by the switch and the second frame pulse generated from the clock signal by the predetermined second signal generating means are combined. The output signal of the phase comparison circuit which receives the frame pulse as an input is selected, and either one of the output signals of the first signal generating means and the phase comparison circuit and the phase locked loop controls the oscillator. Featured clock signal regeneration device.