JP2723819B2 - Sampling clock recovery device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock regenerating apparatus, and more particularly to a sampling clock regenerating apparatus for sampling a video signal with an asynchronous sampling clock, transmitting the sampled signal, and regenerating the sampling clock on the receiving side.

[0002]

2. Description of the Related Art Generally, when digitally transmitting a video signal such as a television signal, a sampling clock frequency of the video signal is determined so as to be synchronized with a video synchronization signal. On the other hand, the transmission clock frequency of the digital transmission path is often determined in advance by the transmission system, and is independent of the clock frequency of the video synchronization signal. As described above, when the sampling clock frequency of the video signal to be transmitted is different from the transmission clock frequency, the sampling clock frequency of the video signal is faithfully reproduced on the receiving side and matched with the sampling clock frequency of the video signal on the transmission side. There is a need. If they do not match, the video signal cannot be reproduced.

For this reason, for example, in the configuration described in Japanese Patent Application Laid-Open No. 54-51305 published on April 23, 1979, the transmitting side determines the ratio of the clock frequency between the sampling clock and the transmission clock to the frequency. The information is transmitted as information, and the receiving side newly generates frequency information from the ratio of the clock frequency of the sampling clock to the transmission clock, compares the frequency information with the frequency information from the transmitting side, and uses the difference value to generate the sampling clock. Under the control, the sampling clock frequency reproduced on the receiving side is matched with the sampling clock frequency on the transmitting side.

FIG. 5 is a block diagram showing a conventional sampling clock reproducing apparatus.

[0005] Referring to FIG. 5, the conventional sampling clock reproducing apparatus comprises a transmitting section 62 and a receiving section 63.

The transmitting section 62 includes an A / D converter 2 for converting the video input signal 1 into a digital signal, a sampling clock generating circuit 6 for outputting a sampling clock 7 at the timing of the video input signal 1, and an A / D converter. An encoding circuit 4 for outputting an encoded signal 5a obtained by encoding the D output 3, a transmission line clock generating circuit 8 for outputting a transmission clock 9, and a frequency dividing circuit for dividing the transmission clock 9 and outputting a divided clock 11 A circuit 10, a frequency information generating circuit 12 for obtaining a clock frequency ratio from the sampling clock 7 and the frequency-divided clock 11 and outputting it as frequency information 13a, multiplexing the coded signal 5a and the frequency information 13a and outputting transmission data 15 And a multiplexing circuit 14.

[0007] The receiving section 63 includes a transmission line clock recovery circuit 1 for extracting a transmission clock 20 from the transmission data 15.
9, a separation circuit 16 for separating the transmission data 15 into an encoded signal 5b and frequency information 13b, a decoding circuit 17 for decoding the encoded signal 5b and outputting a decoded signal 18, and dividing and dividing the transmission clock 20. A frequency dividing circuit 21 for outputting a frequency-divided clock 22, a sampling clock reproducing circuit 60 for outputting a sampling clock 61, a frequency information generating circuit 25 for outputting frequency information 26 from the sampling clock 61 and the frequency-divided clock 22, , Frequency information 13b separated by the separation circuit 16
And the frequency information 26 output by the frequency information generating circuit 25
And a subtracter 27 that calculates a difference between the subtracter 27 and outputs a difference signal 28,
A D / A converter 31 that D / A converts the decoded signal 18 by a sampling clock 61 and outputs a video output signal 32.

Next, the operation will be described with reference to FIG.

The video input signal 1 input to the transmitting section 62 is
The signal is sampled by the sampling clock 7 that is asynchronous with the transmission clock 9 output from the sampling clock generation circuit 6, converted from an analog signal to a digital signal by the A / D converter 2, and output as an A / D output 3. A / D
The output 3 is encoded by the encoding circuit 4. The transmission clock 9 output from the transmission line clock generation circuit 8 is divided by the frequency dividing circuit 10 and output as the divided clock 11. Here, the frequency division is N when the frequency of the transmission clock is fHz.
Is an integer, and the frequency is (f / N) Hz.

The frequency information generating circuit 12 obtains a clock frequency ratio between the divided clock 11 and the sampling clock 7, and outputs it as frequency information 13a. The multiplexing circuit 14 encodes the encoded signal 5a output from the encoding circuit 4 and the frequency information 1
3a is multiplexed and transmitted as transmission data 15.

The transmission data 15 input to the receiving unit 63 is
The transmission line clock recovery circuit 19 recovers the clock and outputs it as a transmission clock 20. The transmission clock 20 is frequency-divided by the frequency dividing circuit 21 and output to the frequency information generating circuit 25 as the frequency-divided clock 22.

On the other hand, the transmission data 15 is separated into an encoded signal 5b and frequency information 13b by a separation circuit 16 using a transmission clock 20. The separated encoded signal 5b is decoded by the decoding circuit 17 and output as a decoded signal 18.

The frequency information generating circuit 25 outputs frequency information 26 from the sampling clock 61 and the frequency-divided clock 22 output from the sampling clock reproducing circuit 60. The frequency information 26 is the frequency information 1 separated from the transmission data 15.
3b, the difference is obtained by the subtractor 27, and the difference signal 2
8 is output to the sampling clock recovery circuit 60.

Since the frequency information is a clock frequency ratio between the sampling clock and the frequency-divided clock, the frequency information 1
3b and the frequency information 26, the feedback control is performed by the sampling clock recovery circuit 60, the frequency information generation circuit 25, and the subtracter 27 so that the value of the difference signal 28 is minimized. A sampling clock 61 equivalent to the sampling clock 7 can be reproduced.

The decoded signal 18, which is a digital signal, is converted into an analog signal by the D / A converter 31 at the timing of the sampling clock 61 equal to the sampling clock frequency 7 on the transmission side, and is reproduced as a video output signal 32. .

FIG. 6 is a detailed block diagram of the frequency information generating circuit of FIG. Frequency information generating circuits 12 and 25
Comprises a differentiating circuit 33, a counter 35, and a register 37.

FIG. 7 is a time chart showing an example of the operation of the frequency information generating circuit.

Next, the operation will be described with reference to FIGS. 6 and 7, but the description will be made for the frequency information generating circuit 12 on the transmitting side. Since the frequency information generating circuit 25 on the receiving side performs the same operation, the description is omitted. .

The counter 35 counts the sampling clock 7 and takes in a count value 36 output from the counter 35 into a register 37. At this time, the divided clock 11 is differentiated by the differentiating circuit 33. The differentiating operation is performed in synchronization with the rising of the first clock of the sampling clock 7 from the rising of the divided clock 11 from the Low level to the High level,
This is performed by generating the differential pulse 34 which falls from the High level to the Low level and becomes the Low level for one cycle of the sampling clock 7.

The differentiating pulse 34 is output from the differentiating circuit 33 every period of the divided clock 11 and is used as a load signal for the counter 35. During one cycle of the differential pulse 34, the number of clocks of the sampling clock 7 is counted.

The differentiated pulse 34 is used as a latch signal of the register 37, and when the differentiated pulse 34 falls from a high level to a low level, the count value 36 is latched and output as frequency information 13a.

On the receiving side, the frequency information
b is compared with the frequency information 26 on the receiving side for each period of the divided clock 22 by the subtracter 27, and a VCO, which is a voltage-controlled oscillator built in the sampling clock recovery circuit 60, is obtained from the difference signal 28 between the two. (Voltage C
The sampling clock 61 is reproduced by controlling an integrated oscillator (oscillator).

However, when the accuracy of the frequency information on the transmitting side is coarse, the difference signal 28 also has coarse accuracy, and the variation in the frequency ratio of the difference signal 28 becomes coarse due to this roughness.
In order to increase the frequency stability, it is necessary to reduce the gain of the VCO frequency control.

Conversely, even if the accuracy of the frequency information is high, when the fluctuation of the frequency ratio of the difference signal 28 is large, it is necessary to increase the gain of the frequency control of the VCO in order to improve the followability. As one method for this, it is conceivable to control the gain characteristic using a non-linear gain characteristic in which the gain is reduced when the difference signal 28 is small, and the gain is increased as the difference signal 28 increases. When the value is large, it is necessary to consider the characteristics of stabilizing the frequency so as not to cause overshoot and shortening the synchronization pull-in time.

[0025]

The above-mentioned conventional sampling clock recovery apparatus uses a differential value between the transmission-side frequency information and the reception-side frequency information multiplied by a gain and then integrating to obtain a VCO control voltage. Was controlled using a non-linear gain characteristic that makes the gain small when the difference value is small and increases as the difference value increases, but no overshoot occurs when the gain is large. In this way, the gain characteristics must be determined so as to achieve frequency stability and shorten the pull-in time. However, since a gain characteristic that satisfies both the frequency stability and the shortening of the pull-in time cannot be obtained, there is a disadvantage that the sampling clock cannot be stably reproduced with a short pull-in time.

An object of the present invention is to provide a sampling clock reproducing apparatus which reproduces a sampling clock with a stable frequency and a short pull-in time.

[0027]

According to the present invention, there is provided a sampling clock reproducing apparatus which converts an image signal into a digital signal.
A D / D converter; a sampling clock generation circuit for generating a first sampling clock in response to the video signal;
An encoding circuit that outputs an encoded signal obtained by encoding the output of the converter; a transmission line clock generation circuit that outputs a first transmission clock; and a first divided clock that divides the first transmission clock. , A first frequency information generating circuit that outputs a first frequency ratio signal from the first sampling clock and the first frequency-divided clock, and the encoded signal. A multiplexing circuit that outputs a transmission signal multiplexed with the first frequency ratio signal; a transmission line clock regeneration circuit that outputs a second transmission clock from the transmission signal; A separating circuit that separates and outputs the coded signal and the first frequency ratio signal from a decoding circuit that decodes the coded signal and outputs a decoded signal; The second to reproduce the divided clock of 2 A frequency divider, a first sampling clock recovery circuit for outputting a second sampling clock, and a second frequency ratio signal output from the second frequency-divided clock and the second sampling clock. A second frequency information generation circuit, a subtractor that outputs a difference signal between the first frequency ratio signal and the second frequency ratio signal separated by the separation circuit, A receiving unit including: a D / A converter that converts the signal into an analog signal by a sampling clock and outputs the video signal; wherein the receiving unit includes the difference signal and the An average calculating circuit for averaging the difference signal from the second transmission clock and outputting a difference average value signal, wherein the first sampling clock recovery circuit performs a third operation on the basis of the difference average value signal and the difference signal. Sampling Sampling clock reproducing apparatus characterized by being composed of the second sampling clock recovery circuit for outputting a click can be obtained.

Further, there is provided a sampling clock reproducing apparatus characterized in that the average calculating circuit comprises a register, a counter and an adder.

Further, the second sampling clock recovery circuit detects a frequency change of the difference signal, and detects either the difference signal or the difference average value signal according to the magnitude of the frequency change. A selection circuit for selecting and outputting under the control of the frequency change detection circuit; and a D / D converter for converting an output signal of the selection circuit into an analog control signal.
A sampling clock reproducing apparatus is provided, comprising: an A-converter; an integrating circuit for integrating the analog control signal; and a voltage-controlled oscillator for controlling an oscillation frequency by an output signal of the integrating circuit.

[0030]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a sampling clock reproducing apparatus according to the present invention.

The present embodiment shown in FIG. 1 comprises a transmitting section 62 and a receiving section 64.

The transmitting section 62 is the same as the sampling clock recovery apparatus shown in FIG.

The receiving section 64 includes a transmission line clock recovery circuit 19 for extracting the transmission clock 20 from the transmission data 15,
The coded signal 5b and the frequency information 13b from the transmission data 15
A decoding circuit 17 for decoding the encoded signal 5b and outputting a decoded signal 18, and a frequency dividing circuit 21 for dividing the transmission clock 20 and outputting the divided clock 22
A frequency information generating circuit 25 that outputs frequency information 26 from the sampling clock 24 and the frequency-divided clock 22; frequency information 13b separated by the separating circuit 16; and frequency information 26 output by the frequency information generating circuit 25. A subtracter 27 that takes the difference between the two and outputs a difference signal 28, an average calculation circuit 29 that takes an average of the difference signals based on the difference signal 28 and the transmission clock 20 and outputs a difference average value signal 30, A sampling clock recovery circuit 23 for outputting a sampling clock 24 from the difference signal 28;
And a D / A converter 31 that performs D / A conversion on the sampling clock 24 and outputs a video output signal 32.

In the above configuration, the separation circuit 16
, Decoding circuit 17, D / A converter 31, transmission line clock recovery circuit 19, frequency dividing circuit 21, frequency information generating circuit 25, and subtracter 27 are the same as those shown in FIG.
Is the same as the sampling clock recovery device shown in FIG.

Next, the operation will be described in detail.

In FIG. 1, a clock is extracted from a transmission data 15 inputted to a receiving section 64 by a transmission line clock recovery circuit 19 and a transmission clock 20 is output. The transmission clock 20 is frequency-divided by a frequency dividing circuit 21 and a frequency-divided clock 22
To the frequency information generation circuit 25.

On the other hand, the transmission data 15 is separated by the separation circuit 16 into the encoded signal 5b and the frequency information 13b using the transmission clock 20. The separated encoded signal 5b is decoded by the decoding circuit 17 and output as a decoded signal 18.

The frequency information generating circuit 25 outputs frequency information 26 from the sampling clock 24 and the frequency-divided clock 22 output from the sampling clock reproducing circuit 23. The frequency information 26 is the frequency information 1 extracted from the transmission data 15.
3b, the difference is obtained by the subtractor 27, and the difference signal 2
8, the sampling clock recovery circuit 23 and the average calculation circuit 2
9 is output.

The average calculating circuit 29 calculates the average of the difference signal 28 over a predetermined period and outputs a difference average value signal 30. The difference signal 28 and the difference average value signal 30 are input to the sampling clock recovery circuit 23. The sampling clock recovery circuit 23 detects a frequency change from the difference signal 28, selects the difference signal 28 when the frequency change is large, and selects the difference average value signal 30 when the frequency change is small. To generate a sampling clock 24.

The sampling clock 24 is input to the frequency information generation circuit 25 and output to the D / A converter 31. The decoded signal 18 output from the decoding circuit 17 is D / D
The digital signal is converted into an analog signal by the A converter 31 and output as a video output signal 32.

FIG. 2 is a detailed block diagram of the average calculating circuit of FIG.

Referring to FIG. 2, the average calculating circuit 29 comprises an adder 38, a counter 42, a register 40 and a register 44.

The difference signal 28 is added to the addition value output 41 of the register 40 by the adder 38, and re-input to the register 40 as the adder output 39. On the other hand, transmission clock 2
0 counts the counter 42 and outputs the control signal 43 at the time of full counting. The control signal 43 is used as a clock of the register 44 and operates as a divider circuit of the addition value output 41. That is, the difference signal 28 is divided by the number of transmission clocks 20 in a predetermined period, an average value is obtained, and the result is output as a difference average value signal 30.

FIG. 3 is a detailed block diagram of the sampling clock recovery circuit of FIG. 1, and FIG. 4 is a configuration diagram of the frequency change detection circuit of FIG.

The sampling clock recovery circuit 23 includes a selection circuit 45, a D / A converter 49, an integration circuit 51, and a VCO
53 and a frequency change detection circuit 46.

The difference signal 28 is input to the frequency change detection circuit 46. The frequency change detection circuit 46 outputs the difference signal 28
Is larger than a predetermined value, the selection circuit 45 outputs a control signal 47 for selecting the difference signal 28. When the change of the difference signal 28 is smaller than a predetermined value, the selection circuit 45
Outputs a control signal 47 for selecting the difference average value signal 30. The selection output signal 48 output from the selection circuit 45 is
The digital signal is converted into an analog signal by a D / A converter 49 and output to a integrating circuit 51 as a D / A output 50.

An integrating circuit 51 integrates the D / A output 50 and outputs V
It outputs to the VCO 53 as a CO control signal 52. Here, the integrating circuit 51 is used for removing high frequency noise components.

The VCO 53 is a free-running oscillation circuit whose oscillation frequency changes according to the input voltage, and outputs the sampling clock 24 based on the value of the VCO control signal 52.

The operation of the frequency change detection circuit 46 will now be described with reference to FIG.

The frequency change detection circuit 46 includes a register 54
, A subtractor 59, and a comparator 56.

The currently input difference signal 28 and the register 5
4 and the previous difference signal 28 output as a register output 55 is compared by a subtractor 59 and output as a subtractor output 57 to a comparator 56. The comparator 56 selects the control signal 47 for selecting the difference signal 28 when the output 57 of the subtractor is larger than a predetermined threshold value 58, and selects the difference average value signal 30 when the output 57 is smaller than the threshold value 58. The control signal 47 is output.

As described above, the operation of averaging the difference signal 28 is performed, the frequency change of the difference signal 28 is detected, and the difference signal 28 or the difference average value signal 30 is selected according to the magnitude of the frequency change. Control the
The optimally controlled sampling clock 24 can be reproduced.

[0054]

As described above, the sampling clock reproducing apparatus of the present invention obtains the average of the differential signal when the frequency change is small, thereby obtaining the frequency information indicating the clock frequency ratio between the sampling clock and the transmission clock. The accuracy of the differential signal can be increased, the frequency can be stabilized, and the gain characteristics can be determined finely. Therefore, it is possible to configure the frequency characteristics and gain characteristics to shorten the pull-in time so that overshoot does not occur. . In addition, when a large frequency change is detected, a non-linear characteristic that can shorten the pull-in time without increasing the gain characteristic of the VCO can be configured because the difference signal itself is controlled instead of the average of the differential signal. This has the effect of reproducing the sampling clock while stabilizing the frequency with a shorter pull-in time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a sampling clock reproducing apparatus according to the present invention.

FIG. 2 is a detailed block diagram of an average calculation circuit of FIG. 1;

FIG. 3 is a detailed block diagram of a sampling clock recovery circuit of FIG. 1;

FIG. 4 is a configuration diagram of a frequency change detection circuit of FIG. 3;

FIG. 5 is a block diagram showing a conventional sampling clock recovery device.

FIG. 6 is a detailed block diagram of the frequency information generation circuit of FIG. 5;

FIG. 7 is a time chart showing an example of the operation of the frequency information generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video input signal 2 A / D converter 3 A / D output 4 Encoding circuit 5a, 5b Encoding signal 6 Sampling clock generation circuit 7 Sampling clock 8 Transmission line clock generation circuit 9 Transmission clock 10 Frequency dividing circuit 11 minutes Frequency clock 12 Frequency information generating circuit 13a, 13b Frequency information 14 Multiplexing circuit 15 Transmission data 16 Separation circuit 17 Decoding circuit 18 Decoded signal 19 Transmission line clock regeneration circuit 20 Transmission clock 21 Frequency division circuit 22 Frequency division clock 23 Sampling clock regeneration Circuit 24 Sampling clock 25 Frequency information generation circuit 26 Frequency information 27 Subtractor 28 Difference signal 29 Average calculation circuit 30 Difference average value signal 31 D / A converter 32 Video output signal 33 Differentiation circuit 34 Differential pulse 35 Counter 36 Count value 37 Register 38 Adder 39 Adder output 0 register 41 addition value output 42 counter 43 control signal 44 register 45 selection circuit 46 frequency change detection circuit 47 control signal 48 selection output signal 49 D / A converter 50 D / A output 51 integration circuit 52 VCO control signal 53 VCO 54 register 55 Register output 56 Comparator 57 Subtractor output 58 Threshold value 59 Subtractor 60 Sampling clock recovery circuit 61 Sampling clock 62 Transmitter 63 Receiver 64 Receiver

Continuation of front page (56) References JP-A-4-311160 (JP, A) JP-A-4-290306 (JP, A) JP-A-54-51305 (JP, A) JP-A-6-338880 (JP, A) , A) JP-A-2-27432 (JP, A) JP-A-2-30292 (JP, A) JP-A-2-93855 (JP, U)

Claims (3)

(57) [Claims] 1. A method for converting a video signal into a digital signal
/ D converter, a sampling clock generation circuit for generating a first sampling clock in response to the video signal,
An encoding circuit that outputs an encoded signal obtained by encoding the output of the D converter; a transmission line clock generation circuit that outputs a first transmission clock; and a first frequency divider that divides the first transmission clock A first frequency dividing circuit for outputting a clock, a first frequency information generating circuit for outputting a first frequency ratio signal from the first sampling clock and the first divided clock,
Transmitting means including a multiplexing circuit for outputting a transmission signal obtained by multiplexing the coded signal and the first frequency ratio signal;
A transmission line clock recovery circuit that outputs a second transmission clock from the transmission signal; a separation circuit that separates and outputs the encoded signal and the first frequency ratio signal from the transmission signal; A decoding circuit that decodes and outputs a decoded signal; a second frequency divider that divides the second transmission clock to reproduce a second divided clock; and a first circuit that outputs a second sampled clock. A sampling clock recovery circuit, a second frequency information generation circuit that outputs a second frequency ratio signal from the second divided clock and the second sampling clock, and the second frequency information generation circuit that is separated by the separation circuit. A subtractor that outputs a difference signal between a first frequency ratio signal and the second frequency ratio signal; and a D / that converts the decoded signal into an analog signal by the second sampling clock and outputs the video signal. Reception including an A converter And a sampling clock recovery device comprising: a receiving unit configured to average the difference signal from the difference signal and the second transmission clock and output a difference average value signal in addition to the above configuration. Wherein the first sampling clock recovery circuit comprises a second sampling clock recovery circuit for outputting a third sampling clock from the difference average value signal and the difference signal. Clock regeneration device. 2. The sampling clock recovery device according to claim 1, wherein said average calculation circuit comprises a register, a counter, and an adder. 3. A frequency change detection circuit for detecting a frequency change of the difference signal, wherein the second sampling clock recovery circuit detects one of the difference signal and the difference average value signal according to the magnitude of the frequency change. A selection circuit that selects and outputs the signal under the control of the frequency change detection circuit, a D / A converter that converts an output signal of the selection circuit into an analog control signal, an integration circuit that integrates the analog control signal, and the integration circuit 2. The sampling clock reproducing apparatus according to claim 1, further comprising: a voltage controlled oscillator that controls an oscillation frequency according to the output signal.