JPS61167224A - Digital phase locked loop - Google Patents

Abstract

PURPOSE:To keep a stable locking by retarding a pulse train of an input clock signal by a phase adder at an interval of one pulse for a prescribed time and inputting the result to a phase comparator so as to prevent the disturbance of an output clock signal. CONSTITUTION:When an input clock signal S1 is inputted to a T flip-flop 6, the flip-flop 6 is inverted at each trailing of the input clock signal S1. Thus, AND gates 7, 8 are opened at an interval of one pulse, an output pulse S10 of the AND gate 8 becomes a pulse train retarded for a prescribed time, and an output S6 of the phase adding device 5 is an input clock signal S1 retarded by a prescribed time (t) at an interval of one pulse. The phase of a phase adding device output S6 at each pulse at locking to a frequency division signal S3 is led or lagged alternately by t/2 each, then the phase difference is detected accurately by a phase comparator 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital phase-locked circuit that synchronizes with an input clock frequency and generates an output clock frequency that is multiplied by that frequency.

Summary of the Invention The present invention provides a digital phase synchronization circuit that connects a phase comparator, a filter, a voltage controlled oscillator, and a frequency divider in a loop to generate an output clock frequency that is synchronized with an input clock frequency and multiplied by that frequency. In this method, disturbances in the output clock signal during synchronization are removed by inputting to the phase comparator a pulse train in which the input clock is delayed by a certain period of time every other pulse.

BACKGROUND ART Conventionally, as shown in FIG. 4, this type of digital phase-locked circuit has been constructed by loop-connecting a phase comparator 1, a low-pass filter 2, a voltage-controlled oscillator 3, and a frequency divider 4.
An input clock signal 51 is inputted to the voltage controlled oscillator 3 so that it is synchronized with the input clock signal S1 and outputs an output clock signal S2 having a frequency multiplied by the frequency of the input clock signal s1. The phase comparator l receives a frequency-divided signal s obtained by dividing the output clock signal S2 by the frequency divider 4.
3 and the phase of the input clock signal s within a range of ±2π, and outputs a voltage or current proportional to the phase difference as a phase difference signal s4. The control signal ss, which has been smoothed to remove high frequency components, is supplied to the voltage controlled oscillator 3 to control its oscillation frequency. Therefore, by controlling so that the phase difference between the input clock signal s1 and the frequency-divided signal S3 is eliminated, the voltage-controlled oscillator 3 outputs a frequency obtained by multiplying the frequency of the input clock signal S1 by the frequency division ratio of the frequency divider 4. A clock signal is output.

The above-mentioned phase comparator l is configured so that it can also detect frequency differences.
A phase comparator with an operating range of ±2π is used.

Although such a phase comparator generates a phase difference signal with a pulse width proportional to the phase difference, it is not guaranteed that a normal phase difference will be detected when the phase difference becomes small to a certain extent after synchronization is completed. This is because there is a limit to the operating speed of the logic elements that constitute the phase comparator 1. Therefore, the conventional digital phase synchronized circuit has the disadvantage that the output clock signal is disturbed in the synchronized state.

Problems to be Solved by the Invention The purpose of the present invention is to solve the above-mentioned conventional drawbacks and to provide a stable multiplied output without causing disturbance of the output clock signal during synchronization. be.

Composition of the Invention The digital phase synchronized circuit of the present invention has a phase comparator, a filter, a voltage controlled oscillator, and a frequency divider connected in a loop, and synchronizes with a clock signal input to the phase comparator to generate a frequency that is an integral multiple of the clock signal. A digital phase synchronized circuit that transmits a clock signal is provided with a phase adder that delays the input clock signal by a certain period of time every other pulse, and the phase comparator is configured to combine the output pulse of the phase adder and the output of the voltage controlled oscillator. It is characterized by outputting a DC voltage or current proportional to the phase difference of the pulses.

EMBODIMENT OF EMBODIMENT OF THE INVENTION Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, in addition to providing a phase adder 5 that delays the input clock signal S1 by a certain period of time every other pulse, and inputting the phase adder output s6 output from the phase adder 5 to the phase comparator 1. is similar to the conventional example shown in FIG.

FIG. 82 is a block diagram showing a configuration example of the phase adder 5. As shown in FIG. That is, the ant game opened by the T-type flip-flop 6 and the positive output S7 of the T-type flip-flop 6
1.7, an AND gate 8 opened by the inverted output S8 of the T-type flip-flop 6, a delay circuit 9 that delays the output pulse slo of the AND gate 8 for a certain period of time, and an output pulse S9 of the AND gate 7 and the delay. The input clock signal S1 is input to AND gates 7 and 8, and the OR circuit 10 outputs a phase adder output S6.

Now, the input clock signal S1 as shown in FIG. 3(A) is
When input to the T-type flip-flop 6, the T-type flip-flop 6 is inverted every time the input clock signal S] falls. Therefore, the positive output S7 of the T-type flip-flop 6
The +inverted output S8 is as shown in (B) and (C) of the figure, respectively, and the AND gates 7 and 8 are opened every other pulse. Therefore, the output pulse S8 of the AND gate 7 becomes as shown in FIG. 10D, and the output pulse slo of the AND gate 8 becomes as shown in FIG. delay pulse s
ll is a pulse train in which the output pulse slo is delayed by a certain period of time, as shown in FIG. Therefore, the phase adder output S6 is the input clock signal S!, as shown in IN (G). becomes a signal delayed by a certain time t every other pulse. At the time of synchronization, the divided signal S3 matches the average phase of the phase adder output S6, so the phase adder output S
The phase of each pulse of 6 is t/with respect to the frequency divided signal S3.
They will alternately advance or lag in increments of two. The lead or lag phase difference of t/2 is accurately detected by a phase comparator 1, smoothed by a low-pass filter 2 to remove high frequency components, and then supplied to a voltage controlled oscillator 3. That is, in this embodiment, upon completion of synchronization, the phase comparator 1 operates within an operating range in which normal phase difference detection is possible, thereby maintaining stable synchronization and preventing disturbances in the output clock. It has the effect of being able to.

Effects of the Invention As described above, in the present invention, the phase adder delays the pulse train of the input clock signal by a certain period of time every other pulse and inputs it to the phase comparator, so that the phase comparator operates when synchronization is completed. Since it is configured to be able to operate within this range, it has the effect of preventing disturbances in the output clock signal upon completion of synchronization and maintaining stable synchronization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the phase adder of the above embodiment, and FIG. 3 is a time diagram for explaining the operation of the phase adder. FIG. 4 is a block diagram showing an example of a conventional digital phase synchronization circuit. In the figure, 1: phase comparator, 2: low-pass filter,
3: Voltage controlled oscillator, 4: Frequency divider, 5; Phase adder, 6
: T-type flip-flop, 7: AND gate, 8: AND gate, 9: Delay circuit, 10: OR circuit.

Claims (1)

[Claims] Digital phase synchronization in which a phase comparator, a filter, a voltage controlled oscillator, and a frequency divider are connected in a loop, and a frequency that is an integer multiple of the clock signal input to the phase comparator is synchronized with the clock signal. The circuit includes a phase adder that delays the input clock signal for a certain period of time every other pulse, and the phase comparator generates a direct current proportional to the phase difference between the output pulse of the phase adder and the output pulse of the voltage controlled oscillator. A digital phase-locked circuit characterized by outputting voltage or current.