JPH01136417A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent phase fluctuation by time axis correction when an output signal is pull in to the synchronizing stable state by stopping the time axis correction in the synchronizing stable state where the phase of the output signal is deviated in the leading and lagging direction respectively within a prescribed period in a digital phase synchronizing circuit. CONSTITUTION:A delay circuit 15 comprising two stages of delay devices 15a, 15b retarding the frequency division pulse of a frequency division circuit 10 frequency- dividing an oscillated pulse by a prescribed period each and outputting a 1st delay pulse outputted from the pre-stage delay device 15a as an output signal, and 1st and 2nd phase comparator circuits 12, 13 detecting the lead/lag of the phase of a 2nd delay pulse outputted from the frequency division pulse and the delay device 15b of the post-stage with respect to each input signal and outputting the lead/lag auxiliary discrimination signal of the phase of the output signal are provided. Moreover, a phase difference decision circuit 14 is provided which outputs both the decision signals in response to lead/lag selectively to the said counter only when a phase deviation exceeding a prescribed period of the input signal and output signal is detected based on the combination of the presence of each auxiliary discrimination signal. Thus, the time axis correction is stopped when the synchronizing stable state is reached.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronized circuit used for clock reproduction of digital equipment.

[Conventional technology]

Conventionally, in digital signal transmitting/receiving devices, recording/reproducing devices, etc., when receiving or recording, for example, a clock component included in a pulse train signal of transmitted input data is extracted, and a clock pulse synchronized with the clock component is extracted. It is necessary to perform processing such as reception and recording based on the clock pulse.

Therefore, this type of device is provided with a phase-locked circuit, also called a PLL circuit, which forms the clock pulses synchronized with the input signal based on a phase comparison between the input signal and an internally generated signal. There is.

Conventionally, this type of phase-locked circuit has a voltage side a oscillation i.
, loop filters (analog low-pass filters), analog phase comparators, etc. are used to perform analog processing, but in this case, the bandwidth and center frequency of the control loop cannot be easily changed (adjusted), and , a voltage-controlled oscillator, and a low-pass filter, it is easily affected by temperature changes and fluctuations in power supply voltage, resulting in various inconveniences.

Therefore, instead of using the voltage-controlled oscillator, low-pass filter, phase comparator, etc., a digital phase-locked circuit has been proposed that performs digital processing using an oscillator with a fixed oscillation frequency, a 1-frequency divider, a counter, etc. has been done.

By the way, the digital/1/type phase synchronized circuit is described in, for example, the Journal of the Institute of Electronics and Communication Engineers (78/12 Vol 56-ANo.
12), "Binary quantization all-digital phase synchronization system", basically, the phase difference between the input signal (pulse train signal) and the output signal (pulse train signal) is advanced,
In addition to performing binary quantization and detection with a delay, the detection results are reversibly counted and integrated, and each time the integrated value reaches a positive or negative set value, the oscillation pulse of the oscillator is corrected by adding or deleting a pulse, and the oscillation The output signal formed by dividing the pulse is synchronized with the input signal.

The conventional digital phase-locked circuit described in the journal of the Institute of Electronics and Communication Engineers is configured as shown in FIG. That is, an input signal of a square wave pulse train that changes in binary value with an average period Ti based on the clock component is input to the binary phase comparator (3) of the phase comparison block (2a), and the input signal to the comparator (3) is The signal and the output signal of a square wave pulse train outputted from a frequency dividing circuit (to be described later), that is, the output clock pulse, are compared in binary phase, and from the comparator (31) to the counter section 151 of the reversible counter (41), a lead or a delay is determined. A signal 81°b+ is output.

That is, if the output clock pulse rises earlier than the input signal, an advance discrimination signal a1 is output to the counter (4), and conversely, if the output clock pulse rises later than the input signal, a delay discrimination signal b+ is output to the counter section C51. Ru.

The counter section (5) is set to a predetermined initial value N every time it is reset, and counts the discrimination signals a+ and bt in q inversely, adds 1 to the count by inputting the discrimination signal at, and counts by 1 by inputting the discrimination signal hl. Subtract 1 and count.

Furthermore, the count signal of the counter section (5) is determined by the count value judgment section (
61, the counter unit r5) counts N in the increasing and decreasing direction, and when the count value signal reaches 2N and 0, respectively, the determining unit (6) is inputted to the determining unit (6) for determining advance and delay.

(6b) to the time axis control circuit of the control block (7a) (
8), a positive control signal a2 for an insertion command and a negative control signal b2 for a deletion command are output, respectively.

' By the way, the control circuit (81 has a constant period To/(2
The oscillation pulse of the oscillator (9) oscillated by M) is input,
Both control signals a2. bg is not input, the input oscillation pulse is sent directly to the control circuit (8).
is output from.

Then, the control signal a2. bz each is a control circuit (8)
, the control circuit (8) deletes and inserts the oscillation pulse, for example, l pulse, and changes the period of the output pulse from the standard To/(2M) to To/(2M-1) to To/
(2M+1) respectively, performs time axis correction on the oscillation pulse, and reset terminal of the counter section (5) (
rst)/<A/s is output and the counter (4
) to reset.

In order to form a pulse with a period To as a clock pulse, the oscillation bulk output from the control circuit r8) is input to the 2M frequency dividing circuit +10, and the output pulse of the control circuit f81 is divided by 2M by the frequency dividing circuit rIa. At the same time, the frequency divided pulse of the frequency dividing circuit is outputted to the output terminal (Il+) and the comparator (31) as an internally generated clock pulse.

Then, control signals a2 . Formation of b2 and control signal a3h
By one-pulse correction of the phase of the oscillation pulse by z, the output signal of the output terminal Qll is loop-controlled, and the output signal of the input terminal f
Synchronizes with the rise of the i+ input signal.

Note that the number of pulses to be deleted or inserted in order to perform time axis correction may be set according to the amount of correction per time, etc., and the larger the number of pulses, the larger the amount of correction per time.

[Problem that the invention seeks to solve]

By the way, in the case of the conventional digital phase synchronized circuit, the phase lead or delay of the output signal of the output terminal GD, that is, the output clock pulse, with respect to the input signal of the input terminal (1) is detected, and the phase synchronization circuit is based on so-called binary information. Since the phase of the oscillation pulse is corrected by one pulse, that is, by a unit amount, the phase correction by a unit amount is always performed regardless of whether the phase shift amount of the output clock pulse is large or small.

The speed of synchronization pull-in based on phase correction depends on the initial value N of the counter (4), and the smaller N is, the better the responsiveness is.

However, especially when the output clock pulse is almost in phase with the input signal, it appears to be stable and synchronized.

When a state (hereinafter referred to as a stable state) is reached, a unit amount of phase correction becomes an excessive correction. Therefore, if the initial value N is set relatively small to improve responsiveness, excessive correction phase disturbances occur frequently.

Therefore, in the conventional digital phase synchronization circuit, there is a problem that when the synchronization is in a stable state, the output signal has a lot of jitter due to correction, and the output signal becomes unstable.

The present invention has been made with the above-mentioned problems in mind, and its technical object is to prevent phase fluctuations in an output signal in a stable state with a relatively simple configuration.

[Means for solving problems]

Technical means for solving the problem mentioned above will be explained below using FIG. 1 corresponding to the embodiment.

This invention detects a phase shift between an input signal of a pulse train and an output signal formed by frequency-dividing an oscillation pulse of a constant period from an oscillator (9), and selects a signal for determining whether the phase of the output signal is advanced or delayed. At the same time, both the discrimination signals are incremented and decremented by a reversible counter (4), and each time the count value of the counter (41) changes by a certain value in the increasing and decreasing directions, it is counted according to the direction of change. In the digitally controlled phase synchronization circuit, the oscillation puffless circuit performs time axis correction of pulse deletion or pulse insertion on the oscillation pulse, resets the counter (4), and synchronizes the phase of the output signal with the input signal. a frequency divider circuit f'll) that divides the frequency of the frequency divider circuit f'll), a delay circuit 09 that outputs the frequency divided pulse of the frequency divider circuit αO as a delayed signal for a fixed period of time, and the delay circuit (15b) at the subsequent stage of the frequency divided pulse. The phase lead and lag of each of the second delayed pulses outputted from the input signal are detected, and a signal for determining the phase lead and lag of each of the frequency divided pulse and the second delayed pulse is used as a signal for determining the phase lead and lag of the output signal. Go ahead.

The first signal is output as a delay auxiliary discrimination signal. Detecting a phase shift between the input signal ° and the output signal that exceeds the certain period based on the combination of a3 of the second phase comparator circuit α and the presence or absence of each of the auxiliary discrimination signals; The phase difference determination circuit (14) advances only when a phase advance or lag is detected beyond the phase range corresponding to the certain period of time, and selectively outputs both the discrimination signals to the counter according to the lag. Technical measures are being taken.

[Effect]

Therefore, according to the present invention, during a stable synchronization state in which the phase of the output signal deviates within a certain period in the leading direction and the delayed direction, the determining signal is not output from the determining circuit 04, and the counting of the counter (41) is stopped. time axis correction is stopped.

Therefore, when the output signal is brought into a stable synchronization state, phase fluctuations due to time axis correction are prevented, and stable lock playback can be performed.

Since control can be performed only by binary discrimination of lead and lag without measuring the amount of phase difference between the input signal and the output signal, phase fluctuations in the output signal can be prevented with a simple configuration, which can solve technical problems. is resolved.

〔Example〕

Next, the present invention will be explained in detail with reference to FIGS. 1 and 2 showing one embodiment thereof.

FIG. 1 shows the case where one pulse is deleted or inserted. In the same figure, the same symbols as in FIG.
The phase comparison block and control block (2) and αa provided in place of a) and (7m) are the first . In the second phase comparison circuit, the input signal 8a and the frequency division pulse Sb of the frequency division circuit α0.

It consists of a binary phase comparator that determines the phase lead or lag of each input signal 8a of the second delayed pulse Sd output from the delay device at the latter stage of the delay circuit described below, and determines the phase lead or lag of the frequency-divided pulse sb. Discrimination signals ao, bo, second
A signal ao' for determining whether the phase of the delayed pulse Sd is advanced or delayed;
bo' is the output signal of the output terminal aG, that is, the phase advance of the output clock pulse.

Output as a delay auxiliary discrimination signal.

α is a phase difference judgment circuit to which the discrimination signals ao, bo, ao', bo' are input;
, bo', the phase of the output clock pulse advances, and only when it deviates by more than a certain period set in each lag direction, it advances in accordance with the direction of the lag, and a lag discrimination signal is generated. Selectively counter a+ and b+ (4
).

a9 delays the frequency divided pulse sb on the frequency dividing circuit surface by twice the fixed period a (δ=KTo/(2M)) in which the period of the oscillation pulse of the oscillator [9] (=TO/(2M)) is the unit. There are two delay circuits that delay by δ for a certain period of time (
15B).

(15b) consists of a cascade circuit, and the preceding stage delay device (15a
) is output as an output clock pulse to the output terminal OD, and the second delay bus 8d output from the subsequent delay device (15b) is supplied to the phase comparator circuit a3. .

In this embodiment, the fixed period δ is set to one cycle of the oscillation pulse (=To/(2M)), and the delay device (15a).

(15b) are each formed of a D-type flip-flop.

Furthermore, for the sake of simplicity, To=Ti is set.

Then, the average frequency '(=1/Ti
) input signal 8a for each square wave pulse is sent to the phase comparator circuit (2
).

At the same time, the oscillation pulse of the square wave pulse train with a constant frequency of 2Mf from the oscillator (9) is input to the control circuit (8).
The pulse obtained by dividing the oscillation pulse by 2M, that is, the period of the input signal 8a, is input to the frequency dividing circuit αO from the frequency dividing circuit aG to the data input terminal (d) of the delay device (15B). A frequency-divided pulse sb shown in is output. In addition, flI and L in FIG. 2 1a) to 1(j) indicate high level and low level.

At this time, an oscillation pulse is supplied to the clock terminal (ck) of the delay device (15a), (t5b), and the delay device (15a)
, (15b) each one period of the oscillation pulse 1/(
2Mf) (=Ti/(2M)), the phase of the frequency-divided pulse sb is delayed by δ using a delay device (15B) to obtain the first delayed pulse in FIG. 2(e). 8c is formed, and the delay device (15b) causes the first
I/; x, in which the phase of the delayed pulse 8c is delayed by δ;
That is, as shown in FIG. 3D, a second delayed pulse 8d is formed by delaying the phase of the frequency-divided pulse 8b by 2δ (-Ti7M).

Then, the first delayed pulse 8c is outputted to the output terminal 011 as an output clock pulse, and the divided pulse S
c, the second delayed pulse Sd is connected to the phase comparator circuit υ.

03 respectively.

Further, the phase comparator circuit α3 generates a frequency divided pulse Sb and a second delayed pulse S based on the rising edge of the input signal 8a.
The lead or lag of d is detected, and at this time, the phase comparator circuit (
2) outputs a high-level discrimination signal aO consisting of the frequency-divided pulse 8b when the frequency-divided pulse sb rises before the input signal 8a and outputs a high-level discrimination signal aO when the frequency-divided pulse sb rises before the input signal 8a; When detecting the rising delay, the divided pulse s
Similarly, the phase comparator circuit α3 outputs a high-level discrimination signal bO consisting of the input signal Sa, and similarly outputs the second delay pulse Sd when the second delay pulse Sd rises earlier than the input signal Sa.
It outputs a high-level discrimination signal ao' consisting of the second delayed pulse Sd, and outputs a high-level discrimination signal bo' consisting of the second delayed pulse Sd when a delay is detected when the second delayed pulse Sd rises with the input signal 8a. .

When the input signal 8a, the frequency-divided pulse Sb, and the second delay pulse 8d become respectively (at, (b), (dD) in FIG.
), outputted at the timing shown in (g), and the discrimination signal b
o and bo' are output at the timing shown in the figure).

By the way, No. 1. Although the second delayed pulses Sc and Sd always rise with a delay of 2.delta. from the frequency-divided pulse sb, the phase relationship of the frequency-divided pulse 8b with the asynchronous output signal Sa is unstable.

Then, the discrimination signals ao, bo, ao', bo
' is selectively output, and when the divided pulse sb is advanced in phase by 2I or less, the second delay pulse Sd is always delayed in phase and the discrimination signals ao and bo' are output, and the divided pulse When sb becomes an advanced phase exceeding 2δ, the discrimination signal ao and the discrimination signal ao' or bo are determined according to the amount of advance.
' is output and when the divided pulse sb has a delayed phase exceeding 2δ, the second delayed pulse sb also necessarily has a delayed phase and the discrimination signals bo and bo' are output.

On the other hand, in order to use the first delayed pulse Sc as an output signal, the first
It is necessary to synchronize the delayed pulse 8c with the input signal Sa.

Since the first delayed pulse Sc lags the frequency-divided pulse sb by i, when the first delayed pulse Sc is synchronized with the input signal 8g, the frequency-divided pulse Sc advances in phase and the second delayed pulse Sd lags. Be in phase.

Then, as mentioned above, the range where the divided pulse sb advances in phase by 2δ or less, that is, the first delayed pulse Se is δ
Assuming that the range of ±δ in which the signal advances and lags by 0 is the range of stable synchronization state, the output signal, that is, the It is possible to determine whether the phase of the one-delayed pulse Sc is advanced or delayed.

Note that H and L in the table correspond to the presence and absence of a signal.

Therefore, the determination circuit α4 outputs the determination signals an, bo, ao',
Based on the combination of presence and absence (H, L) of bo', a lead or delay exceeding ±δ of the first delay pulse Sc is detected, and the discrimination signals ao and ao' become high level at the same time.
When detecting the presence of o and ao' and when detecting the presence of the discriminating signals bo and ao' in which the discriminating signals bo and ao' become high at the same time, that is, when detecting a lead of 6 or more, the discriminating signal a1 is output to the counter section (51). In addition, the discrimination signals ha, bo'
When detecting the presence of the discrimination signals bo and ho' which become high level at the same time.

That is, when a delay of 6 or more is detected, the discrimination signal b+ is output to the counter section f51.

On the other hand, when the presence of the discrimination signals ao and bo' in which the discrimination ports fao and bo' become high level at the same time is detected, that is, when a lead or a delay within ±δ is detected, at this time the first delay pulse Sc is almost equal to the input signal S8. Since the phase of the output signal of the output terminal 0D is almost synchronized with the input signal Sa and enters a so-called stable state, the determination circuit α inhibits the output of the determination signals a+ and h+.

Based on the operation of the counter section C3)9 determination section (6), the counter (4) receives the determination signal at as in the conventional case.

bl is input eight times, and each time the count value signal reaches 2N and 0, the control signal a2. b2 each control circuit +
81, and at this time, the control circuit f81 outputs the control signal a2. Delete l pulse from oscillation pulse by inputting bz,
In addition to performing time axis correction for each pulse insertion, a reset pulse is output to the counter section C51 and the counter (
4) Reset.

Furthermore, based on the time axis correction of the control circuit (8), one pulse of the high level period of the divided pulse sb is deleted.

Changes to long and short depending on insertion, xth, l/rt
2 delay'<0 where the phase of Se and Sd is corrected by one period Ti of the oscillation pulse in the opposite direction to the direction in which it is detected, the divided pulses sb and 1a second delay pulse 8c
, 8d becomes a pulse with a duty of -50%.

Also, M=8. , N72, each pulse 8b,
The length of the regular high level and low level periods 8c and 8d is 8 cycles of the oscillation pulses shown by squares in each of FIGS. 2(b) to 2(d).

Then, as shown in FIGS. 2(a) and (b), the input signal 8
When the divided pulse sb has a delayed phase with respect to a, the judgment signals a+ and bt of the judgment circuit α4 are as shown in (i) and (j) in the same figure.
At this time, since N=2, the first
During the asynchronous state until the phase shift of the delayed pulse Se becomes within ±δ, time axis correction is performed by inserting one pulse every time the count value of the counter section r51 shown in FIG.
The high-level period length of each pulse 8b, Sc, and Sd is shortened to approximately 7 periods of the oscillation pulse as shown in (Cb), ((3), and ■ in (d) in the same figure. k)
■、■.

■ indicates the count value of the counter section (51).Furthermore, due to the repeating of the time axis correction, the phase shift of the first delayed pulse SC is within ±δ, and when the synchronization stable state is reached, at this time, When the discrimination signals a+ and bt are no longer output, the counter unit [5] stops counting and no time axis correction is performed.

Then, when the phase shift of the first delay path Be exceeds ±δ again, time axis correction is performed in the same manner as described above.

Therefore, the output terminal OD consisting of the first delayed pulse SC
During the synchronized stable state in which the phase shift of the output signal of the input signal 8a is within ±1 set by the delay time of the delay circuit α0, time axis correction is not performed, and the output signal due to the time axis correction is This prevents the phase disturbance of the signal and enables stable reproduction and formation of the clock signal IL/-.

In addition, if δ is set to a minute amount corresponding to one period of the oscillation pulse as in the example, the output signal after being drawn into a synchronous stable state will be stably maintained at the center frequency without fluctuations due to jitter etc., and it will be possible to achieve high accuracy. It is possible to reproduce and form clock pulses.

Then, without measuring the amount of phase difference between the input signal Sa and the output signal, the lead and lag of the input signals of the pulses 8b and Sd, which are ahead and behind the output signal by δ, are determined in binary terms. Since the control is carried out by using a simple configuration, good control can be achieved.

Moreover, a pulse signal with a duty of 50% is outputted as an output signal based on the frequency division of the frequency dividing circuit αO, regardless of the duty of the input signal 8a and the oscillation pulse.
Another advantage is that a clock pulse with a duty of -50% can be easily obtained.

Note that the number of pulses to be deleted or inserted at one time can of course be set arbitrarily; for example, one pulse may be deleted or inserted for each oscillation pulse (DI same period high level, low level TVF double pulse).

Furthermore, it is of course possible to variably set the delay amounts of the delay devices (15a) and (15b) and to arbitrarily set the above-mentioned δ.

Furthermore, it goes without saying that the periods Ti, To, constants M, N, etc. may be set arbitrarily.

〔Effect of the invention〕

As described above, according to the phase locked circuit of the present invention, the phase shift in the lead and lag directions of the output signal is within a certain amount,
When the synchronization stable state is reached, time base correction is stopped and
A stable output signal synchronized with the input signal can be obtained,
When digitally synchronizing an output signal with an input signal, control performance can be easily improved without measuring the amount of phase shift.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of one embodiment of the phase-locked circuit of the present invention, Fig. 2 (a) to tentative) are timing charts for explaining the operation of Fig. 1, and Fig. 3 is a block diagram of a conventional phase-locked circuit. It is a diagram. +11...Input terminal, (4)...Reversible counter, [
8)...Time axis control circuit, (9)...Oscillator, αG
...Frequency divider circuit, 0υ...output terminal, α2. (To)・
...First. Second phase comparison circuit, a4... Phase difference determination circuit, 115... Delay circuit, (15a), (15b).
...Delay device.

Claims (1)

[Claims] (1) Detecting the phase shift between the input signal of the pulse train and the output signal formed by dividing the oscillation pulse of a constant period of the oscillator, and selectively forming a signal for determining whether the phase of the output signal is advanced or delayed. At the same time, both the discrimination signals are incremented or decremented by a reversible counter, and each time the counted value of the counter changes by a certain value in the increasing or decreasing direction, a pulse is deleted or a pulse is added to the oscillation pulse depending on the direction of change. A digitally controlled phase synchronization circuit that performs insertion time axis correction, resets the counter, and synchronizes the phase of the output signal with the input signal, comprising: a frequency dividing circuit that divides the frequency of the oscillation pulse; a delay circuit comprising a two-stage delay device that delays the frequency-divided pulse of the circuit by a certain period of time, and outputs the first delayed pulse outputted from the previous-stage delay device as the output signal; The second output from the delay device
The phase lead or lag of each delayed pulse with respect to the input signal is detected, and the phase lead or lag discrimination signal of each of the frequency divided pulse and the second delayed pulse is used for auxiliary discrimination of the phase lead or lag of the output signal. The first output as a signal
, a second phase comparison circuit, detecting a phase shift between the input signal and the output signal that exceeds the fixed period based on the combination of presence or absence of each of the auxiliary discrimination signals, and detecting a phase shift exceeding the fixed period of time of the output signal; Phase synchronization characterized by comprising: a phase difference determination circuit that advances only when a lead or lag is detected beyond a phase range corresponding to a period, and selectively outputs both of the discrimination signals to the counter according to the lag. circuit.