JPS60251741A - Identification circuit - Google Patents

Abstract

PURPOSE:To reduce the effect of an input signal due to jitter by increasing/decreasing a clock frequency-divided by a digital phase synchronizing circuit so that the leading of an identification clock is located at the center of an input signal pulse. CONSTITUTION:An input signal (a) is fed to differentiation circuits 1, 2, which detects the change in the rising/falling is detected and a short pulse is transmitted to FFs 3, 4. An identification clock (d) is fed to the FFs 3, 4, to output a pulse (b) from the leading of the input signal (a) to the leading of a clock (d) and outputs a pulse (c) from the leading of the clock (d) to the trailing of the input signal (a). Counters 5, 6 count a pulse from an oscillator 8 during that time and the pulse is compared by a comparator 7. A clock control circuit increases/ decreases the pulse fed to a frequency divider 10 through the result of comparison to control the timing of the identification clock (d). Then the result is fed to a D-FF11 together with the input signal (a). Since the signal is identified always at the center position of the input signal, the jitter in the identified output is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a circuit for identifying an input digital signal by means of an internal clock, and particularly to a circuit for identifying an input digital signal using an internal clock. This paper relates to improvements to the identification circuit used.

Conventional technology and problems An identification circuit that uses a DPLL to generate a clock (retiming clock) synchronized with an input signal and identifies the input digital signal using this clock to determine the timing of the input digital signal is used in digital communications, etc. It is widely used in the field of

In the conventional identification circuit using DPLL fir, D
The PLL differentiates the rising or falling edge of an input digital signal pulse to generate a differential pulse, and uses this differential pulse to synchronize with the DPLL f input signal. Therefore, if there is jitter in the input signal pulse and there are fluctuations in its rising or falling position, the DPL
The clock generated by L also has jitter, so it is inevitable that the output signal generated after identification will also have jitter.Objective of the InventionThe present invention aims to solve these problems of the prior art. The purpose of this is to use a DPLL to generate a clock synchronized with an input signal, and use this clock to identify a human-powered digital signal, so that even if there is jitter in the human-powered signal, it will be identified. An object of the present invention is to provide an identification circuit that can reduce jitter in an output signal.

Structure of the Invention The identification circuit of the present invention includes a DPLL that generates an identification clock by frequency dividing the clock of an oscillator. a first counting means for counting the time from the rising edge of the identification clock to the falling edge of the input signal; a second counting means for counting the time from the rising edge of the identification clock to the falling edge of the input signal; The clock frequency divided by the DPLL f2 is decreased or increased by a certain value depending on the magnitude of the count value of the counting means.

Embodiment of the Invention FIG. 1 shows the configuration of an embodiment of the identification circuit of the invention. In the figure, 1 and 2 are differentiating circuits, and 3 and 4 are set-reset flip-flops (hereinafter abbreviated as F and F).
, 5.6 is a counter, 7 is a comparison circuit, 8 is an oscillator, 9 is a clock control circuit, 1° is a frequency dividing circuit (1/A'), 11
is a D type flip-flop (hereinafter abbreviated as F, F).

FIG. 2 is a time chart showing the relationship between the signals of each part in the circuit of FIG. 1, where α is the input signal, b and c are the output signals of F, F5, and F4, respectively, and d is the timing clock. , these signals are first
Its position is also shown in the figure.

In FIG. 1, an input signal α is applied to differentiating circuits 1 and 2, which differentiate the rising and falling changes of the input signal α, respectively, to generate short pulses. F, F5 are differentiator circuits. The output of □1 is applied to the set input, and the output of the frequency divider circuit 10 is applied to the 9 sets. Therefore, F, F3 are applied to the rising edge of the input signal as shown in Figure 2. It generates a pulse that rises at the rising edge of the retiming clock d and falls at the rising edge of the retiming clock d. Furthermore, F and F4 are set at the rising edge of the retiming clock d, and are added to the output f reset input of the differentiating circuit 2. Therefore, F and F4 are set at the rising edge of the retiming clock d, as shown in Figure 2C. Generates a pulse that rises at the rising edge of the human input signal and falls at the rising edge of the human input signal. The counters 5 and 6 have the output of the oscillator 8 added to the tarok input, and the outputs of the counters 5 and 6 are F and F3, respectively.
, F, F 4 outputs are added to the control input,
Therefore, the counter 5 counts the number of clock pulses rL1 of the oscillator 8 corresponding to the period from the rising edge of the human input signal to the rising edge of the timing clock, and the counter 6 counts the number rL1 of clock pulses of the oscillator 8 corresponding to the period from the rising edge of the human input signal to the falling edge of the human input signal. The number n2 of clock pulses of the corresponding oscillator 8 is counted.

In this case, it goes without saying that the speed of the clock generated by the oscillator 8 needs to be sufficiently higher than the speed of the input signal a. Comparison circuit 7 compares count value rLl and n2, and when n,>n2, a first signal output is generated, and yL
+ (Generates the second signal output when rL2, and generates the third signal output when r,=ru,.

On the other hand, in addition to being supplied to the counters 5 and 6 as described above, the clock output of the oscillator 8 is also supplied to the frequency dividing circuit 9 via the clock control circuit 9, where it is divided into 1/N, and the retiming clock b occurs. At this time, when the clock control circuit 9 receives the first signal output from the comparison circuit 7, it inhibits one bit of the clock from the oscillator 8, and the second
When it receives the signal pressure from the oscillator 8, it adds one extra bit to the clock from the oscillator 8, and when it receives the third signal output, it makes no change to the clock from the oscillator 8. Therefore, the rising edge of the retiming clock b is the human input signal α
When the retiming clock h is behind the center position A of the human input signal α, the period of the retiming clock h becomes shorter and the rise of the retiming clock b gradually advances; conversely, the rise of the retiming clock b is ahead of the center position A of the human signal When there is 9
The cycle of timing clock h becomes longer and the rise of retiming clock b gradually lags by C1, and when the rise of retiming clock b coincides with the center position of input signal α, the rise of retiming clock b reaches that position. Retained. In this way, the rise of the retiming clock b always follows the center position of the input signal α.

D-F, Fll has the retiming clock b of the frequency divider circuit 10 applied to its clock input, and the input signal α is applied to its data input, thereby identifying the input signal at its center position and generating an output signal. do. In this way, in the identification circuit C2 of FIG. 1, the input signal α is always identified at its central position.

The retiming clock b of the frequency dividing circuit 10 is outputted to the outside as a clock signal CLK and used for other purposes.

As described in detail, according to the identification circuit of the present invention, the DPL L that generates the identification clock is controlled so that identification is always performed at the center position of the input signal. Compared to a conventional identification circuit that synchronizes the DPLL in the downstream, jitter in the identification output can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the identification circuit of the present invention;
FIG. 2 is a time chart showing signals of various parts in the circuit of FIG. 1.2... Differential circuit, 6.4... Set-reset flip-flop (FJ'), 5, 6... Kawanta,
7... Comparison circuit, 8... Oscillator, 9... Clock control circuit, 10... Frequency dividing circuit (1/A/), 11...
・D type flip-flop (D-F, F) Patent applicant Fujitsu Limited

Claims (1)

[Claims] In an identification circuit that includes a digital phase-locked circuit (hereinafter referred to as DPLL) that divides the frequency of an oscillator clock to generate an identification clock, and that identifies an input signal using the identification clock, the identification is performed from the rising edge of the input signal. a first counting means for counting the time from the rising edge of the identification clock to the falling edge of the input signal; a second counting means for counting the time from the rising edge of the identification clock to the falling edge of the input signal; An identification circuit characterized in that the clock frequency-divided in the DPLL is decreased or increased by a certain value depending on the magnitude (1) of the numerical value and the count value of the second stealth counting means.