JPS62242420A - Digital phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To suppress vibration without using a rapid clock and to instantaneously acquire synchronizm by outputting a phase synchronizing signal with F Hz frequency based on an input digital signal sent at the speed of F bits per second. CONSTITUTION:An oscillation circuit 11 oscillates a signal with F(R+M+1) Hz frequency and a frequency dividing circuit 1A divides the signal into 1/(R+M+1+ or -K) frequency and outputs a phase signal. On the other hand, a phase comparator 3 detects a phase difference between an input digital signal and the phase synchronizing signal outputted from the circuit 1A and outputs a phase advance pulse or a phase delay pulse to a control circuit 5 in accordance with the phase difference. Based on the phase advance pulse or the phase delay pulse, the control circuit 5 controls the value of K in the circuit 1A as '0' or '1'. At that time, a protection circuit 1B acts so as to load the circuit 1A when phase variation with a prescribed level is generated in the input digital signal by the prescribed number of times.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital phase synchronization circuit that outputs a phase synchronization signal of frequency FH2 based on an input digital signal sent at a rate of F bits per second.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional digital phase synchronization circuit. In the figure, 1 is an input terminal for inputting an input digital signal sent at a rate of F bits per second, and 11 is an F bits per second input terminal.
A fixed frequency oscillator that generates a frequency of H2, 2 a phase comparator that compares and detects the phase difference between the input digital signal input to input terminal 1 and the phase synchronization signal, and 4 a signal sent from phase comparator 2. A loop filter 13 outputs a phase-delayed control signal or a phase-advanced control signal based on the phase difference comparison signal; 8 is a frequency dividing circuit consisting of a counter that divides the frequency of the pulse train from the pulse addition/removal circuit and outputs a phase synchronization signal; 12 is a frequency dividing circuit; This is an output terminal for taking out the phase synchronization signal output from the circuit 8.

Next, the operation of the above configuration example will be explained based on the time chart of each part shown in FIG.

The input digital signal 201 input to the input terminal is compared with the phase synchronization signal 205 by the phase comparator 2, and if the phase of the phase synchronization signal 205 is ahead of the input digital signal 201, the phase comparator 2 enters the loop. One phase lead pulse is output to the filter 4.

Also, compared to the input digital signal 201, the phase synchronization signal 2
When the phase of 05 is delayed, the phase comparator 2 outputs one phase-delayed pulse to the loop filter 4.

Here, the loop filter 4 is constituted by a counter capable of counting up to 2N, and is initially reset to the median value N. And a count amplifier for the phase advance pulse input of the phase comparator 2.

When the countdown state for the phase lag pulse reaches 2N or O, the phase lag control signal 202 or phase advance control signal 20 is output as the output of the loop filter 4.
3 is output to the pulse addition/removal circuit 8, reset to N again, and the same operation is repeated.

The pulse addition/removal circuit 8 receives the phase delay control signal 202.
Alternatively, according to the phase advance control signal 203, a part of the pulse train is added to or removed from the output pulse train output from the fixed frequency oscillator 11, and the result is outputted to the frequency dividing circuit 8 as the clock input 204.

The frequency dividing circuit 8 divides the frequency of the clock input 204 and outputs a phase synchronization signal 205 in which phase fluctuations are suppressed.

[Problem that the invention seeks to solve]

Conventional digital phase-locked circuits are configured as described above, so it is necessary to use a high-speed clock to suppress phase fluctuations, and when the phase difference is large, a corresponding phase control signal is required. Therefore, there were problems such as it took time to pull in synchronization.

This invention was made to solve the above-mentioned problems, and it is possible to suppress fluctuations and instantly obtain synchronization without using a high-speed clock. On the other hand, it is an object of the present invention to obtain a digital phase synchronization circuit that is difficult to lose phase synchronization.

[Means for solving problems]

Therefore, the digital phase synchronization circuit according to the present invention has the following characteristics:
F, R, and M are arbitrary numbers, and when K is a number of 0 or 1, the oscillation circuit 11 that oscillates a signal with a frequency of F (R + M + 1) HZ, and the F (R + M + 1) from the oscillation circuit 11
a (R+M+1±K) base frequency divider circuit IA that divides a Hz signal; a phase comparator 3 that compares the phase difference between the input digital signal and the phase synchronization signal output from the frequency divider circuit IA; a control circuit 5 that controls the value of K in the frequency divider circuit IA to change the frequency division ratio of the frequency divider circuit IA based on the phase lead pulse and the phase lag pulse output from the phase comparator; The present invention is characterized by comprising a protection circuit IB that loads the frequency divider circuit IA when a phase fluctuation of a predetermined magnitude occurs in the digital signal a predetermined number of times.

[Effect]

The oscillation circuit 11 according to the present invention has a frequency F (R0M+
1) A signal of HZ is oscillated, and the frequency dividing circuit IA converts the signal of frequency F (R+M+1) oscillated from this oscillation circuit to
+M+1±K) and outputs a phase synchronization signal.

On the other hand, the phase comparator 3 receives the input digital signal and the frequency dividing circuit I.
A phase difference with the phase synchronization signal output from A is detected, and a phase lead pulse or a phase delay pulse is output to the control circuit 3 according to this phase difference.

The control circuit 3 controls the value of K in the frequency dividing circuit IA to 0 or l based on the phase lead pulse and the phase lead pulse.

At this time, the protection circuit IB acts to load the frequency divider circuit IA when a phase fluctuation of a predetermined magnitude occurs in the input digital signal a predetermined number of times.

〔Example] An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an input terminal for inputting an input digital signal sent at a rate of F bits per second, and 11 is an input terminal with a frequency of F (R+M
+1) An oscillation circuit that oscillates a HZ pulse signal, 2 detects the rise or fall of the input digital signal input to input terminal 1, and has a width of 1/F (R+M+1)
An edge detection circuit that generates pulses of less than a second; 8 is an R-adic counter that outputs one carry pulse when it counts eight pulse signals oscillated from the oscillation circuit 11; 10 is a pulse from the oscillation circuit 11; Input the carry pulse of counter 8 using the signal as a shift clock (2M+1)
Bit shift register 9 uses the carry pulse of counter 8 as the reset terminal, and (2M+1) of shift register 10
) is a flip-flop which inputs the bit shift output to the set terminal; 6 is an AND gate which inputs the output of the edge detection circuit 2 and the output of the flip-flop 9; and outputs the logical sum; 3 is the output of the edge detection circuit 2; shift register l
A phase comparator 4 compares the phases of the input digital signal and the phase synchronization signal by inputting the output from O and outputs a phase lead pulse or a phase lag pulse based on the lead or lag of the phase. It is composed of a counter that can count up to 2N, and is initially reset to the median value N, and when the count amplifier for the phase lead pulse and the countdown for the phase delay pulse reach 2N or 0. , a loop filter called a random walk filter that outputs a phase delay control signal or a phase advance control signal, is reset to N again, and repeats the same operation; 5 is a phase advance control signal or phase delay control from the loop filter 4; Follow the signal
In the shift register IO, the carry pulse of the counter 8 is set to (M+1±K) bits (K is O or L).
A control circuit 7 controls the shift, and 7 inputs the output of the AND gate 6 and the output from the shift register IO.
The OR gate IB is a protection circuit that loads the frequency divider circuit when a phase fluctuation of a predetermined magnitude occurs in the input digital signal a predetermined number of times.

Here, the R-adic counter 8 and the shift register 10 are (R+
M+1:tK) base frequency divider circuit IA is configured.

Next, the operation of the present invention configured as described above will be explained based on the time chart shown in FIG.

When an input digital signal 101 sent at a rate of F bits per second is input to the input terminal 1, when the output of this input digital signal 101 is logic 0, the input terminal 1 is configured with an R-adic counter 8 and a shift register IO. Frequency divider circuit IA and NOR
The loop of the gate 7 performs (R+M+1) frequency division, and the frequency F (R+M
+1) A signal with a frequency FH2 obtained by dividing HZ by 1/(R+M+1) is output.

On the other hand, the edge detection circuit 2 receives the input digital signal 101
The edge detection pulse 102 is output by detecting the rising edge of .

Further, the carry pulse 104 output from the counter 8 resets the flip-flop 9, and the carry pulse 104
The output 103 of the shift register 10 which has been shifted by (2M+1) bits sets the flip-flop 9, so that the flip-flop 9 outputs an inverted output pulse 105.

At this time, when the inverted output pulse 105 is a logic 0, the AND gate 6 outputs an output pulse that passes the edge detection pulse 102 from the edge detection circuit 2 and allows the counter 8 to be directly loaded.

Further, when the inverted output pulse 105 is logic 1, the phase comparator 3 compares the phase of the edge detection pulse 102 from the edge detection circuit 2 and the phase synchronization signal 108, and determines whether the phases match, lead, or lag. The pulse is quantized into a phase lead pulse or a phase delay pulse and sent to the loop filter 4.

Loop filter (so-called random walk filter)
Then, in order to remove noise, integration is performed and the control circuit 5
A phase lead control signal 106 or a phase delay control signal 107 is sent to
bit (R=0, l or -1) and outputs the phase synchronization signal 108 to the output terminal 12.

Therefore, the protection circuit IB has AND gates 6 and N.

The edge detection output pulse 1 is arranged between the R gate 7 and output from the edge detection circuit 2.
02, for example, a time dividing circuit in which there is a large phase fluctuation a predetermined number of times such that the inverted output pulse 105 output from the flip-flop 9 is output as a logic 0, such as the edge detection output pulse 110 or the edge detection output pulse 120. Direct loading of the counter 8 making up the IA is possible.

As shown in FIG. 3, this protection circuit IB includes an A-adic counter 16 that counts the edge detection output passing through an AND gate every time an edge is detected, a flip-flop 17 that is set when an edge is detected A times in a row, and a flip-flop 17 that is set when an edge is detected A times in a row.
The normal rotation output is the first input, and the second input is the AND gate 6.
and an AND gate 18 which outputs the output from the AND gate 18.

Therefore, the edge detection pulse 102 is applied to the A-adic counter 16.
When input, the A-adic counter 16 counts the edge detection pulses 102, and outputs a set signal to the flip-flop 17 when a predetermined number A of edge detection pulses have been counted. This cent signal causes the flip-flop 17 to
The normal output of opens the gate of AND gate 18, and
The output of gate 6 is input to NOR gate 7 via AND gate 18.

Then, the signal output from the NOR gate 7 is sent to the counter 8.
It is possible to load .

〔Effect of the invention〕

As explained above, the present invention provides frequency F(R+M+
1) An oscillation circuit that oscillates a HZ signal, and a frequency division of the F (R+M+1)HZ signal from the oscillation circuit (R+M+1
±K) base frequency divider circuit, a phase comparator that compares the phase difference between the human input digital signal and the phase synchronization signal output from the frequency divider circuit, and a phase lead pulse output from the phase comparator and a phase lead pulse output from the phase comparator. a control circuit that controls the value of K in the frequency divider circuit based on the phase delay pulse to change the frequency division ratio of the frequency divider circuit; and a control circuit that changes the frequency division ratio of the frequency divider circuit based on the phase delay pulse; Since it is equipped with a protection circuit that loads the frequency divider circuit above, it is possible to sufficiently suppress phase fluctuations, and it is possible to quickly acquire synchronization. A phase-locked circuit that is unlikely to lose phase lock can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital phase synchronization circuit according to an embodiment of the present invention, FIG. 2 is a time chart for an embodiment of the present invention, FIG. 3 is a detailed configuration diagram of a protection circuit, and FIG. Conventional digital phase synchronization circuit block diagram,
FIG. 5 is a time chart of a conventional digital phase synchronization circuit. 1... Input terminal, 2... Edge detection circuit, 3...
Phase comparator, 4... Loop filter, 5... Control circuit, 6... AND gate, 7... NOR gate, 8
...Counter, 9...Flip-flop, 10...
- Shift register, 11... Oscillator, 12... Output terminal, 13... Pulse addition/removal circuit, IA... Frequency division circuit, 1[3... Protection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A digital phase synchronization circuit that outputs a phase synchronization signal with a frequency of RHZ based on an input digital signal sent at a rate of F bits per second, comprising: an oscillation circuit that oscillates a signal with a frequency of F(R+M+1)HZ; Compare the phase difference between the (R+M+1±K)-adic frequency divider circuit that divides the F(R+M+1)HZ signal from the oscillation circuit and the input digital signal and the phase synchronization signal output from the frequency divider circuit. a phase comparator; a control circuit that controls the value of K in the frequency divider circuit based on the phase lead pulse and the phase lag pulse outputted from the phase comparator to change the frequency division ratio of the frequency divider circuit; A digital phase synchronization circuit comprising: a protection circuit that loads the frequency dividing circuit when a phase fluctuation of a predetermined magnitude occurs in an input digital signal a predetermined number of times. However, F, R, and M are arbitrary numbers, and K represents either 0 or 1.