JP2744453B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a data processing device provided with a CPU and formed on a single semiconductor substrate, and furthermore a single data processing device for converting a multi-frequency mixed analog signal in such a data processing device. Regarding technology for identifying frequencies, for example, DTMF (dual tone
The present invention relates to a technology effective when applied to a single-chip microcomputer LSI having a multi-frequency (receiver) function.

(Prior art)

A DTMF signal used in a push-button telephone or the like is a two-frequency mixed signal obtained by combining one of the four low-frequency groups and one of the four high-frequency groups. Such DTMF signals are used not only to specify the destination station when making a call, but also to provide access to the record of the answering machine, as well as instruction signals for home automation and remote control using the telephone. It has also been used as.

Conventionally, a receiver for receiving a DTMF signal and separating and identifying the single frequency has been provided as a dedicated LSI. For example, a DTMF receiver LSI separates a single frequency from a DTMF signal using a bandpass filter for a high group or a bandpass filter for a low group, and shapes the separated single frequency with a comparator or a limiter. The interval or cycle of the waveform-shaped signal is counted based on the clock signal, and the counting result is compared with an expected value set in advance to obtain a single-frequency signal included in the two-frequency mixed signal. Or a switched capacitor filter for eight channels for discriminating between the high-group four-frequency and the low-group four-frequency is provided for each of the eight channels. Determine. The determination result is coded by a decoder or the like and output to the outside.

Data output externally from the DTMF receiver is used for data processing by a processor or microcomputer.
It is taken into the LSI, and the necessary control is performed by this.

An example of a document describing the DTMF receiver LSI is "LSI Handbook" P629 issued by Ohmsha on November 30, 1984.

[Problems to be solved by the invention]

However, if the DTMF receiver and the data processing device that performs control based on this output are configured by different LSIs, there is a possibility that noise may be affected when interfacing with each other. Moreover, the conventional DTMF receiver that constitutes a single LSI is configured to output the single-frequency discrimination result included in the multi-frequency mixed signal to the outside, so that a single frequency that can be discriminated, in other words, an applicable input The frequency band for analog signals was limited. As described above, since the characteristics or functions of the conventional DTMF receiver are determined centrally by its own hardware, there is no general versatility in the identifiable single frequency and the applicable frequency band for the input analog signal. In addition, since the sampling rate and conversion accuracy at the time of conversion are fixed, the operation or function cannot be freely selected, thereby making it difficult to easily cope with various systems and required specifications. The present inventor has clarified that there is a problem.

An object of the present invention is to provide a data processing apparatus having a function of determining a single frequency from a mixed analog signal having a plurality of frequencies, and having versatility in a frequency band for a determinable single frequency and an applicable input analog signal. To provide. Another object of the present invention is to provide a data processing device capable of easily selecting operating characteristics and functions such as the number of sampling periods of input analog signals and determination accuracy at the time of single frequency determination.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, means for separating a single frequency from a multi-frequency mixed analog signal, means for waveform shaping the separated single frequency, and waveform shaping according to an operation determined based on an instruction or signal given from a central processing unit. Means for forming digital data for frequency discrimination from a signal;
A multi-frequency receiver comprising data holding means for holding the digital data thus formed in an accessible manner by a central processing unit is formed together with the central processing unit on one semiconductor substrate to constitute a data processing unit. Things. For example, if the digital data forming means is constituted by a counter or the like which counts a clock signal having a fixed relationship with the operation clock signal of the central processing unit at intervals of an integral multiple of the period of the waveform-shaped signal, The processing device takes in the count result and determines the frequency of the single frequency or the type of the single frequency.

(Operation)

As described above, the central processing unit forms a multi-frequency mixed analog signal based on the conditions or signals given by itself to determine the operation of the digital data forming means and the data obtained by the digital data forming means. Since the type of the frequency is determined, it is possible to give versatility to the type of the single frequency that can be determined and the frequency band for the applicable input analog signal.

By changing the conditions and signals given by the central processing unit to determine the operation of the digital data forming means, it is possible to select the operating characteristics such as the sampling period of the input analog signal and the determination accuracy during single frequency determination. The degree of freedom increases.

Also, when the operation of the digital data forming means is indicated cyclically every time at every signal cycle obtained by the waveform shaping means or at an integer multiple thereof, the digital data formation is synchronized with the instruction at the central processing unit. By instructing the acquisition of the data obtained by the means, the multi-frequency receiver can operate asynchronously with the central processing unit, thereby reducing the load on the central processing unit when acquiring data for single frequency discrimination. You.

〔Example〕

FIG. 1 shows a data processing apparatus according to one embodiment of the present invention. Although not particularly limited, the data processing device shown in FIG. 1 is a single-chip microcomputer LSI in which a central processing unit is formed on one semiconductor substrate together with necessary peripheral devices.

In FIG. 1, a functional block indicated by 1 is a central processing unit CPU (hereinafter simply referred to as CPU) 30, a ROM (read only memory) 31, and a RAM (random access memory) 32 controlled by the CPU. , A functional block including peripheral devices such as an I / O (input / output circuit) 33. The functional block 1 can be interfaced with the outside via a data bus DB, an address bus AB, and a control bus CB.

In FIG. 1, reference numeral 2 denotes a DTMF receiver positioned as one peripheral device in a single-chip microcomputer LSI. The DTMF receiver 2 is not particularly limited, but is a DTMF signal used in push-button telephones or the like, that is, a two-frequency mixing in which one of the four low frequencies and one of the four high frequencies are combined. Analog signal Ai
This is a circuit that receives n and obtains information for determining two single frequencies that constitute n. This type of single frequency
CPU 30 based on the information obtained by DTMF receiver 2
Do.

DTMF receiver 2 is supplied to analog input terminal 3
A gain adjustment preamplifier and an anti-aliasing filter 20 for correcting line loss and reducing aliasing noise with respect to the DTMF signal Ain are provided at the input stage. Each is supplied to the low-group bandpass filter 5. The high-group bandpass filter 4 removes four low-group frequencies from the input DTMF signal Ain,
Also, the low-pass bandpass filter 5 receives the input DTMF signal Ain
From the high frequency group. Although not particularly limited, the high-group bandpass filter 4 and the low-group bandpass filter 5 can be configured by a biquad cascade-connected switched capacitor filter or an analog filter.

The single frequency separated by the high-group bandpass filter 4 is shaped into a rectangular wave by detecting its zero-cross point by a comparator such as a limiter, and the single-frequency separated by the low-group bandpass filter 5. Similarly, the frequency is shaped into a rectangular wave by detecting the zero-cross point by the comparator 7. The reference potential Vref is applied to each of the comparators 6 and 7.

In order to know the type of the signal whose waveform has been shaped by the comparator 6, it is necessary to measure the interval time between zero-cross points of the signal or a time that is an integral multiple thereof. In order to measure such a time, an edge generating circuit 21 for generating a pulse signal for each cycle of the output signal waveform of the comparator 6 and a high-group mode register 22 A high-group edge counter 23 that outputs a count-up signal CU ₂₃ each time it counts up to the set value of
A high-group period counter 8 is provided for resetting the count value each time the count-up signal CU ₂₃ is issued and counting the number of clocks of the clock signal CLK. The count-up signal CU ₂₃ output from the high group edge counter 23 is also supplied to the controller 14. This controller 14
Gate in the gate control signal GS ₁₀ before the high group for cycle counter 8 by the count-up signal CU ₂₃ is reset
10 is opened, and the count value of the high group period counter 8 at that time is transferred to the data register 12 internally. The count-up signal CU ₂₃ controls the high group interrupt flag 15 to be set. The flag signal FLG _{15 in the} set state informs the CPU 30 that the count value of the high group cycle counter 8 has been loaded into the data register 12, and subsequently issues a count-up signal CU ₂₃ to the controller 14. Even if it is operated, it acts as a prohibition signal for preventing the gate 10 from being opened. The reset for the high group interrupt flag 15 is enabled by a reset signal RST ₁₅ output by the CPU 30. When the flag 15 is reset, the controller 14 receives the count-up signal CU ₂₃ again, so that a new count value by the high group cycle counter 8 can be loaded into the data register 12.

Similarly, on the comparator 7 side, an edge generation circuit 24 that generates a pulse signal for each cycle of the output signal waveform of the comparator 7 and a low-group mode register that outputs the number of pulse signals output from the edge generation circuit 24 A low-group edge counter 26 that outputs a count-up signal CU ₂₆ every time counting is performed up to a set value of 25;
A low-group period counter 9 is provided for resetting the count value each time ₂₆ is generated and counting the number of clocks of the clock signal CLK. The count-up signal CU ₂₆ output from the low group edge counter 26 is also supplied to the controller 14. This controller 14 uses its count-up signal
Open gate 11 with gate control signals GS ₁₁ before low group for cycle counter 9 is reset by the CU _26, to the internal transfer count by low group for cycle counter 9 at the time the data register 13. The count-up signal CU ₂₆ controls the low group interrupt flag 16 to a set state. The flag signal FLG _{16 in the} set state indicates that the count value of the low group cycle counter 9 has been loaded into the data register 13 by the CPU 30.
And acts as a prohibition signal for the controller 14 to prevent the gate 11 from being opened even if the count-up signal CU ₂₆ is subsequently issued. The reset for the low group interrupt flag ₁₆ is enabled by a reset signal RST ₁₆ output by the CPU 30. When the flag 16 is reset, the controller 14 receives the count-up signal CU ₂₆ again, so that a new count value of the low-group cycle counter 9 can be loaded into the data register 13.

The number of cycles to be set in the high group mode register 22 and the low group mode register 25, that is, the pulse count value at which the respective edge counters ₂₃ and ₂₆ should output the count-up signals CU ₂₃ and CU ₂₆ is set by the CPU 30. I do. In this setting operation, selection of the high group mode register 22 and the low group mode register ₂₅ is performed by register selection signals RS ₂₂ and RS ₂₅ formed by an address decoder (not shown) for decoding an output address signal of the CPU 30. . Similarly, the CPU 30 accesses the count values loaded in the data registers 12 and 13,
The selection of the data registers 12 and 13 at that time is performed by register selection signals RS ₁₂ and RS ₁₃ formed by an address decoder (not shown). Note that the above registers 12,
13, 22, and 25 are connected to the data input / output terminals of the CPU 30 via the data bus IDB.

The loading of the count values from the cycle counters 8 and 9 into the data registers 12 and 13 indicates that the flag signals FLG ₁₅ and
The CPU 30 is notified by the FLG ₁₆ . Flag signal FLG ₁₅ , FL
G ₁₆ is positioned as an internal interrupt signal to the CPU 30, the CPU 30 at a predetermined sampling timing detects the flag signal FLG _15, FLG ₁₆ in the set state, the single frequency from DTMF signal 2 frequency mixing under predetermined conditions The process branches to DTMF receiver processing for determination.

When the operation of the CPU 30 branches to the DTMF receiver processing, the CPU 30
30 is not particularly limited, but first performs high group frequency discrimination,
Next, low group frequency discrimination is performed. For example, when determining the high group frequency, the CPU 30 accesses the data register 12 and takes in the count data. The acquired count data is compared with reference data corresponding to each of the four high-frequency groups, whereby
The high frequency group single frequency included in the DTMF signal Ain is determined.

Here, reference data corresponding to each of the high group 4 frequencies and the low group 4 frequencies is a clock signal CL corresponding to the cycle of each single frequency.
This is a count value of K, in other words, time information corresponding to the cycle of each single frequency. Therefore, by comparing the count values of the cycle counters 8 and 9 for counting the number of pulses of the clock signal CLK and the reference data directly or with a predetermined weight, the type of the single frequency included in the DTMF signal Ain can be changed. Is determined.

 Next, a detailed example of the DTMF receiver processing operation will be described.

In the DTMF receiver process, the CPU 30 has a high group discrimination flag (not shown) for determining whether to perform the high group discrimination but the low group discrimination, and the high group discrimination flag is initialized to a set state. The discrimination processing of each frequency of the high group and the low group in the DTMF receiver processing is not particularly limited, but is performed four times for each of the low group and the high group, and the DTMF measured in each of the four processings
The number of cycles of the signal Ain, that is, the number of pulses to be counted by the edge counters 23 and 26 is 3, 3, 2, and 3. Therefore, data corresponding to the number of three cycles is initially set in the high group mode register 22 and the low group mode register 25 by the CPU 30.

As shown in FIG. 2, the main routine of the DTMF receiver process first determines whether or not the high group determination flag is set (step S1). , when the flag signal FLG ₁₅ of high-group for the interrupt flag 15 in step S2 is determined to be in the set state, and executes the high group frequency discrimination processing routine (step S3). If the determination result in step S1 is in the reset state, the low group frequency determination is performed in response to determining in step S4 that the flag signal FLG ₁₆ of the low group splitting flag ₁₆ is in the set state. The processing routine is executed (Step S5). If it is determined in step S6 that the signal is a DTMF signal with respect to the determination results obtained by the high group frequency processing routine and the low group frequency processing routine, the processing returns to the beginning through the continuity check processing routine (step S7). In step S6, an enable bit for the DTMF receiver processing is disabled and initialized (step S8), and the DTMF receiver processing ends.

As shown in FIG. 3, the high group frequency determination processing routine stores the count value of the high group cycle counter 8 in the RAM from the data register 12 (step S30). In other words, it is determined whether or not the count data used for the determination is data corresponding to the three periods of the DTMF signal Ain (step S31). In the case of the three-period determination, a comparison is made to determine whether or not the count value stored in the RAM is included in the four high frequencies of the DTMF signal, that is, whether or not the signal is a DTMF signal (step S32).
If it is determined that the signal is a DTMF signal in step S34, it is determined which of the four high-frequency groups corresponds (step S34). When it is determined in step S31 that it is a two-cycle determination, the type of the high-group single frequency included in the DTMF signal is determined through steps S35 to S37 in the same manner as described above using the reference data for the two-cycle determination.

The low group frequency determination processing routine is also performed in the same manner as the high group frequency determination processing through steps S50 to S57 shown in FIG.

The processing routine of the continuity check described above sets the number of periods of the DTMF signal Ain measured four times for each of the low group and the high group to 3, 3, and
This is a process of changing the set values of the mode registers 22 and 25 so as to change to 2,3. That is, as shown in FIG. 5, in a series of four frequency determination processes for each of the high group and the low group, when it is determined in step S70 that the frequency determination operation is the second time, the third determination operation is performed. Therefore, the set value of the corresponding mode register 22 or 25 is changed to data corresponding to the number of two cycles (step S71). Next, when it is determined in step S72 that the frequency determination operation is the third one, the set value of the corresponding mode register 22 or 25 is changed to data corresponding to the number of three cycles for the fourth determination operation. (Step S37). When it is determined in step S74 that the frequency determination operation is the fourth time, the high group determination flag is switched (step S7).
Five). That is, if the high group discrimination flag is in the set state, it is reset, and if it is in the reset state, it is set. Thus, after the series of four high group (low group) frequency discrimination processes, the next series of four low group (high group) frequency discrimination processes can be started.

As described above, according to the present embodiment, the CPU 30
The clock signal CLK signal and the set values for the mode registers 22 and 25 provided by itself to determine the counting operation of the high group cycle counter 8 and the low group cycle counter 9 and the count values of the counters 8 and 9 are used. Since the type of the single frequency included in the DTMF signal Ain is determined based on the DTMF signal Ain, the characteristic or function of the DTMF receiver 2 is not centrally determined by its own hardware. Signal Ai
The frequency band for n can be made versatile. Furthermore, to make the applicable input analog signal frequency band more versatile, the bandpass filters 4,5
It is preferable that the switching clock signal frequency for the switched capacitor filter constituting the above is made variable or selectable.

Also, by changing the set values for the mode registers 22 and 25 and the frequency of the clock signal CLK, the operation characteristics such as the number of measurement cycles for the DTMF signal Ain and the counting accuracy of the zero-cross point interval time of the waveform-shaped signal are changed. The degree of freedom of function selection can be increased. further,
The count data held in the shared data registers 12 and 13 is C
Since the PU 30 is not updated by the new count value unless the flags 15 and 16 are reset, the same count data can be sampled any number of times and subjected to the single-frequency determination process,
Also in this respect, the degree of freedom of function selection is increased. By increasing the degree of freedom in selecting the operation characteristics and functions of the DTMF receiver 2, the sampling rate and the number of times of sampling data can be determined in consideration of the relationship between the processing capacity and the load of the CPU 30 on the system. Thus, the reliability of the DTMF receiver 2 can be maximized within a system allowable range.

Further, the count values of the cycle counters 8 and 9 are stored in the data registers 12 and
13, when loaded, the flag signals FLG ₁₅ , FLG
_The CPU 30 is notified via the CPU ₁₆ and the CPU can take in the count data at an arbitrary timing based on the notification and shift to processing for single frequency discrimination.
Can operate asynchronously with the CPU 30, and can reduce the load on the CPU 30 when acquiring count data for single frequency discrimination.

FIG. 6 shows a part of another embodiment of the present invention. In the embodiment shown in FIG.
Is read by the CPU 30 to determine the type of single frequency included in the DTMF signal Ain. In the embodiment shown in FIG. 6, the determination operation is performed by the DTMF receiver 40.

The DTMF receiver 40 partially shown in FIG.
A single-chip microcomputer LSI is configured together with the functional blocks 42 including the above. This DTMF receiver 40
Is the data register of the DTMF receiver 2 shown in FIG.
12 and 13 are changed to the configuration shown in FIG.
That is, in addition to the data register 43 which holds the count value of the counter 8,
The reference value for high-group single-frequency discrimination is set in correspondence with each of the four high-group frequencies, and the high-group upper-limit register 44, high-group lower-value register 45, and the count value held by the data register 43 A high-group single-frequency determining circuit 46 that compares the reference data with the DTMF signal Ain to determine the type of the high-group single frequency, and holds a determination result output from the high-group single-frequency determining circuit 46. And a data latch 47 which can be accessed arbitrarily. The high-group single-frequency determination circuit 46 determines the type of single-frequency by determining whether the measured count value falls between the upper limit and the lower limit of the reference data corresponding to each of the four high-group frequencies. . On the low-group cycle counter 9 side, in addition to the data register 48 holding the count value of the counter 9, reference data for low-group single-frequency discrimination corresponds to each of the low-group four frequencies. The upper limit register 49 for the lower group, the upper limit register 50 for the lower group, and the count value held in the data register 48 are compared with the reference data to determine the DTMF.
The low-group single-frequency determination circuit 51 that determines the type of the low-group single frequency included in the signal Ain, and a determination result output from the low-group single-frequency determination circuit 51 are held, and can be arbitrarily accessed by the CPU 41. And a data latch 52. The low-group single-frequency determination circuit 51 determines the type of the low-group single-frequency by determining whether the measured count value falls between the upper limit and the lower limit of any of the reference data corresponding to each of the four low-group frequencies. judge.

According to the present embodiment, the CPU 41 only needs to take in the information corresponding to the type of the single frequency determined by the DTMF receiver 40 at an arbitrary timing according to the operating condition issued by itself, and determines the type of the single frequency by itself. You don't have to
Can be significantly reduced.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, the case where the hardware for the high group frequency and the hardware for the low group frequency are individually provided as an example, but depending on the processing capability for the single frequency discrimination by the central processing unit, etc. Some of them may be shared by time sharing. Also, hardware for the high group, the middle group, and the low group may be provided.

In the above embodiment, the interrupt flags 15, 16 for the high group and the low group are used as means for informing the central processing unit of a state in which the count value obtained by the cycle counter can be read. An interrupt flag commonly used for the low-level group and the low-level group, and a flag bit for making it possible to identify the source of the interrupt flag. In this case, the control for the flag bits can use the rectangular waves output from the comparators 6 and 7, and the sampling for the flag bits can be performed when an interrupt generated by the interrupt flag is accepted. .

Although the DTMF receiver 2 of the above embodiment uses a period counter, the present invention is not limited to this, and may be a switched capacitor filter type. For example, in this case, the capacitor ratio of the switched capacitor filter is switched in a time-division manner to form a band-pass filter for a plurality of channels corresponding to the high-frequency 4 frequency and the low-frequency 4 frequency, and the serial output corresponding to each channel is obtained. The channel can be identified by a clock operation so as to detect the channel signal having the maximum amplitude, and data corresponding to the channel identification can be supplied to the data register. In this case, the switching operation clock applied to the switched capacitor filter or the like has a certain relation with the operation reference signal of the microprocessor.

The means for holding the count value of the cycle counter and the like so that it can be accessed by the central processing unit can be configured in a first-in first-out (FIFO) format. In this case, the count value of the cycle counter immediately before resetting can be continuously loaded into the data holding means a plurality of times.

Also, since the central processing unit can grasp the frequency of the count clock signal with respect to its own operation reference clock signal, the single-frequency discrimination processing is not limited to the comparison processing with the reference data, but the frequency of the count clock signal and the count data. May be determined based on the calculation result based on

Further, the output of the edge generating circuit or the output of the comparator may be directly supplied to the period counter without using the edge counter and the mode register used in the embodiment shown in FIG.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer LSI with a built-in DTMF receiver, which is a field of application as a background, has been described, but the present invention is not limited to this. The present invention can be widely applied to microcomputer LSIs and other data processing LSIs having a built-in multi-frequency receiver that handles multi-frequency mixed analog signals other than DTMF signals.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, the microprocessor determines the type of the single frequency included in the multi-frequency mixed analog signal based on the signal given to determine the operation of the digital data forming means and the data obtained by accessing the data holding means. The characteristics or functions of the multi-frequency receiver are not determined centrally by its own hardware, but by changing the signal for determining its operation,
The frequency band for the input analog signal can be made versatile, and the accuracy of the analog / digital conversion performed by the digital data forming means can be set relatively freely.

Further, when the opening and closing control of the gate means provided between the digital data forming means and the data holding means is performed based on the control of the microprocessor, the sampling receipt of the data for the single frequency identification and the number of times of sampling of the same data. Can be arbitrarily changed according to the control means of the microprocessor, and the degree of freedom in easily selecting the operation characteristics and functions of the multi-frequency receiver can be further increased. In addition, this makes it possible to determine the data sampling rate and the number of times of sampling for single-frequency identification in consideration of the relationship between the processing capacity of the microprocessor on the system and the load on the processor. It is possible to maximize the reliability of the multi-frequency receiver within the range.

When the signal change obtained by shaping the waveform of the input analog signal is used as a flag bit or an interrupt signal for an access request to the data holding means, further, once the digital data is internally transferred to the data holding means, the gate means is used. When the microprocessor is internally controlled to be closed, the microprocessor should easily and asynchronously control the number of sampling times and sampling rate of data for single frequency identification according to its internal control operation procedure with reference to a flag bit or an interrupt signal. Will be able to

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a data processing device according to the present invention, FIG. 2 is a flowchart of an embodiment showing a main routine for single frequency discrimination, and FIG. 3 is shown in FIG. 4 is a flowchart showing a subroutine for determining a high group frequency, FIG. 4 is a flowchart showing a subroutine for determining a low group frequency shown in FIG. 2, and FIG. 5 is a flowchart showing a continuity check shown in FIG. FIG. 6 is a block diagram showing another embodiment of the data processing apparatus according to the present invention. 1,42 ... Function block, 6,7 ... Comparator.

Continued on the front page (72) Inventor Keiji Kuboyama 5-20-1, Kamisumihoncho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Tomoaki Kubomura 5-2-1, Josuihoncho, Kodaira-shi, Tokyo No. Hitachi, Ltd. Musashi Factory (56) References JP-A-54-71512 (JP, A) JP-A-63-135870 (JP, A)

Claims (1)

(57) [Claims] 1. A multi-frequency receiver is provided on a single semiconductor substrate together with a central processing unit. The multi-frequency receiver includes means for separating a single frequency from a multi-frequency mixed analog signal, and means for separating the separated single frequency. Means for shaping the waveform, and a plurality of sets of means for forming digital data for determining the type of single frequency based on the signal whose waveform has been shaped, wherein the means for forming the digital data includes: A pulse generation circuit that outputs a pulse signal at predetermined intervals, a mode register that is made write-accessible by the central processing unit, and counts the number of pulses output from the pulse generation circuit up to a value set in the mode register Output a count-up signal every time
A counter, a second counter that counts a clock signal supplied from the central processing unit and is reset by the count-up signal, and an input connected to an output of the second counter via a gate circuit, the central processing unit A read-accessible data register from the first state to the second state by the count-up signal, a predetermined interrupt signal to the central processing unit according to the second state, and a reset signal from the central processing unit. An interrupt flag for returning from the second state to the first state; and a count value of the second counter by turning on the gate circuit on condition that the interrupt flag is in the first state when the count-up signal is output. And a controller for transferring the data to the data register. The frequency of the clock signal and the setting of the mode register are made variable, and the value of the data register is read in response to the interrupt signal.
A data processing device for performing a type discrimination process of a single frequency constituting a multi-frequency mixed analog signal based on a frequency of the clock signal and a value set in the mode register.