JP3284145B2 - PLL synchronous measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synchronous measuring apparatus, and more particularly, to a PLL synchronous measuring apparatus which measures an electric current, a voltage, etc. by A / D-converting an input signal in synchronization with a PLL circuit. It is about.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional example of this type of measuring apparatus. According to this, the waveform of the input signal IN is shaped by the waveform shaping circuit 10, and the synchronous clock signal synchronized with the fundamental wave is output from the waveform shaping circuit 10.

This synchronous clock signal is supplied to a PLL (P
The PLL circuit 11 outputs a sampling clock signal having a frequency that is N times as high as that of the sample-hold circuit 12 to the sample-hold circuit 12.

The input signal IN is sampled by the sample-and-hold circuit 12, converted into a digital signal by an A / D conversion circuit 13, and then converted into a digital signal (DSP).
(AlSignal Processor).

The synchronous clock signal of the waveform shaping circuit 10 is taken into the period measuring circuit 15 and a predetermined number thereof is counted, so that the period data is output from the same period measuring circuit 15 to the arithmetic processing means 14. .

[0006] The arithmetic processing means 14 performs arithmetic processing such as effective value arithmetic for each waveform of the input signal, and stores the arithmetic data together with the periodic data in the memory 16. As described above, since time data for each waveform or every several waveforms is obtained, for example, the integrated current value Ah and the integrated power value Wh
Can be processed.

[0007]

SUMMARY OF THE INVENTION However, PLL
Since the circuit 11 has a response time to the frequency fluctuation,
There is a possibility that the data taken into the arithmetic processing unit 14 via the A / D conversion circuit 13 and the time data measured by the period measurement circuit 15 do not correspond.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and has a structural feature that a waveform shaping circuit for outputting a synchronous clock signal synchronized with a fundamental wave of an input signal; Upon receiving this synchronous clock signal,
A PLL circuit that outputs a sampling clock signal having a double frequency, an A / D conversion circuit that samples the input signal using the sampling clock signal from the PLL circuit, and converts the input signal into a digital signal; An arithmetic processing means for performing a predetermined arithmetic operation on the output digital signal; a memory for storing arithmetic data obtained by the arithmetic processing means; and a cycle measuring means for measuring a cycle of the input signal; In a measuring device which supplies the cycle data measured by the measuring means to the arithmetic processing means or the memory so as to be able to arithmetically process the input signal including its time element, the cycle measuring means comprises the PLL The input signal based on a signal obtained by dividing the sampling clock signal output from the voltage controlled oscillator in the circuit by 1 / N In that so as to measure the period data.

[0009]

According to the above configuration, the sampling of the input signal and the A / D conversion are performed based on the sampling clock signal output from the voltage controlled oscillator in the PLL circuit. / N is used, so that A / D
There is no time lag between the converted data and the periodic data.

[0010]

FIG. 1 is a block diagram of a measuring apparatus according to one embodiment of the present invention. Note that the same reference numerals as those in FIG. 2 described above denote the same parts in FIG.

The PLL circuit 11 includes a phase comparator 11a, a low-pass filter (LFP) 11b, and a voltage-controlled oscillator (V
CO) 11c and a counter 11d. The phase comparator 11a receives an input signal (in this case, the waveform shaping circuit 1).
(A synchronous clock signal from 0) and a feedback signal from the counter 11d, and outputs the difference voltage.

The low-pass filter 11b removes high-frequency noise components contained in the difference voltage, and the voltage-controlled oscillator 11c generates a sampling clock signal having a frequency N times the synchronous clock signal in accordance with the difference voltage. Is output.

The sampling clock signal is supplied to the sample-and-hold circuit 12, and the counter 11d divides the frequency of the sampling clock signal by 1 / N and supplies it to the phase comparator 11a as a feedback signal.

Here, since the low-pass filter 11b has a time delay element, if the frequency of the input signal fluctuates suddenly, a delay will follow in the following. That is, at the time of frequency fluctuation, a time lag occurs between the input signal (synchronous clock signal) and the sampling clock signal output from the voltage controlled oscillator 11c.

Therefore, in the present invention, the cycle measuring circuit 15 counts the feedback signal divided by 1 / N to obtain cycle data.

As a result, there is no time lag between the waveform data converted by the A / D conversion circuit 13 and the cycle data obtained by the cycle measurement circuit 15, and the arithmetic processing means 1
For example, when the integrated current value Ah and the integrated power value Wh are calculated by the method 4, accurate measurement values can be obtained.

In the above embodiment, the periodic data is input to the arithmetic processing means. However, the periodic data may be directly written into the memory 16 together with the arithmetic data from the arithmetic processing means.

[0018]

As described above, according to the present invention, A / D conversion is performed by synchronizing an input signal with a PLL circuit, and voltage, current, power, etc. are measured, or harmonic analysis is performed. In a PLL synchronous measuring device that performs
By measuring the period data of the input signal based on a signal obtained by dividing the sampling clock signal output from the voltage controlled oscillator in the PLL circuit by 1 / N,
There is no time lag between the A / D-converted waveform data and its periodic data, and therefore, when performing calculations and analyzes including time elements, an effect is obtained in which more accurate values can be obtained. You.

[Brief description of the drawings]

FIG. 1 is a block diagram according to an embodiment of the present invention.

FIG. 2 is a block diagram for explaining a conventional example.

[Description of Signs] 10 Waveform shaping circuit 11 PLL circuit 11a Phase comparator 11b Low-pass filter 11c Voltage-controlled oscillator 11d Counter 13 A / D conversion circuit 14 Arithmetic processing means 15 Period measurement circuit 16 Memory

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 19/00-19/257 H03L 7/06 H03M 1/12

Claims (1)

(57) [Claims] 1. A waveform shaping circuit for outputting a synchronous clock signal synchronized with a fundamental wave of an input signal, a PLL circuit for receiving the synchronous clock signal and outputting a sampling clock signal having a frequency N times higher than the synchronous clock signal, An A / D conversion circuit that samples the input signal by a sampling clock signal from the circuit and converts the input signal into a digital signal; an arithmetic processing unit that performs a predetermined operation on the digital signal output from the A / D conversion circuit; A memory for storing calculation data obtained by the calculation processing means; and a cycle measurement means for measuring a cycle of the input signal, wherein the cycle data measured by the cycle measurement means is stored in the calculation processing means or the memory. Wherein the input signal can be subjected to arithmetic processing including its time element. The PLL synchronization circuit characterized in that the measuring means measures the period data of the input signal based on a signal obtained by dividing the sampling clock signal output from the voltage controlled oscillator in the PLL circuit by 1 / N. Type measuring device.