CN100349378C - Network synchronization slave clock phase-locked loop capable of integrating - Google Patents
Network synchronization slave clock phase-locked loop capable of integrating Download PDFInfo
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Abstract
The present invention relates to a network-synchronization integratable slave-clock phase-locked loop used for all-level synchronization units of an SDH transport network, time frequency synchronization equipment of CDMA base stations, digital synchronization networks and all-level slave clocks of stored-program control exchanges. The slave-clock phase-locked loop namely a dual-ring slave-clock phase-locked loop is composed of a loose coupling full digital phase-locked loop and a narrow-band analog phase-locked loop crossly connected together, wherein input reference signals are added to an input end of the full digital phase-locked loop of which the output signal is used as the input of the analog phase-locked loop; the output of the analog phase-locked loop is used as the output of the slave clock phase-locked loop. The two phase-locked loops share a high-stability constant-temperature voltage-controlled crystal oscillator VCXO. The full digital phase-locked loop uses the high-stability constant-temperature voltage-controlled crystal oscillator VCXO in the analog phase-locked loop as a frequency source respectively added to a pulse plus-minus circuit, a K counting circuit and a data acquisition processing circuit as an internal clock.
Description
Technical field
The present invention relates to a kind of SDH of being used for and transmit net lock units at different levels, cdma base station temporal frequency synchronizer, digital synchronous network and the stored-program control exchange network synchronization slave clock phase-locked loop capable of integrating from clock at different levels.
Background technology
The digital communication network net refers to require the clock frequency and the phase place of all nodes in the net to be strict controlled in certain range of tolerable variance in order to guarantee the digital communication network operate as normal synchronously.In various digital communication networks, be used to realize netting synchronous equipment and be called network synchronous clock, be called for short by " clock ".
The net simultaneous techniques is one of key technology of digital communication network, is divided into quasi-synchronizing method and with footwork two big classes.Accurate simultaneous techniques is usually used in international link, and each node independently is provided with reference clock (cesium-beam atomic clock), and its frequency accuracy remains on 10
-11Within the extremely narrow frequency tolerance.The domestic digital communication network in various countries generally adopts principal and subordinate's method of synchronization, the classification of net interior nodes clock, it is primary resource clock (highest clock or one-level clock) that high stability and high precision clock (cesium-beam atomic clock or gps clock) are set, other nodal clocks are called from clock in the net, with from clock phase-locked loop technology and primary resource clock (or upper level clock) Frequency Synchronization, make the whole network clock work on same frequency.
From the clock phase-locked loop technology is the core technology of net simultaneous techniques.It is at different levels from all kinds of net synchronizers such as clock, SDH system equipment lock units at different levels, cdma mobile communication net base station temporal frequency synchronizer to be widely used in digital synchronous network and stored-program control exchange.
(1), from the clock phase-locked loop characteristic
Because the specific (special) requirements that net is synchronous is a kind of special phase-locked loop from clock phase-locked loop, except that the high performance technology that satisfies ITU--T related advisory and GB regulation requires, have following distinguishing feature:
1, loop bandwidth is extremely narrow: for the timing jitter that the filtering reference-input signal produces through Network Transmission, the loop band requires less than 10Hz;
2, loose coupling: have tracking, maintenance and three kinds of operating states of free oscillation from clock request.Hold mode refers to the input reference dropout, still keeps benchmark to lose preceding frequency values from clock output frequency.Keep requiring between output of clock phase-locked loop road and input reference, adopting loose coupling;
3, have the Based Intelligent Control ability: data acquisition and processing (DAP), operating state judgement, conversion, indication, failure diagnosis, alarm etc. require loop to finish automatically.
Therefore, be a kind of special high-performance, arrowband, loose coupling INTELLIGENT PLL from clock phase-locked loop.
At present, generally adopt both at home and abroad shown in Figure 1 from the clock phase-locked loop technical scheme.Thisly come down to an analog phase-locked look,, claim that it is the monocycle clock phase-locked loop for ease of distinguishing with technical solution of the present invention from clock phase-locked loop.It is on the basis of the analog phase-locked look of being made up of pulse phase discriminator, integration low pass filter, VCXO (high-stability constant-temperature VCXO) and ÷ 2N frequency divider, adds digital processing and the control circuit be made up of frequency detection circuit, A/D converter, microprocessor and D/A converter and forms.Digital processing and control circuit are finished narrow-band filtering, loose coupling and Based Intelligent Control function.
Monocycle clock phase-locked loop operation principle is summarized as follows:
1, input reference signal u
i(t) and local oscillated signal u
o(t) phase demodulation in pulse phase discriminator send A/D converter through integration low pass filter output direct-flow error voltage.A/D converter converts direct-flow error voltage to the data-signal of reflection two signal phase error;
2, the data-signal of A/D converter output is stored behind data acquisition, sum-average arithmetic, digital filtering operation in microprocessor, and T (digital filter time constant) will store data and send D/A converter at regular intervals;
3, D/A converter converts input data signal to analog DC voltage, control VCXO frequency.Behind the loop-locking, loop output frequency f
oWith benchmark incoming frequency f
iSynchronously, i.e. f
o=f
i
4, when microprocessor through the frequency monitoring electric circuit inspection when the input reference dropout, the data that immediate instruction is stored before D/A converter send the input reference dropout, keep the D/A converter output dc voltage constant, and then to keep the loop output frequency still be frequency values before the input reference dropout, realizes loop loose coupling maintenance function;
5, when loop is caught and follow the tracks of, data sample and the detected signal (frequency signal of microprocessor to gathering, forced signal etc.) handle in real time according to the state criterion, realize functions such as loop parameter conversion, operating state conversion, state indication, fault detect, alarm.
There is following shortcoming in the monocycle clock phase-locked loop:
(1) technical sophistication: not only comprise the complicated hardware system, and need complicated systems soft ware support;
(2) be not easy to integrated: aspect system hardware, because D/A converter, microprocessor, D/A converter are the important component parts of loop, it is complicated that hardware is formed, and contain a large amount of analog circuits, is not easy to the system integration;
(3) versatility is poor: systems soft ware is the indispensable part of loop, because the state criterion is based upon on the basis that the data to the front and back twice storage compare in real time, loop also need become parameter operation (require loop that the two kinds of parameters in arrowband and broadband are set and be respectively applied for tracking mode work and trapped state work), not only make the systems soft ware complexity, and clock system at different levels can not be general;
(4) be difficult for guaranteeing high-performance: the control voltage that D/A converter outputs to VCXO is not continuous variation, but ladder saltus step, can not guarantee when making loop tracks that the loop output frequency accurately equals the input reference frequency, but near the continuous step saltus step of two frequency quantized levels the input reference frequency produces the stability that output phase is unstable and the influence net is synchronous.In addition, keep performance owing to be subjected to D/A converter and A/D converter figure place and microprocessor internal resource limit to be difficult for obtaining high accuracy;
(5) require high-level technical staff to support: no matter develop still and produce in batches, all need existing hardware designs ability, the high-level technical staff who is familiar with software programming again supports.
Summary of the invention
The object of the present invention is to provide a kind of network synchronization slave clock phase-locked loop capable of integrating,, reduce equipment volume, reduce cost, be convenient to produce to reduce technical sophistication degree from clock phase-locked loop.
For achieving the above object, technical program of the present invention lies in having adopted a kind of network synchronization slave clock phase-locked loop capable of integrating, should be that the dicyclo be made up of a loose coupling all-digital phase-locked loop and arrowband analog phase-locked look interconnection is from clock phase-locked loop from clock phase-locked loop, the input reference signal is added to the input of all-digital phase-locked loop, the output signal of all-digital phase-locked loop is as the analog phase-locked look input, analog phase-locked look output is as the output from clock phase-locked loop, two shared high-stability constant-temperature VCXOs of phase-locked loop, described loose coupling all-digital phase-locked loop is by first pulse phase discriminator, data acquisition processing circuit, logic control circuit, the K counter, pulse addition and subtraction circuit ID circuit, Fractional-N frequency device and high-stability constant-temperature VCXO are formed, first pulse phase discriminator compares the phase place of input reference signal and all-digital phase-locked loop output signal, output pulse width is proportional to the error pulse of two signal phase differences, error pulse produces control signal control K rolling counters forward after data acquisition processing circuit, the K counter converts two signal phase differences to and adds pulse or subtract pulse output, and through pulse addition and subtraction circuit adding or deduction pulse in the train pulse of high-stability constant-temperature VCXO output, adjust loose coupling all-digital phase-locked loop output frequency, make all-digital phase-locked loop catch locking fast, all-digital phase-locked loop is added to pulse addition and subtraction circuit respectively with the high-stability constant-temperature VCXO working frequency source in the analog phase-locked look, K counting circuit and data acquisition processing circuit are made internal clocking.
Described arrowband analog phase-locked look is by second pulse phase discriminator, loop filter, form with high-stability constant-temperature VCXO and 2N frequency divider that all-digital phase-locked loop is shared, second pulse phase discriminator compares the phase place of all-digital phase-locked loop output signal and analog phase-locked look output signal, export the analog DC voltage that is proportional to two signal phase differences through loop filter, the output frequency of control high-stability constant-temperature VCXO.
Described data acquisition processing circuit is by data acquisition circuit, the waveform restore circuit, the constant generator, bus switch and comparator five parts constitute, data acquisition circuit becomes the error pulse conversion of signals of first pulse phase discriminator output data and carries out the filtering interfering processing, the constant generator produces constant data, bus switch is controlled by logic control circuit, be used for gating sampled data or constant data, the waveform restore circuit then reverts to pulse control signal with the data of bus switch gating, and comparator comparison sampled data and constant data produce follows the tracks of and catch soon index signal; The sampled data of data acquisition circuit inserts bus switch on the one hand, inserts comparator simultaneously again, and the constant data of the generation of constant generator similarly inserts bus switch on the one hand, inserts comparator simultaneously again; Sampled data and regular data data compare at comparator, comparator output low level when equating, the indication loop enters lock-out state, comparator output high level when unequal, the indication loop enters trapped state, the input of restore circuit inserts the output of bus switch, the bus select signal of bus switch is used for bus and switches, be used for during the bus select signal low level of bus switch following the tracks of and catching, the data acquisition circuit bus data is connected with the waveform restore circuit, recover the pulse signal identical at waveform restore circuit output with the phase discriminator output pulse width, when the bus select signal of bus switch control end is in high level, the constant data that the constant generator the produces waveform restore circuit that veers away, the output of waveform restore circuit is by the impulse waveform of constant data decision, the sampled data when constant data equals to follow the tracks of.
Logic control circuit is made of frequency monitoring circuit and control circuit, two inputs of frequency monitoring circuit add the input reference signal and from the output signal of clock, monitor having or not of two signals, logic control circuit then produces control signal and various condition indicative signal according to the output and the forced signal of frequency monitoring circuit.
The present invention adopts brand-new dicyclo clock phase-locked loop structure: will be finished by two phase-locked loops from arrowband, loose coupling and the Based Intelligent Control functional separation of clock phase-locked loop.The loose coupling all-digital phase-locked loop is finished loose coupling and Based Intelligent Control function, and the arrowband analog phase-locked look is finished the narrow-band filtering function, makes clock performance be able to comprehensive raising; Two phase-locked loop interconnections and shared same high-stability constant-temperature VCXO, no matter have initial condition how during stable state the digital phase-locked loop stable state differ and be constantly equal to 0 important feature, make condition judgement and keep realization mechanism to simplify greatly.The present invention adopts unique data acquisition processing circuit: the digital data acquisition processing circuit of unique design and simple function control circuit combination, can realize loose coupling maintenance and Based Intelligent Control function.Without A/D converter, D/A converter, microprocessor and corresponding complex software, do not contain analog circuit, all adopt digital circuit, make the fully integrated possibility that becomes of system.The present invention's whole circuit except that high-stability constant-temperature VCXO and the several Resistor-Capacitor Units of loop filter can be integrated in a slice chip, and clock phase-locked loop systems technology very complicated, that high-tech requires is simplified to foolproof device application problem.Make system simplification, cost reduction, volume reduce, and be convenient to new product development and production.
Description of drawings
Fig. 1 is existing from clock phase-locked loop technical scheme block diagram;
Fig. 2 is a network synchronization slave clock phase-locked loop capable of integrating block diagram of the present invention;
Fig. 3 is network synchronization slave clock phase-locked loop capable of integrating chip clk-pll of the present invention (being used for stored-program control exchange two, a stratum-3 clock) application circuit;
Fig. 4 is Fig. 3 Clk-pll chip functions modular circuit;
Fig. 5 is data acquisition processing circuit figure.
Embodiment
The present invention is made up of a loose coupling all-digital phase-locked loop and an arrowband analog phase-locked look interconnection (not being simple polyphone) from clock phase-locked loop, is called the dicyclo clock phase-locked loop.The general frame as shown in Figure 2; Input reference signal u
i(t) be added to the all-digital phase-locked loop input, all-digital phase-locked loop output signal u
O1(t) as analog phase-locked look input, analog phase-locked look output signal u
O2(t) export as clock phase-locked loop; Two shared VCXO of loop, all-digital phase-locked loop is added to ID circuit, K counter and The data treatment circuit respectively and makes internal clocking with analog phase-locked look VCXO working frequency source.Be characterized in:
1, will finish by two phase-locked loops from narrow-band filtering, loose coupling and the Based Intelligent Control functional separation of clock phase-locked loop.The loose coupling all-digital phase-locked loop is caught, is followed the tracks of the input reference frequency fast and finishes loose coupling and the Based Intelligent Control function, and the arrowband analog phase-locked look is finished narrow-band filtering, suppressed the input jiffer function.Make performance improve comprehensively.
2, all-digital phase-locked loop is used analog phase-locked look VCXO working frequency source, the DCO (digital controlled oscillator) of all-digital phase-locked loop is become VDCO (voltage-controlled digital controlled oscillator), all-digital phase-locked loop output frequency and phase place are controlled by digital phase-locked loop not only, and controlled by analog phase-locked look, have regardless of initial condition, (when analog-and digital-loop all locks) digital phase-locked loop stable state differs and is constantly equal to 0 important feature during stable state, make condition judgement and maintenance realization mechanism simplify the integrated possibility that becomes greatly.
Dicyclo clock phase-locked loop operation principle is summarized as follows:
1, pulse phase discriminator (1), K counter, ID circuit (plus-minus circuit), ÷ Fractional-N frequency device and VCXO form the single order all-digital phase-locked loop, and wherein K counter, ID circuit and VCXO constitute VDCO.Pulse phase discriminator (1) is input reference signal u relatively
i(t) with digital phase-locked local signal u
O1(t) phase place, output pulse width is proportional to the error pulse signal controlling K rolling counters forward of two signal phase differences, the K counter changes into two signal phase differences and adds pulse or subtract pulse output, in the train pulse of VCXO output, add or the deduction pulse through the ID circuit, adjust the digital loop output frequency, digital loop is caught fast into lock.Behind the loop-locking, its output frequency f
O1Equal the input reference frequency f
i, stable state differs θ
E ∞Be proportional to initial frequency difference Δ f
o(Δ f
o=f
i-f
v).
2, pulse phase discriminator (2), loop filter, VCXO and ÷ 2N frequency divider are formed arrowband, one 2 rank analog phase-locked look, digital phase-locked loop output signal μ
O1(t) as arrowband analog phase-locked look input signal.Pulse phase discriminator (2) comparator input signal μ
O1(t) and arrowband analog phase-locked look local signal μ
O2(t) phase place is exported the analog DC voltage that is proportional to two signal phase differences through loop filter, the frequency of control VCXO.Behind the loop-locking, arrowband analog phase-locked look output frequency f
O2Follow the tracks of digital phase-locked loop output frequency f
O1, that is follow the tracks of the input reference frequency f
i, reach f
O2=f
v=f
O1=f
i, and with its input signal shake of the narrow-band characteristic filtering of arrowband analog phase-locked look.
3, because two shared same VCXO of loop along with arrowband analog phase-locked look continuous frequency of adjusting VCXO in acquisition procedure, make the inherent frequency error Δ ω of digital phase-locked loop
oConstantly reduce, and then make the digital phase-locked loop stable state differ θ
E ∞Constantly reduce.In a single day the arrowband analog phase-locked look goes into lock, because f
v=f
i, then get Δ ω
o=0, θ
E ∞=0.Expression digital phase-locked loop stable state differs when equalling zero, and enters the tracking operating state from clock phase-locked loop.Following the tracks of operating state, pulse phase discriminator (1) output duty cycle is 50% pulse signal, the digital phase-locked loop output signal not only with input reference signal same frequency but also same-phase.
4, loose coupling and Based Intelligent Control function are finished by insertion data acquisition processing circuit and control circuit in the all-digital phase-locked loop.Data acquisition processing circuit has data acquisition and waveform restore funcitons.Data acquisition circuit becomes the error pulse conversion of signals of pulse phase discriminator (1) output data and carries out the filtering interfering processing.Data after the waveform restore circuit then will be handled revert to the pulse signal identical with the error pulse signal.When clock phase-locked loop locks (when two loops all lock), because the digital phase-locked loop stable state differs identically vanishing, image data is a constant.When the input reference dropout, the control waveform recovered part is still exported the pulse signal by this constant value decision, then keeps the digital phase-locked loop output frequency constant, and then keeps arrowband analog phase-locked look output frequency constant, realizes that loose coupling keeps function.Whether control circuit equals the operating state criterion that this constant value is set up, judgement, control and telltable clock operating state according to sampled data.
Fig. 3 illustrates integrated dicyclo clock phase-locked loop chip clk-pll (being used for stored-program control exchange two, stratum-3 clock) application circuit.The external VCXO of clk-pll (centre frequency 16.384MHZ) and a RC integration loop filter are (by R
1, C
1Form).VCXO output is connected with the Ioc-16m input with 16m.Pd2-out output T-Ring path filter input, loop filter output termination VCXO control end.Fa and fb input join as loop input, loop input reference frequency 8KHz.Loop output 8KHz and 2048KHz are respectively by a8k and the output of 2m output.Digital phase-locked loop operating frequency 2KHz, analog phase-locked look operating frequency 8KHz.All the other input/output ports of Clk-pll are:
Mp1, mp2: force free oscillation and force the retentive control input.External force switch S1, S2.
Mfb, mfo: output, external status indicator lamp, low level lamp are showed the score and are not indicated the loop input/output signal normal;
Hold: output, external maintenance indicator light, the bright indication loop of low level lamp is operated in the maintenance operating state;
Free: output, external free oscillation indicator light, the bright indication of low level lamp is operated in the free oscillation operating state;
Alarm: output, external alarm indicator, bright indication loop fault warning of low level lamp or losing lock alarm;
R-cat: output, the external indicator light of catching soon, the bright indication loop of low level lamp is operated in catches operating state;
Track: output, external tracking indicator light, the bright indication loop of low level lamp is operated in tracking mode;
Wout: waveform recovers output, is used for debugging;
Pdl-out: digital phase-locked loop phase discriminator output is used for debugging;
D8k: the digital phase-locked loop output is used for debugging;
Also have VCC in addition: feeder ear (+5V) and GND: earth terminal and external power supply filtering shunt capacitance.
Clk-pll chip circuit shown in Figure 4 is made up of following functional module: DV4 (parametric frequency divider), ECPD-1 (digital phase-locked loop phase discriminator), K10 (K counter), D-ID (plus-minus circuit), DV-4096 (frequency divider in the digital rings), S-DSP (data acquisition processing circuit), contr (logic control circuit), ECPD-2 (analog phase-locked look phase discriminator), n-2048 (frequency divider in the analog loop).Wherein DV4, ECPD-1, K10, D-ID, DV-4096, D-DSP, contr and external VCXO form loose coupling intelligent digital phase-locked loop; ECPD-2, n-2048, external VCXO and loop filter are formed the arrowband analog phase-locked look.Have 6 input pins (fa, fb, mp1, mp2, Ioc-16m, 16m) and 13 output pins (mfb, mfo, hold, free, alarm, r-cat, track, wout, pd1-out, pd2-out, d8k, a8k, 2m).Also have power supply pin and grounding pin in addition.Each function module circuit brief introduction is as follows:
1.K10-K counter
The K counter is used for the error pulse of ECPD-1 output is transformed into and adds pulse or subtract pulse.The K counter is for adding/down counter, by adding/subtract Enable Pin d/upn control.K value sign counter maximum count bit wide is determined the counter maximum count value.Control impuls is added to/subtracts Enable Pin d/upn, and the VCXO signal is received K clock kclk end by the Ioc-16m input pin.D/upn=1 (corresponding control impuls high level) adds counting to the K clock, and when counting reached maximum, pulsewidth of addpls end output equaled the pulse that adds in kclk cycle; D/upn=0 (corresponding control impuls low level) subtracts counting, count down to the subtract pulse that pulsewidth of subpls end output in 0 o'clock equals the kclk cycle.
2, d-id-I/D circuit
The I/D circuit is used for control frequency, has three input: idclk (ID clock) to connect that VCXO signal (being inserted by the 16m input pin), addpls (adding pulse) connect K counter addpls output, subpls (subtract pulse) connects K counter subpls output; An output idout.When not having " adding pulse " and " subtract pulse ", the output of output idout is the two divided-frequency of idclk; When one of the last appearance of addpls adds pulse, among the output pulse sequence of idout, insert a pulse; When subpls brings out existing subtract pulse, pulse of deduction from the output pulse sequence of idout.The purpose that continuous insertion of " adding pulse " and " subtract pulse " control idout output pulse sequence that input constantly occurs and deduction pulse reach the numerical control frequency.
3, epcd-1/epcd-2-ECPD phase discriminator
ECPD edge phase discriminator is a kind of of pulse phase discriminator, is used for the phase bit comparison.Two input phase-a and phase-b are arranged, an output end p d-out.The pulse trailing edge is effective, and phase-a input pulse trailing edge makes pd-out become high level, and phase-b input pulse trailing edge makes pd-out become low level.Phase-a T-Ring road input external standard signal, phase-b connects local signal, the pulse signal of phase discriminator output pulse width direct ratio two signal phase differences.If two input signals are zero to differ (actual differing is pi/2), the duty ratio of output signal is 50%; If the local signal phase place lags behind the external standard signal, the duty ratio of output signal is greater than 50%; If the local signal phase place lags behind the external standard signal, the duty ratio of output signal is little by 50%.
4, S-dsp-data acquisition processing circuit
Data acquisition processing circuit is finished functions such as data acquisition, bus selection, data comparison and waveform recovery.Four input: pd1-out are connected with ECPD-1 output pd1-out, and internal clocking spclk connects the VCXO signal, is inserted by the Ioc-16m input pin.The sel end links to each other with control circuit output sel, and gatel connects DV-4096 frequency divider output q11.Three outputs: waveform recovers output wout (meeting chip output pin wout), tracking mode output track output (meeting chip output pin track), trapped state output r-cat (meeting chip output pin r-cat).Data acquisition function is that the pulse signal that phase discriminator is exported is become data, and the waveform restore funcitons is that data are become pulse signal.Sampled data is sent the waveform restore circuit on the one hand, and the waveform restore circuit is according to the input data, and the pulse signal that produces respective width is exported through wout.The data of gathering send comparator to compare with constant data simultaneously: comparator output low level when equating, and the indication loop enters lock-out state, comparator output high level when unequal, the indication loop is in trapped state.Bus selection control signal sel is used for bus and switches; Be used for during the sel low level following the tracks of and catching, the data acquisition circuit data/address bus is connected with waveform restore circuit data/address bus; The bus selector control end is in high level during maintenance, data acquisition circuit data/address bus and constant generator bus are connected, the constant data that the constant generator produces is sent the waveform restore circuit, and waveform restore circuit output wout output is by the impulse waveform of constant data decision.
5, contr-logic control circuit
Logic control circuit is made up of frequency monitoring circuit and control circuit.The frequency monitoring circuit is used to monitor having or not of input reference signal (the fb termination is gone into) and loop output signal (the fo termination is gone into), and control circuit then produces control signal sel and various condition indicative signal (low level): mfb (input is normal), mfo (input normally), hold (hold mode), free (free-running operation), alam (losing lock or fault warning) according to frequency monitoring circuit output and forced signal mp1, mp2 and r-cat.
6, DV4-parametric frequency divider:
Be used for the input reference signal frequency split is become 2KHZ input reference signal.Fraction frequency device input end connects the input reference signal, and the phase-a end of output and ECPD-1 joins.
7, frequency divider in the DV-4096-digital phase-locked loop ring:
Fraction frequency device input end connects the ID circuit output end.Output divides two-way: one road q11 send the phase-b end of ECPD-1 to make the digital phase-locked loop local signal; Another road q9 send the ECPD-phase2 end to make the analog phase-locked look input signal, and is connected as digital phase-locked loop output monitoring with chip output pin d8k.
8, frequency divider in the N-2048-analog phase-locked look ring:
Fraction frequency device input end connects the VCXO signal, is inserted by the Ioc-16m input pin.Output divides two-way: one road q10 send the phase-b end of ECPD-2 to make the analog phase-locked look local signal, and is connected as analog phase-locked look one tunnel output with chip output pin a8k; Another road q2 is connected with chip output pin 2m as another road output of analog phase-locked look.
Data acquisition processing circuit shown in Figure 5 is made up of data acquisition circuit, constant generator, bus selector, comparator and waveform restore circuit five parts.Data acquisition circuit becomes the pulse signal of phase discriminator output into data, send the waveform restore circuit through 8 sum-average arithmetics and bus selector with data, recovers the pulse signal identical with the phase discriminator output pulse width at waveform restore circuit output.The constant data that the data of gathering send comparator and constant generator to produce simultaneously compares: comparator output low level when equating, and the indication loop enters lock-out state, comparator output high level when unequal, the indication loop is in trapped state.The bus selector control signal is used for bus and switches: the bus selector control end is in low level during tracking, output bus and data bus enable; The bus selector control end is in high level during maintenance, and output bus and constant generator bus are connected, and the constant data that the constant generator produces is sent the waveform restore circuit, and waveform restore circuit output output pulse width is determined by constant data.Sampled data when the constant data that the constant generator produces equals to follow the tracks of.
Claims (4)
1, a kind of network synchronization slave clock phase-locked loop capable of integrating, should be that the dicyclo be made up of a loose coupling all-digital phase-locked loop and arrowband analog phase-locked look interconnection is from clock phase-locked loop from clock phase-locked loop, the input reference signal is added to the input of all-digital phase-locked loop, the output signal of all-digital phase-locked loop is as the analog phase-locked look input, analog phase-locked look output is as the output from clock phase-locked loop, two shared high-stability constant-temperature VCXOs of phase-locked loop (VCXO), it is characterized in that: described loose coupling all-digital phase-locked loop is by first pulse phase discriminator, data acquisition processing circuit, logic control circuit, the K counter, pulse addition and subtraction circuit (ID circuit), Fractional-N frequency device (÷ N) and high-stability constant-temperature VCXO (VCXO) are formed, first pulse phase discriminator compares the phase place of input reference signal and all-digital phase-locked loop output signal, output pulse width is proportional to the error pulse of two signal phase differences, error pulse produces control signal control K rolling counters forward after data acquisition processing circuit, the K counter converts two signal phase differences to and adds pulse or subtract pulse output, and through pulse addition and subtraction circuit (ID circuit) adding or deduction pulse in the train pulse of high-stability constant-temperature VCXO (VCXO) output, adjust loose coupling all-digital phase-locked loop output frequency, make all-digital phase-locked loop catch locking fast, all-digital phase-locked loop is added to pulse addition and subtraction circuit respectively with high-stability constant-temperature VCXO (VCXO) the working frequency source in the analog phase-locked look, K counting circuit and data acquisition processing circuit are made internal clocking.
2, according to claim 1 from clock phase-locked loop, it is characterized in that: described arrowband analog phase-locked look is by second pulse phase discriminator, loop filter, form with high-stability constant-temperature VCXO (VCXO) and 2N frequency divider (÷ 2N) that all-digital phase-locked loop is shared, second pulse phase discriminator compares the phase place of all-digital phase-locked loop output signal and analog phase-locked look output signal, export the analog DC voltage that is proportional to two signal phase differences through loop filter, the output frequency of control high-stability constant-temperature VCXO (VCXO).
3, according to claim 1 and 2 from clock phase-locked loop, it is characterized in that: described data acquisition processing circuit is by data acquisition circuit, the waveform restore circuit, the constant generator, bus switch and comparator five parts constitute, data acquisition circuit becomes the error pulse conversion of signals of first pulse phase discriminator output data and carries out the filtering interfering processing, the constant generator produces constant data, bus switch is controlled by logic control circuit, be used for gating sampled data or constant data, the waveform restore circuit then reverts to pulse control signal with the data of bus switch gating, and comparator comparison sampled data and constant data produce follows the tracks of and catch soon index signal; The sampled data of data acquisition circuit inserts bus switch on the one hand, inserts comparator simultaneously again, and the constant data of the generation of constant generator similarly inserts bus switch on the one hand, inserts comparator simultaneously again; Sampled data and regular data data compare at comparator, comparator output low level when equating, the indication loop enters lock-out state, comparator output high level when unequal, the indication loop enters trapped state, the input of restore circuit inserts the output of bus switch, the bus select signal of bus switch is used for bus and switches, be used for during the bus select signal low level of bus switch following the tracks of and catching, the data acquisition circuit bus data is connected with the waveform restore circuit, recover the pulse signal identical at waveform restore circuit output with the phase discriminator output pulse width, when the bus select signal of bus switch control end is in high level, the constant data that the constant generator the produces waveform restore circuit that veers away, the output of waveform restore circuit is by the impulse waveform of constant data decision, the sampled data when constant data equals to follow the tracks of.
4, according to claim 3 from clock phase-locked loop, it is characterized in that: logic control circuit is made of frequency monitoring circuit and control circuit, two inputs of frequency monitoring circuit add the input reference signal and from the output signal of clock, monitor having or not of two signals, logic control circuit then produces control signal and various condition indicative signal according to the output and the forced signal of frequency monitoring circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021157421A CN100349378C (en) | 2002-04-19 | 2002-04-19 | Network synchronization slave clock phase-locked loop capable of integrating |
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| CNB021157421A CN100349378C (en) | 2002-04-19 | 2002-04-19 | Network synchronization slave clock phase-locked loop capable of integrating |
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| CN100349378C true CN100349378C (en) | 2007-11-14 |
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| CNB021157421A Expired - Fee Related CN100349378C (en) | 2002-04-19 | 2002-04-19 | Network synchronization slave clock phase-locked loop capable of integrating |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101977105B (en) * | 2010-11-11 | 2013-02-20 | 大唐电信（成都）信息技术有限公司 | Automatic equalization phase-lock compensation method of time delay symmetric difference |
| CN102624384B (en) * | 2012-04-28 | 2014-06-11 | 中国科学院上海微系统与信息技术研究所 | Phaselocked loop with frequency self-scanning function |
| CN110391894B (en) * | 2019-08-30 | 2020-08-04 | 清华大学 | Receiving end of synchronous system, synchronous system and particle accelerator |
| CN115498998B (en) * | 2022-11-14 | 2023-02-21 | 南京邮电大学 | High-frequency crystal oscillator based on phase error automatic correction |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61121530A (en) * | 1984-11-16 | 1986-06-09 | Fujitsu Ten Ltd | Digital phase synchronization loop circuit |
| JPH0772186A (en) * | 1993-08-31 | 1995-03-17 | Hioki Ee Corp | Pll synchronization type measuring device |
| JPH09135240A (en) * | 1995-11-10 | 1997-05-20 | Kokusai Electric Co Ltd | Digital phase synchronizing circuit for multi-rate signal receiving circuit |
| JPH09261019A (en) * | 1996-03-27 | 1997-10-03 | Sanyo Electric Co Ltd | Synchronization circuit |
| US5896428A (en) * | 1995-09-20 | 1999-04-20 | Sony Corporation | Digital counter and digital phase locked loop circuit using same |
| CN1235424A (en) * | 1998-02-12 | 1999-11-17 | 日本电气株式会社 | Digital PLL circuit and clock generation method |
| CN1057882C (en) * | 1994-01-19 | 2000-10-25 | 日本无线株式会社 | Pll synthesizer and method of controlling the same |
| CN1275713A (en) * | 1999-05-28 | 2000-12-06 | 庄钠 | Digital magnetic compass system |
-
2002
- 2002-04-19 CN CNB021157421A patent/CN100349378C/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61121530A (en) * | 1984-11-16 | 1986-06-09 | Fujitsu Ten Ltd | Digital phase synchronization loop circuit |
| JPH0772186A (en) * | 1993-08-31 | 1995-03-17 | Hioki Ee Corp | Pll synchronization type measuring device |
| CN1057882C (en) * | 1994-01-19 | 2000-10-25 | 日本无线株式会社 | Pll synthesizer and method of controlling the same |
| US5896428A (en) * | 1995-09-20 | 1999-04-20 | Sony Corporation | Digital counter and digital phase locked loop circuit using same |
| JPH09135240A (en) * | 1995-11-10 | 1997-05-20 | Kokusai Electric Co Ltd | Digital phase synchronizing circuit for multi-rate signal receiving circuit |
| JPH09261019A (en) * | 1996-03-27 | 1997-10-03 | Sanyo Electric Co Ltd | Synchronization circuit |
| CN1235424A (en) * | 1998-02-12 | 1999-11-17 | 日本电气株式会社 | Digital PLL circuit and clock generation method |
| CN1275713A (en) * | 1999-05-28 | 2000-12-06 | 庄钠 | Digital magnetic compass system |
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| CN1452319A (en) | 2003-10-29 |
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