CN101098205A - Recovery device and control method for implementing arbitrary velocity business access signal - Google Patents
Recovery device and control method for implementing arbitrary velocity business access signal Download PDFInfo
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- CN101098205A CN101098205A CNA2006100866457A CN200610086645A CN101098205A CN 101098205 A CN101098205 A CN 101098205A CN A2006100866457 A CNA2006100866457 A CN A2006100866457A CN 200610086645 A CN200610086645 A CN 200610086645A CN 101098205 A CN101098205 A CN 101098205A
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- clock
- register
- data recovery
- recovery unit
- frequency
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
Abstract
The invention discloses a recover device for realizing free-speed service access signal and a relative control method, wherein the device comprises a clock and data recover unit, a controller, and a clock synthesizer, the controller via a bus bidirectional communicates with the clock and data recover unit, to set the clock synthesizer, to output accurate clock needed by the clock and data recover unit, the reference clock output by the clock synthesizer is directly input into the clock and data recover unit to be used. The invention uses common multiple calculation to automatically recognize the speed of access service, and uses service common-frequency or frequency doubling locking service, and high-frequency sampling to lock low-frequency service to realize accurate regeneration, to avoid error code and effectively avoid the frequency bias caused by special code structure.
Description
Technical field
The present invention relates to signal regeneration, the recovery of the communications field, relate in particular to a kind of recovery device and control method of arbitrary velocity business access signal within the specific limits.
Background technology
The demand that transport communication equipment exists multi-service to insert, loaded service signal in the optical transmission device for example generally comprises the business of various speed types.In some cases, equipment can not be known type of service in advance, and this just requires it to have adaptation function to service rate.
Receiving equipment in the optical transmission device generally comprises inserting Signal Processing: opto-electronic conversion, clock and data recovery (CDR), Business Processing.Adaptation function to service rate is mainly reflected on this part function of clock and data recovery, and promptly clock and data recovery need be realized the business of the various speed of self adaptation.
Existing CDR technology comprises three parts: CDR, CPU control unit and clock synthesizer as shown in Figure 1.The course of work: service signal is a high-speed serial signals through opto-electronic conversion, enters CDR, recovers data and clock; The CPU control unit can be provided with the job category of CDR and control the output clock of clock synthesizer according to type of service; The clock synthesizer is according to the setting of control unit, and the output reference clock uses to CDR.
The functional characteristics of prior art is to support two kinds of job categories: automatically lock with external control and lock.When automatically locking, support various fixed velocity service inputs.During the external control locking,,,, come locking service for CDR provides the external clock reference by CPU control unit control clock synthesizer according to known type of service.
There is following problem in prior art:
The first, under the situation of automatically locking, only support the input of fixed velocity service, but for the variable Rate business, such as having the business that inserts Handshake Protocol, speed is inconsistent when inserting when shaking hands speed and operate as normal, the situation of losing lock at this moment can occur.
The second, under the situation of automatically locking, for having the rule code word in some business, frequency deviation can take place, easily losing lock.Under the external control lock condition,, must know type of service in advance though there are not the problems referred to above.
Summary of the invention
The objective of the invention is, a kind of recovery device and control method that realizes arbitrary velocity business access signal is provided, solve the problem that prior art exists, overcome chip and automatically locked professional shortcoming, solve the access problem of variable Rate business.
The present invention can discern the speed of access service automatically by calculating the common multiple method, and adopt professional same frequency or frequency multiplication locking service, according to the Nyquist law, adopt the method for high frequency sampling locking low frequency business, can realize that accurately regeneration is professional, and error code not.
To achieve these goals, the present invention specifically is achieved in that
A kind of recovery device of realizing arbitrary velocity business access signal is characterized in that, comprising:
Clock and data recovery unit, control unit, clock synthesizer;
Described clock and data recovery unit is used to realize phase-locked loop, reads signal frequency, and losing lock alarm indication is provided, and supports lock function;
Described clock synthesizer is used for fixed frequency clock is carried out a times frequency division, and the clock of output frequency is supplied with the clock and data recovery unit and used;
Described control unit, be provided with the clock and data recovery unit mode of operation, read clock and data recovery unit internal register, and the concrete frequency of clock;
Described control unit carries out both-way communication by bus and clock and data recovery unit;
Described control unit is provided with the clock synthesizer by bus, the accurate clock that clock synthesizer output clock and data recovery unit is needed;
The reference clock of clock synthesizer output is directly inputted to the clock and data recovery unit, uses for the clock and data recovery unit.
Described clock synthesizer can be placed in the clock and data recovery unit;
Described bus adopts cpu bus.
Described clock synthesizer can be placed on outside the clock and data recovery unit;
Described bus adopts iic bus.
A kind of control method that realizes arbitrary velocity business access signal, the clock and data recovery unit is in the locking service pattern, sets a variable for register number, it is characterized in that, comprises the steps;
Step 4, according to the variate-value set, the service rate that reads be deposited into number with register that current variable-value equates in;
Step 5, obtain the common multiple of the data of first register in numbering and the register that current variable-value equates;
The common multiple that step 6, basis obtain is provided with reference clock, locking service, and then enters step 1.
Described common multiple equals the product of the numbering of data in the register and register.
The present invention has following advantage:
1, the present invention is the fixed frequency of identification services or the multiple frequency that comprises automatically;
2, the present invention not only can lock the business of all fixed rates of used CDR chip support;
3, and can lock the business of the professional and concrete specific coding structure of variable Rate;
4, effectively overcome the frequency deviation that the specific coding structure causes.
Description of drawings
Fig. 1 is a functional block diagram of the prior art;
Fig. 2 is an apparatus function block diagram of the present invention;
Fig. 3 is the control method flow chart that the professional regeneration of arbitrary velocity recovers;
Fig. 4 is embodiment one functional block diagram;
Fig. 5 is embodiment two functional block diagrams.
Embodiment
With reference to accompanying drawing, with detailed description specific embodiments of the present invention.
Wherein, 1 is the CDR chip, 2 is the CPU control unit, 3 is the clock synthesizer, and 4 is the VSC8123 chip, and 5 is AMCC186 chip etc., 6 is the clock synthesizer of VSC8123 chip internal, 7 is the ADN2812 chip, and 8 is the control system that AMCC186 chip etc. is formed, and 9 be the clock synthesizer of composition such as ICS525 chip.
As shown in Figure 2, the present invention is made up of three parts: clock and data recovery unit, control unit, clock synthesizer.
CDR except that having phase-locked loop, also has the function of the signal frequency of reading; Losing lock alarm LOL can be provided indication; Support automatically locks and the external control lock function;
The clock synthesizer can carry out a times frequency division to certain fixed frequency clock, exports the clock of various frequencies, supplies with CDR and uses;
Control unit, be provided with CDR mode of operation, read the CDR internal register, and the concrete frequency of clock.
Control unit and CDR communication are two-way among the present invention, and prior art is unidirectional usually, and control unit only is provided with CDR, and does not read CDR speed.
Annexation between the each several part of the present invention is as follows:
Control unit carries out both-way communication by cpu bus or iic bus to CDR, be that control unit can be provided with parameters such as CDR internal register, mode of operation, reference clock, operating rate, also can read parameters such as the interior register of CDR, mode of operation, service rate.
Control unit is provided with the clock synthesizer by cpu bus or iic bus again, the accurate clock that clock synthesizer output CDR is needed.
The reference clock of clock synthesizer output is directly inputted to CDR, uses for CDR.
Workflow of the present invention is as follows:
Initial condition is that CDR work is in certain locking service mode state, for ease of explanation, establishes variable k=1, but is not limited to variable k:
1. control unit reads the losing lock alarm, judges whether losing lock;
2. if losing lock not then reads in the CDR service rate in the register, according to current k value, data deposit among the register k, such as k=1, just deposit in the register 1, and k=2 deposits in the register 2, then end;
3. if losing lock reads service rate in the interior register of CDR;
4. according to current k value, the service rate that reads is deposited among the register k, enter step 5 then;
5. the common multiple of the data of counter register 1 in the register k; Such as k=3, the common multiple of data in the counter register 1,2,3 then; If k=1, then common multiple be exactly in the register 1 number * 1 or * 2 or * 4 etc.;
6. reference clock is set, locking service is set according to common multiple, and then enter step 1.
For business with fixed rate, STM4 business such as 622MHz, the present invention can be from step 1-3-4-5-6-1 circulation primary, the common multiple that calculates is 622 or 1244 or 2488 etc., control unit is according to this common multiple then, reference clock is set, and the CDR chip lock is set fixes on 622MHz frequency or 2488MHz frequency etc.Fixing on the 622MHz frequency if the CDR chip lock is set, then is the same frequency locking service; Fixing on the 2488MHz frequency if the CDR chip lock is set, then is the frequency multiplication locking service.
For the business of variable Rate, be example with the FDDI business, this traffic frequencies comprises the multiple speed between 12.5MHz and the 125MHz.For such business, it is professional that prior art only can be attempted lock with single a certain frequency, is to lock certainly.And the present invention has well solved this problem, through many circulations of step 1-3-4-5-6-1 of associating, control unit can detect these speed respectively, will adjust reference clock, locking service is set with their common multiple, according to the Nyquist law, adopt the method for high frequency sampling locking low frequency business, the business of can accurately regenerating, and error code not.
Resemble the business that 8B/10B coding waits the specific coding structure for comprising,, can cause that service rate descends, cause the CDR frequency deviation and losing lock occurs owing to be clocklike to connect 0 or connect 1.But after the losing lock alarm of the present invention's monitoring, can provide a fixed reference clock to CDR, and the fixed rate locking service of CDR with high frequency points is set, can not cause losing lock and error code.
Embodiment one, use chip VSC8123
There is the clock synthesizer VSC8123 inside, by register is set: Oscillator range setting[3:0] and Prescale ratewrite[3:0] frequency of clock is set, do not need to add the clock synthesizer.Control unit is by reading VSC8123 internal register Prescale rate read[7:4], can read professional rate value.
The functional block diagram of embodiment one as shown in Figure 4, control unit uses cpu chip AMCC186, control unit can be read and write VSC8123 by the CPU control line, the clock synthesizer is at the VSC8123 chip internal.
The course of work of embodiment one is as follows:
The first step, AMCC186 reads the losing lock alarm of VSC8123 chip, judges whether losing lock, if not losing lock then entered for second step, if losing lock then entered for the 3rd step;
In second step, read VSC8123 internal register Prescale rate read[7:4], according to current k value, data are put into the register k of AMCC186, then end;
The 3rd the step, AMCC186 is from VSC8123 internal register Prescale rate read[7:4] read the service rate value;
The 4th step according to current k value, was put into the service rate value among the AMCC186 register k, entered for the 5th step;
The 5th step, the common multiple of the data of counter register 1 in the register k; Such as k=3, the common multiple of data in the counter register 1,2,3 then; If k=1, then common multiple is exactly the number in the register 1;
In the 6th step, according to common multiple register in the VSC8123 is set: Oscillator range setting[3:0] and Prescalerate write[3:0], locking service is set, and then enter the first step.
Embodiment one can regenerate and recover fixed velocity service, the variable Rate business from 10Mb/s to the 2.7Gb/s speed range and have the business of specific coding form.
Embodiment two, use chip ADN2812
ADN2812 inside does not have clock, needs the outside that clock is provided.ADN2812 has losing lock alarm indication LOL, when LOL is a high level, is the losing lock alarm; When LOL is low high level, do not alarm.ADN2812 internal register CTRA[7,2] be used for telling the ADN2812 concrete frequency of reference clock of input.Register CTRA[1] be used for being provided with and read service rate and still use the reference clock locking service.From register FREQ0～FREQ2, can read service rate.
Control unit uses cpu chip AMCC186, and the clock synthesizer uses chip IC 525 and standard frequency crystal oscillator, and control unit is provided with IC525 by IIC, makes the adjustable clock of its output frequency, as shown in Figure 5.
The workflow of embodiment two is as follows:
The first step, AMCC186 detects losing lock alarm LOL state, judges whether losing lock;
In second step, if losing lock not, then AMCC186 reads service rate from ADN2812 internal register FREQ0～FREQ2, and according to current k value, data deposit among the register k, such as k=1, just deposit in the register 1, and k=2 deposits in the register 2, then end;
In the 3rd step, if losing lock, AMCC186 reads the service rate value from ADN2812 internal register FREQ0～FREQ2;
The 4th step according to current k value, deposited the service rate that reads among the register k in, entered for the 5th step then;
The 5th step, the common multiple of the data of counter register 1 in the register k; Such as k=3, the common multiple of data in the counter register 1,2,3 then; If k=1, then common multiple is exactly the number in the register 1;
In the 6th step, AMCC186 is provided with ADN2812 internal register CTRA[7,2 according to common multiple], and ADN2812 is set is the external control locking mode, and then enter the first step.
Embodiment two can regenerate and recover fixed velocity service, the variable Rate business from 12.7Mb/s to the 2.7Gb/s speed range and have the business of specific coding form.
Claims (5)
1 one kinds of recovery devices of realizing arbitrary velocity business access signal is characterized in that, comprising:
Clock and data recovery unit, control unit, clock synthesizer;
Described clock and data recovery unit is used to realize phase-locked loop, reads signal frequency, and losing lock alarm indication is provided, and supports lock function;
Described clock synthesizer is used for fixed frequency clock is carried out a times frequency division, and the clock of output frequency is supplied with the clock and data recovery unit and used;
Described control unit, be provided with the clock and data recovery unit mode of operation, read clock and data recovery unit internal register, and the concrete frequency of clock;
Described control unit carries out both-way communication by bus and clock and data recovery unit;
Described control unit is provided with the clock synthesizer by bus, the accurate clock that clock synthesizer output clock and data recovery unit is needed;
The reference clock of clock synthesizer output is directly inputted to the clock and data recovery unit, uses for the clock and data recovery unit.
2, the recovery device of realization arbitrary velocity business access signal as claimed in claim 1 is characterized in that:
Described clock synthesizer can be placed in the clock and data recovery unit;
Described bus adopts cpu bus.
3, the recovery device of realization arbitrary velocity business access signal as claimed in claim 1 is characterized in that:
Described clock synthesizer can be placed on outside the clock and data recovery unit;
Described bus adopts iic bus.
4, a kind of control method that realizes arbitrary velocity business access signal, the clock and data recovery unit is in the locking service pattern, sets a variable for register number, it is characterized in that, comprises the steps:
Step 1, control unit read the losing lock alarm, judge whether losing lock, if losing lock does not then enter step 2, otherwise enter step 3;
Step 2, read in the clock and data recovery unit service rate in the register, data are deposited in the register, finish then;
Step 3, read in the clock and data recovery unit service rate in the register;
Step 4, according to the variate-value set, the service rate that reads be deposited into number with register that current variable-value equates in;
Step 5, obtain the common multiple of the data of first register in numbering and the register that current variable-value equates;
The common multiple that step 6, basis obtain is provided with reference clock, locking service, and then enters step 1.
5, the control method of realization arbitrary velocity business access signal as claimed in claim 4 is characterized in that: described common multiple equals the product of the numbering of data in the register and register.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100866457A CN101098205A (en) | 2006-06-27 | 2006-06-27 | Recovery device and control method for implementing arbitrary velocity business access signal |
| PCT/CN2006/003786 WO2008003196A1 (en) | 2006-06-27 | 2006-12-30 | A recovery device and control method for realizing any rate service access signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100866457A CN101098205A (en) | 2006-06-27 | 2006-06-27 | Recovery device and control method for implementing arbitrary velocity business access signal |
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| Publication Number | Publication Date |
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| CN101098205A true CN101098205A (en) | 2008-01-02 |
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| CNA2006100866457A Pending CN101098205A (en) | 2006-06-27 | 2006-06-27 | Recovery device and control method for implementing arbitrary velocity business access signal |
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| CN (1) | CN101098205A (en) |
| WO (1) | WO2008003196A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012171256A1 (en) * | 2011-06-13 | 2012-12-20 | 中兴通讯股份有限公司 | Method and device for microwave transmission clock recovery |
| CN107766599A (en) * | 2016-08-22 | 2018-03-06 | 深圳市中兴微电子技术有限公司 | The prototype verification device of IC chip |
| CN110325973A (en) * | 2017-02-23 | 2019-10-11 | 思科技术公司 | More identity optical modules |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015081482A1 (en) * | 2013-12-03 | 2015-06-11 | Qualcomm Incorporated | Frequency aided clock recovery based on low speed information exchange mechanism |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720199B1 (en) * | 1999-09-21 | 2007-05-21 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Clock recovery |
| US6631144B1 (en) * | 1999-12-21 | 2003-10-07 | Intel Corporation | Multi-rate transponder system and chip set |
| CN1219357C (en) * | 2002-06-06 | 2005-09-14 | 华为技术有限公司 | Digital clock resetting device |
-
2006
- 2006-06-27 CN CNA2006100866457A patent/CN101098205A/en active Pending
- 2006-12-30 WO PCT/CN2006/003786 patent/WO2008003196A1/en active Application Filing
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012171256A1 (en) * | 2011-06-13 | 2012-12-20 | 中兴通讯股份有限公司 | Method and device for microwave transmission clock recovery |
| CN107766599A (en) * | 2016-08-22 | 2018-03-06 | 深圳市中兴微电子技术有限公司 | The prototype verification device of IC chip |
| CN110325973A (en) * | 2017-02-23 | 2019-10-11 | 思科技术公司 | More identity optical modules |
| CN110325973B (en) * | 2017-02-23 | 2023-07-18 | 思科技术公司 | Multi-identity optical module |
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| Publication number | Publication date |
|---|---|
| WO2008003196A1 (en) | 2008-01-10 |
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Application publication date: 20080102 |