WO2012171256A1

WO2012171256A1 - Method and device for microwave transmission clock recovery

Info

Publication number: WO2012171256A1
Application number: PCT/CN2011/078468
Authority: WO
Inventors: 张丽
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-06-13
Filing date: 2011-08-16
Publication date: 2012-12-20
Also published as: CN102833064B; CN102833064A

Abstract

Disclosed are a method and device for microwave transmission clock recovery. In the device, a standard clock generation unit generating a standard clock signal which is consistent with the clock frequency and duty cycle that the current sending end uses according to the clock information that the current sending end uses; under the control of an air interface clock signal sent from an air interface clock receiving unit, a clock frequency extraction unit adjusting the standard clock signal to obtain a first clock signal which is consistent with the frequency of the air interface clock signal; and a local clock adjustment unit adjusting a local clock signal based on the first clock signal to make same track the first clock signal. Reducing the quantity of PLLs used saves on the costs of the microwave communication system; and homogeneous standard clock signals are inputted into a phase adjustable PPL module, avoiding loss of lock in the PLL and the PLL resetting process caused thereby. Therefore, the present invention improves the stability of the microwave communication system, and simplifies the complexity thereof.

Description

Method and device for clock recovery of microwave transmission

The present invention relates to the field of microwave communication technologies, and in particular, to a clock recovery method and apparatus for microwave transmission. Background technique

Microwave communication is communication using electromagnetic waves having a wavelength between 0.1 mm and 1 m. Microwave communication does not require a solid medium. Microwave transmission can be used when the distance between two points is unobstructed. For example: between the satellite and the ground, between the two buildings in the city, and the large open area where the cable cannot be actually laid. Such as: desert, grass and lakes. Microwave communication has the advantages of large capacity, good quality, convenient networking, and strong ability to resist disasters. It is an important means of communication. However, because microwave communication is highly susceptible to weather, such as fog, sand, etc., microwave communication systems need to select different working bandwidths and clock frequencies under different weather conditions to ensure transmission quality. For a communication system whose clock frequency may change at any time, it is very important to ensure that the clock signals at the transmitting end and the receiving end are consistent, stable and reliable.

In the existing microwave communication system, the receiving end clock recovery circuit is as shown in FIG. 1, and includes: a clock extraction module, a clock division module l~n, a PLL (Phase Locked Loop) frequency multiplication module l~n, Fractional frequency division module l~n, clock selection module, clock phase discrimination module, clock adjustment module and protection module. Under different environmental conditions, the microwave communication system operates at different bandwidths and clock frequencies, such as clock frequencies of 7 MHz, 14 MHz, 28 MHz, 49 MHz, and the like. Suppose there are n different clock frequencies. At each clock frequency, the air interface clock signals extracted by the clock extraction module from the data signal frames received from the air are usually not uniform, and then the n clock division modules correspond to them. The uneven clock signal is divided, and the degree of unevenness is weakened. Among them, one clock frequency dividing module corresponds to one clock frequency. The division ratios of the n clock division modules are different. PLL The frequency multiplication module multiplies the clock signal obtained by weakening the degree of unevenness. Next, the fractional frequency division module uses a Sigma-Ddta algorithm to implement a fractional frequency dividing circuit according to the actual application environment, and divides the clock signal after the frequency multiplication into A uniform frequency, such as 50Hz, the clock selection module selects one of the multiple clock signals. If the clock frequency of the current system is 7ΜΗζ, the 50Hz signal corresponding to the frequency division of the 7MHz clock is selected and output to the clock phase detection module. The module uses the 50Hz signal as the reference clock and compares it with the 50Hz obtained by dividing the local clock of the microwave communication system to obtain the phase-detection value. The phase-adjusting value is used to control the clock adjustment module to adjust the local clock, so that the local clock tracks the received air interface clock signal. That is, the clock of the sender. The protection module detects the clock output from the PLL multiplier module in real time. Once the PLL is found to be abnormal, the PLL is reset when no clock is sent.

At present, the clock recovery circuit used in the microwave communication system has the following drawbacks: The number of PLL multiplying modules used is large; after the uneven clock signal is sent to the PLL multiplying module, the PLL may lose lock and affect the quality of the recovered clock signal. The clock recovery circuit requires a protection module to detect the clock output from the PLL multiplier module in real time. Once the PLL is found to be abnormal, the PLL needs to be reset when no clock is sent. The PLL is normally required from reset to normal operation. A few milliseconds, this time leads to the phase change value obtained, so it is necessary to increase the corresponding filtering mechanism. Summary of the invention

The technical problem to be solved by the present invention is to provide a clock recovery method and device for microwave transmission, which overcomes the defects in the prior art that the phase-locked loop is used in a large number and is prone to loss of lock, resulting in instability of the microwave communication system.

The technical solution adopted by the present invention is a clock recovery device for microwave transmission, comprising: an air interface clock receiving unit, a standard clock generating unit, a clock frequency extracting unit, and a local clock adjusting unit;

The standard clock generation unit is configured to: generate a standard clock signal consistent with the clock frequency and duty ratio used by the current transmitting end according to the clock information used by the current transmitting end, and input to the clock frequency. Extraction unit

The clock frequency extraction unit is configured to: under the control of the air interface clock signal sent by the air interface clock receiving unit, adjust the input standard clock signal to obtain a first clock signal that is consistent with the frequency of the air interface clock signal, and input the signal to the local clock adjustment unit. ;

The local clock adjustment unit is configured to: adjust the local clock signal based on the first clock signal to track the first clock signal.

Further, the clock frequency extraction unit includes: a phase adjustable PPL module, a phase adjustment control module, a first comparison module, and a second comparison module;

The first comparison module is configured to: compare the air interface clock signal received by the air interface clock receiving unit with a standard clock signal generated by the standard clock generating unit, and output phase difference information between the air interface clock signal and the standard clock signal, Send to the phase adjustment control module;

The second comparison module is configured to: compare the air interface clock signal received by the air interface clock receiving unit with the first clock signal output by the phase adjustable PPL module, and output the adjustment timing information to the phase adjustment control module;

The first clock signal is initially identical to the standard clock signal, and the phase adjustment control module is configured to: adjust the phase according to the phase difference information and the adjustment timing information

The first clock signal output by the PPL module is adjusted to match the frequency of the first clock signal with the air interface clock signal.

Further, the first comparison module and the second comparison module are buffers;

The phase difference information of the air interface clock signal and the standard clock signal and the adjustment timing information are reflected by the number of currently stored data output by the buffer.

Further, the standard clock generating unit includes: a clock signal source module and a PLL synthesizing module; wherein, the clock signal source module is configured to: generate a reference clock signal and input the reference clock signal to the PLL synthesizing module;

The PLL synthesis module is set to: according to the clock information used by the current sender, the reference clock The signal is converted to a standard clock signal that is consistent with the clock frequency and duty cycle used by the transmitting end. Further, the device further includes: selecting a configuration unit;

Select the configuration unit to set: Real-time knowledge of the clock information used by the current sender, and configure the PLL synthesis module and the phase-adjustable PLL module according to the clock information used by the current transmitter.

Further, the device further includes: a frequency dividing unit;

The first clock signal is divided by the frequency dividing unit and input to the local clock adjusting unit, and the local clock signal is fed back to the frequency dividing unit for frequency division and then input to the local clock adjusting unit.

Based on the foregoing apparatus, the present invention further provides a clock recovery method for microwave transmission, including: generating a standard clock signal consistent with a clock frequency and a duty ratio used by a current transmitting end according to clock information used by a current transmitting end;

Adjusting the standard clock signal under the control of the received air interface clock signal to obtain a first clock signal that is consistent with the frequency of the air interface clock signal;

Adjusting the local clock signal based on the first clock signal to track the first clock signal. Further, under the control of the received air interface clock signal, adjusting the standard clock signal to obtain an air interface clock signal The first clock signal having the same frequency includes: after comparing the received air interface clock signal with the standard clock signal, determining phase difference information between the air interface clock signal and the standard clock signal; and receiving the received air interface clock signal After the first clock signal is aligned, the adjustment timing information is determined;

The first clock signal is initially matched with the standard clock signal, and the first clock signal is adjusted according to the phase difference information and the adjustment timing information, so that the first clock signal and the air interface clock signal have the same frequency. .

Further, the generating, according to the clock information used by the current sending end, a standard clock signal that is consistent with the clock frequency and the duty ratio used by the current transmitting end, including: The reference clock signal is converted into a standard clock signal that is consistent with the clock frequency and duty cycle used by the transmitting end according to the clock information used by the current transmitting end.

Further, before the standard clock signal that is consistent with the clock frequency and the duty ratio used by the current transmitting end is generated according to the clock information used by the current transmitting end, the method further includes: real-time learning the clock information used by the current transmitting end.

With the above technical solution, the present invention has at least the following advantages:

In the method and device for recovering the microwave transmission of the present invention, since the number of using the PLL is reduced, the cost of the microwave communication system is saved; and the standard clock signal of the hook is input to the phase-adjustable PLL module, thereby avoiding the loss of the PLL The lock and the initiated PLL reset process, therefore, the present invention improves the stability of the microwave communication system; the present invention does not require the design of the protection module to protect the PLL, and the filtering mechanism, which simplifies the complexity of the microwave communication system. DRAWINGS

1 is a schematic structural diagram of a clock recovery circuit of a receiving end in a conventional microwave communication system; FIG. 2 is a schematic structural diagram of a clock recovery apparatus for microwave transmission according to a first embodiment of the present invention; FIG. 3 is the first embodiment of the present invention; FIG. 4 is a schematic diagram showing a comparison between a hollow port clock signal and a adjusted first clock signal according to the first embodiment of the present invention; FIG.

5 is a schematic structural diagram of a clock recovery apparatus for microwave transmission according to a second embodiment of the present invention; FIG. 6 is a schematic structural diagram of a clock recovery apparatus for microwave transmission according to a third embodiment of the present invention; FIG. 7 is a schematic diagram of microwave transmission according to a fourth embodiment of the present invention. Flow chart of the clock recovery method. DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

A first embodiment of the present invention, a clock recovery device for microwave transmission, as shown in FIG. 2, The following components are included: an air interface clock receiving unit 10, a standard clock generating unit 20, a clock frequency extracting unit 30, and a local clock adjusting unit 40;

The standard clock generating unit 20 generates a standard clock signal that matches the frequency and duty ratio of the clock signal used by the current transmitting end based on the clock information used by the current transmitting end, and inputs it to the clock frequency extracting unit 30. The standard clock generating unit 20 specifically includes: a clock signal source module 21 and a PLL synthesizing module 22; wherein, the clock signal source module 21 can adopt a voltage-controlled clock oscillator chip of the RAKON company Oscillator Specification: E5176LF. The PLL synthesis module 22 can be used with the company's chip CDCE706.

The clock signal source module 21 generates a reference clock signal input to the PLL synthesizing module 22. The reference clock can be arbitrarily selected and then multiplied or divided by the PLL synthesis module 22 to obtain a standard clock signal that is consistent with the clock frequency and duty cycle used by the current transmitter. The clock information used by the current transmitting end can be set in the PLL synthesizing module 22 as a basis for converting the reference clock signal. The clock information used by the current transmitting end is actually the theoretical value of the clock information used by the current transmitting end, and the clock information includes the frequency and the duty ratio.

The clock frequency extraction unit 30 adjusts the input standard clock signal under the control of the air interface clock signal sent from the air interface clock receiving unit 10 to obtain a first clock signal that matches the frequency of the air interface clock signal, and inputs the signal to the local clock adjustment unit 40. . The air interface clock receiving unit 10 can use Provigent's PVG610 chip.

The local clock adjustment unit 40 adjusts the local clock signal based on the first clock signal to track the first clock signal, i.e., to match the frequency, phase, and duty cycle of the local clock signal with the first clock signal. The local clock adjustment unit 40 specifically includes: a clock phase discrimination module 41 and a clock adjustment module 42; wherein the clock adjustment module 42 can use the AD5541 chip of the ANALOG DEVICES company.

The clock phase discrimination module 41 is configured to determine a phase difference between the first clock signal and the local clock signal, and then the clock adjustment module 42 adjusts and outputs the local clock signal according to the phase difference. As shown in FIG. 2, the clock frequency extraction unit 30 specifically includes: a phase-adjustable PPL module 31, a phase adjustment control module 32, a first comparison module 33, and a second comparison module 34;

The air interface clock signal received by the air interface clock receiving unit 10 is compared with the standard clock signal generated by the standard clock generating unit 20 and input to the first comparison module 33. The first comparison module 33 outputs the phase difference between the air interface clock signal and the standard clock signal. The information is sent to the phase adjustment control module 32.

The air interface clock signal received by the air interface clock receiving unit 10 is compared with the first clock signal output by the phase adjustable PPL module 31 to the second comparison module 34, and the second comparison module 34 outputs the adjustment timing information and sent to the phase adjustment. Control module 32. The first comparison module 33 and the second comparison module 34 can be implemented by using the first buffer and the second buffer respectively, and the specific connection diagram is shown in FIG. 3.

The first clock signal is initially identical to the standard clock signal, that is, the frequency, the phase, and the duty ratio are the same. The phase adjustment control module 32 determines the phase difference information of the air interface clock signal and the standard clock signal, and adjusts the timing information. The first clock signal output by the phase adjustable PPL module 31 is adjusted to match the first clock signal with the air interface clock signal frequency. The clock information used by the current transmitting end can be set in the phase adjustable PPL module 31 as a basis for phase locking.

Here is a detailed introduction to the principle and process of adjusting the first clock signal:

As shown in FIG. 3, when the device is powered on, the standard clock signal is directly output to the write clock port wr_clk of the first buffer, and the standard clock signal is input as the first clock signal to the read clock port of the second buffer. Rd_clk, the air interface clock signal is input to the read clock port rd_clk of the first buffer and the write clock port wr_clk of the second buffer.

It is assumed that n data is pre-stored in the first buffer, and the first buffer can store at most m data, 0<n<m. The first buffer performs a data write operation under the control of a standard clock signal, which is referred to as a write operation, and performs a data read operation under the control of the air interface clock signal, which is referred to as a read operation. If the standard clock signal has a lower frequency than the air interface clock signal, After a period of time, the first buffer is stored. The number of stored data will become 0, that is, empty; if the standard clock signal is higher than the air interface clock signal, after a period of time, the number of data stored in the first buffer will become m, that is, full. The number of data stored in the first buffer is reported to the phase adjustment control module 32 through the cnt (count) port in real time, and the number of reported data can reflect the phase difference information between the air interface clock signal and the standard clock signal. When the number of data reported by the first buffer is empty, the phase adjustment control module 32 determines that the standard clock signal is lower than the frequency of the air interface clock signal, and the frequency of the first clock signal needs to be increased; the phase adjustment control module 32 When the number of data reported by the first buffer is full, according to which it is determined that the standard clock signal is higher than the frequency of the air interface clock signal, the frequency of the first clock signal needs to be lowered, that is, the frequency of the first clock signal is determined. Adjust the direction.

It is assumed that n data is pre-stored in the second buffer, n<m, the second buffer performs a data read operation under the control of the first clock signal, and performs a write operation under the control of the air interface clock signal, and second The buffer reports the number of data stored therein to the phase adjustment control module 32 through the _cn t port in real time. When the frequency of the air interface clock signal is different from the frequency of the first clock signal, the number of data reported by the second buffer changes, that is, the timing of the adjustment comes. As long as the phase adjustment control module 32 receives the number of data reported by the second buffer is not n, that is, a change occurs, the phase adjustment control module 32 adjusts the first clock signal according to the frequency adjustment direction determined by the first buffer. , making the first clock signal coincide with the frequency of the air interface clock signal. Specifically, during the adjustment, the period of the first clock signal, the duty ratio, and the like are adjusted. For example: In Figure 4, when the pulse of the air interface clock signal is continuously vacant, the frequency of the first clock signal needs to be reduced. The original period of the first clock signal is T=10 ns, the high pulse lasts for 5 ns in one cycle, and the low pulse lasts for 5 ns. , the high pulse becomes 5.5 ns in one cycle from the start of the adjustment, the low pulse lasts 5 ns, and the period is extended to 10.5 ns, according to which, until the number of data reported by the second buffer returns to n, that is, No change occurs, and the adjustment of the first clock signal is stopped.

The first clock signal gradually approaches the air interface clock signal after the above adjustment, as shown in FIG. 4, although the length of some adjusted periods is different from other periods, the ratio can be guaranteed. For a longer period of time, the first clock signal has the same number of pulses as the air interface clock signal, that is, the frequencies of the two signals are the same. In practice, the specific value of the relatively long period of time is related to the storage capacity of the first and second buffers.

It should be noted that, as an alternative embodiment, the standard clock signal may be input to the read clock port of the first buffer, and the air interface clock signal may be input to the write clock port of the first buffer; the first clock signal may be input to the write of the second buffer. The clock port, the air interface clock signal can be input to the read clock port of the second buffer.

A second embodiment of the present invention, a clock recovery device for microwave transmission, as shown in FIG. 5, is substantially the same as the device in the first embodiment, except that the device in the embodiment further includes: The unit 50 is configured to learn the clock information used by the current transmitting end in real time, and configure the PLL synthesizing module and the phase adjustable PLL module according to the clock information used by the current transmitting end.

In order to adapt to different environmental conditions, the clock frequency used by the microwave communication system may be changed between 7MHz, 14MHz, 28MHz, 49MHz, etc., and once the clock frequency adopted by the transmitting end changes, the selection configuration unit 50 knows the current situation in real time. The clock information used by the transmitting end is actually the theoretical value of the clock information used by the current transmitting end. The clock information includes the frequency and the duty ratio, and is used to configure the PLL synthesizing module as a basis for converting the reference clock signal; On the other hand, it is used to configure the phase-tunable PLL module as a phase-locked basis.

A third embodiment of the present invention, a clock recovery device for microwave transmission, as shown in FIG. 6, is substantially the same as the device in the second embodiment, except that the device in the embodiment further includes: Unit 60. The first clock signal outputted by the phase-adjustable PLL module 31 is divided by the frequency dividing unit 60 and input to the local clock adjusting unit 40. The final output local clock signal must also be fed back to the frequency dividing unit 60 for frequency division and input to the local. Clock adjustment unit 40. In this embodiment, considering that the selection configuration unit 50, the clock frequency extraction unit 30, and the clock phase detection module 41 are all implemented by an FPGA (Field Programmable Gate Array), the frequency of the first clock signal and the local clock signal exceeds the clock. The range that the phase module 41 can handle, so the same score must be performed first. Frequency processing, preferably, is divided to 50 Hz.

Based on the device in the second embodiment, the fourth embodiment of the present invention provides a clock recovery method for microwave transmission. As shown in FIG. 7, the following specific steps are included:

5101. Obtain the clock information used by the current sender in real time.

S102: Generate a standard clock signal that matches the frequency and duty ratio of the clock signal used by the current transmitting end according to the clock information used by the current transmitting end.

Specifically, the reference clock signal is converted into a standard clock signal that is consistent with a clock frequency and a duty ratio used by the transmitting end according to clock information used by the current transmitting end.

5103. Under the control of the received air interface clock signal, adjust the standard clock signal to obtain a first clock signal that is consistent with the frequency of the air interface clock signal.

Specifically, after comparing the received air interface clock signal with the standard clock signal, determining phase difference information between the air interface clock signal and the standard clock signal; determining the adjustment timing after comparing the received air interface clock signal with the first clock signal Information

The first clock signal is initially matched with the standard clock signal, that is, the frequency, the phase, and the duty ratio are all consistent, and the first clock signal is adjusted according to the phase difference information and the adjustment timing information, The first clock signal is made to coincide with the air interface clock signal frequency.

5104. Adjust the local clock signal based on the first clock signal to track the first clock signal.

The technical means and functions of the present invention for achieving the intended purpose can be more deeply and specifically understood by the description of the specific embodiments. However, the accompanying drawings are only for the purpose of illustration and description, and are not intended to limit. Industrial applicability

The invention saves the cost of the microwave communication system by reducing the number of PLLs; inputting a uniform standard clock signal to the phase-adjustable PLL module, avoiding the loss of the PLL and the PLL reset process caused by the PLL, therefore, the present invention improves Stability of a microwave communication system; the present invention There is no need to design a protection module to protect the PLL and filter mechanism, which simplifies the complexity of the microwave communication system.

Claims

Claim

A clock recovery device for microwave transmission, comprising: an air interface clock receiving unit, a standard clock generating unit, a clock frequency extracting unit, and a local clock adjusting unit; wherein, the standard clock generating unit is configured to: according to the current transmitting end The clock information used generates a standard clock signal that is consistent with the clock frequency and duty ratio used by the current transmitting end, and is input to the clock frequency extracting unit;

2. The clock recovery device for microwave transmission according to claim 1, wherein the clock frequency extraction unit comprises: a phase adjustable PPL module, a phase adjustment control module, a first comparison module, and a second comparison module; among them,

The first clock signal is initially matched with the standard clock signal, and the phase adjustment control module is configured to: adjust the first clock signal output by the phase-adjustable PPL module according to the phase difference information and the adjustment timing information. , making the first clock signal coincide with the frequency of the air interface clock signal.

3. The clock recovery apparatus for microwave transmission according to claim 2, wherein: The first comparison module and the second comparison module are buffers;

The clock recovery device of the microwave transmission according to claim 1, wherein the standard clock generation unit comprises: a clock signal source module and a PLL synthesis module; wherein the clock signal source module is configured to: generate a reference clock signal and Inputting the reference clock signal to a PLL synthesis module;

The PLL synthesis module is configured to: convert the reference clock signal into a standard clock signal that is consistent with the clock frequency and duty ratio used by the transmitting end according to clock information used by the current transmitting end.

The clock recovery device of the microwave transmission according to claim 4, wherein the device further comprises: a selection configuration unit;

The clock recovery device of the microwave transmission according to claim 1 or 2 or 3 or 4 or 5, wherein the device further comprises: a frequency dividing unit;

A clock recovery method using the apparatus of claim 1, characterized in that it comprises:

Generating a standard clock signal consistent with the clock frequency and duty ratio used by the current transmitting end according to the clock information used by the current transmitting end;

Adjusting the local clock signal based on the first clock signal to track the first clock signal

The clock recovery method for microwave transmission according to claim 7, wherein the standard clock signal is adjusted under the control of the received air interface clock signal to obtain a frequency consistent with the air interface clock signal frequency. A clock signal, including:

After comparing the received air interface clock signal with the standard clock signal, determining phase difference information between the air interface clock signal and the standard clock signal; and comparing the received air interface clock signal with the first clock signal, determining adjustment Timing information;

The clock recovery method of the microwave transmission according to claim 7, wherein the generating, according to the clock information used by the current transmitting end, a standard clock signal that is consistent with a clock frequency and a duty ratio used by the current transmitting end, includes:

The reference clock signal is converted into a standard clock signal that coincides with the clock frequency and duty cycle used by the transmitting end according to the clock information used by the current transmitting end.

The clock recovery method for microwave transmission according to claim 7 or 8 or 9, wherein the standard clock signal corresponding to the clock frequency and the duty ratio used by the current transmitting end is generated according to the clock information used by the current transmitting end. The method further includes: obtaining the clock information used by the current sending end in real time.