CN111371523B

CN111371523B - Clock signal processing device and method

Info

Publication number: CN111371523B
Application number: CN201811595138.5A
Authority: CN
Inventors: 刘晓露; 李超林; 赵国良
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2018-12-25
Filing date: 2018-12-25
Publication date: 2023-03-14
Anticipated expiration: 2038-12-25
Also published as: CN111371523A

Abstract

The embodiment of the invention discloses a clock signal processing device, which comprises: the tracking circuit is connected with the clock circuit and used for receiving the clock signal input by the clock circuit and generating a clock signal at the current moment based on the clock signal received at the previous moment; the control circuit is connected with the tracking circuit and used for controlling the tracking circuit to input a clock signal at the current moment into the clock circuit when the clock circuit is unlocked; the tracking circuit inputs a clock signal of the clock circuit and is used for recovering clock locking of the clock circuit. The embodiment of the invention also provides a clock signal processing method.

Description

Clock signal processing device and method

Technical Field

The present invention relates to the field of wireless communication technologies, and in particular, to a clock signal processing apparatus and method.

Background

In current communication systems, both wired and wireless, a clock synchronization system is used. The reference clock is transmitted from a host end to each device in the system through a network; in order to improve the stability of each device in the system and to improve the flexibility of the devices in the system for different applications, more than one reference clock is generally input into the devices. For example, when the reference clock is switched, the phase-locked loop loses the input clock, so that the phase-locked loop is transiently unlocked, and the output frequency changes abruptly. Therefore, how to maintain the output stability of the integrated circuit or ensure the smooth switching of the output of the integrated circuit when the clock signal of the clock circuit is suddenly interrupted or suddenly changed becomes a problem to be solved.

Disclosure of Invention

The embodiment of the invention provides a signal processing device and a signal processing method.

The technical scheme of the embodiment of the invention is realized as follows:

an embodiment of the present invention provides a signal processing apparatus, including:

the tracking circuit is connected with the clock circuit and used for receiving the clock signal input by the clock circuit and generating a clock signal at the current moment based on the clock signal received at the previous moment;

the control circuit is connected with the tracking circuit and used for controlling the tracking circuit to input a clock signal at the current moment into the clock circuit when the clock circuit is unlocked; the tracking circuit inputs a clock signal of the clock circuit and is used for recovering clock locking of the clock circuit.

In the foregoing solution, the tracking circuit includes: the device comprises a first signal processor, a storage circuit and a second signal processor; wherein the content of the first and second substances,

the first signal processor is connected with the clock circuit and used for extracting the signal parameters of the clock signal at the current moment when the clock circuit is not unlocked;

the storage circuit is connected with the first signal processor and used for storing the signal parameters of the clock signal at the previous moment;

and the second signal processor is connected with the clock circuit and used for obtaining the clock signal of the current moment according to the signal parameter of the clock signal of the previous moment.

In the above scheme, the tracking circuit further includes a comparison circuit and an algorithm control circuit, wherein the comparison circuit includes:

the first input end is connected with the first signal processor and used for receiving the signal parameters of the clock signal at the current moment;

the second input end is connected with the output end of the storage circuit and used for receiving the signal parameter of the stored clock signal sent by the storage circuit;

the output end is respectively connected with the first input end and the second input end and is used for outputting a comparison result of the signal parameter of the clock signal at the current moment and the stored signal parameter of the clock signal;

and the algorithm control circuit is connected with the output end at one end and the storage circuit at the other end and is used for controlling the signal parameters of the clock signals stored in the storage circuit to be equal to the signal parameters of the clock signals at the current moment according to the comparison result and a preset algorithm rule.

In the above solution, the tracking circuit further includes:

the third signal processor is connected with the clock circuit and used for extracting the signal parameters of the clock signal at the current moment and counting the signal parameters of the clock signal at the current moment received in a specified number of periods if the clock signal input by the clock circuit is received;

the control circuit is further configured to control the tracking circuit not to input the clock signal at the current time to the clock circuit if a difference between signal parameters of the clock signals counted in two adjacent periods is smaller than a threshold.

In the above solution, the device further comprises at least one buffer,

the at least one buffer is connected between the tracking circuit and the clock circuit for buffering clock signals transmitted between the tracking circuit and the clock circuit.

The embodiment of the invention also provides a clock signal processing method, which comprises the following steps:

receiving a clock signal input by the clock circuit;

generating a clock signal of a current time based on a clock signal received at a previous time;

and when the received clock circuit is unlocked, inputting the clock signal at the current moment to the clock circuit so as to restore the clock locking of the clock circuit.

In the above solution, the receiving a clock signal input by the clock circuit and generating a clock signal at a current time based on a clock signal received at a previous time includes:

extracting the signal parameter of the clock signal at the current moment when the clock circuit is not unlocked;

storing a signal parameter of a clock signal at a previous time;

and obtaining the clock signal of the current moment according to the signal parameter of the clock signal of the previous moment.

In the foregoing solution, the method further includes:

receiving a signal parameter of a clock signal at the current moment;

receiving signal parameters of the stored clock information;

outputting a comparison result of the signal parameter of the clock signal at the current moment and the stored signal parameter of the clock signal;

and controlling the signal parameter of the stored clock signal to be equal to the signal parameter of the clock signal at the current moment according to the comparison result and a preset algorithm rule.

In the foregoing solution, the method further includes:

if the clock signal input by the clock circuit is received, extracting the signal parameter of the clock signal at the current moment, and counting the signal parameters of the clock signal at the current moment received in a specified number of periods;

and if the difference value between the signal parameters of the clock signals counted in two adjacent periods is smaller than a threshold value, controlling the tracking circuit not to input the clock signal at the current moment into the clock circuit.

The signal processing apparatus and method provided in the above embodiments, wherein the apparatus includes: the tracking circuit is connected with the clock circuit and used for receiving the clock signal input by the clock circuit and generating a clock signal at the current moment based on the clock signal received at the previous moment; the control circuit is connected with the tracking circuit and used for controlling the tracking circuit to input a clock signal at the current moment into the clock circuit when the clock circuit is unlocked; the tracking circuit inputs a clock signal of the clock circuit and is used for recovering clock locking of the clock circuit. The device can generate the clock signal of the current moment when the clock circuit is unlocked based on the clock signal received by the clock circuit at the previous moment, and the clock signal is input to the clock circuit in the unlocked state to be used for the clock circuit to recover clock locking, so that the clock circuit can continuously obtain the clock signal of the current moment of the clock circuit in the unlocked state, and the clock signal of the current moment is generated by the clock signal of the previous moment, therefore, the clock signal of the current moment output by the clock circuit can be a normal clock signal, thereby providing a stable clock signal for the integrated circuit with the clock circuit, and further ensuring the stability of the clock circuit to the output of the integrated circuit or the smooth switching of the output when the clock signal is interrupted or changed sharply.

Drawings

Fig. 1 is a schematic structural diagram of a clock signal processing apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an alternative clock signal processing apparatus according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a clock signal processing method according to an embodiment of the present invention;

FIG. 4a is a schematic diagram illustrating a clock circuit in a locked state according to an embodiment of the present invention;

FIG. 4b is a schematic diagram illustrating a circuit schematic of a clock circuit in an unlocked state according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating a method for adjusting a signal parameter of a clock signal according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating a processing method after a clock circuit exits from being unlocked according to an embodiment of the present invention;

fig. 7 is a circuit diagram of a phase locked loop according to an embodiment of the invention.

Detailed Description

In order to make the technical solutions of the present invention better understood by those skilled in the art, the technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as shown or described. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The objectives, features, and advantages of the present invention will be further explained with reference to the accompanying drawings, in which embodiments of the invention are described, it being understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The technical scheme of the invention is further elaborated by combining the drawings and the specific embodiments in the specification.

Fig. 1 is a schematic structural diagram of a clock signal processing apparatus according to an embodiment of the present invention, and as shown in fig. 1, the clock signal processing apparatus 1 includes: a tracking circuit 10 and a control circuit 11; wherein the content of the first and second substances,

the tracking circuit 10 is connected to the clock circuit 12, and configured to receive a clock signal input by the clock circuit 12 and generate a clock signal at a current time based on the clock signal received at a previous time;

the control circuit 11 is connected to the tracking circuit 10, and configured to control the tracking circuit 10 to input a clock signal at a current time, which is generated based on a clock signal received at a previous time, to the clock circuit 12 when the clock circuit 12 is unlocked; wherein, the tracking circuit 10 inputs the clock signal of the clock circuit 12 for the clock circuit 12 to perform clock locking recovery.

Here, the clock signal is a signal having a timer function and ensuring that the related electronic components operate synchronously.

Here, the clock circuit 12 refers to a circuit capable of generating a clock signal, and generally, the clock circuit is generally composed of a crystal oscillator, a crystal oscillation control chip, and a capacitor. Usually, an integrated circuit is mostly integrated with a clock circuit 12, for example, a chip with electronic components synchronously processing has the clock circuit 12 therein, and the clock circuit provides a clock signal for the integrated circuit to maintain normal operation between the electronic components inside the integrated circuit.

Here, the tracking circuit 10 is connected to the clock circuit 12, and while the clock circuit 12 provides a clock signal for the integrated circuit, the tracking circuit 10 can also acquire the clock signal sent by the clock circuit 12, that is, the tracking circuit 10 is configured to receive the clock signal input by the clock circuit 12, and in a normal state of the clock circuit, that is, in a locked state of the clock circuit, the tracking circuit 10 will always track the clock signal provided by the clock circuit 12 for the integrated circuit. Based on this, the tracking circuit 10 can generate a clock signal at the present time based on a clock signal received at the previous time.

Further, the control circuit 11 is connected to the tracking circuit 10, and actually, the output end of the tracking circuit 10 is connected to the clock circuit 12, and when the clock circuit 12 is unlocked, the control circuit controls the clock signal of the tracking circuit 10 at the current time to be input to the clock circuit 12, where the clock signal input to the clock circuit 12 by the tracking circuit 10 is used for recovering the clock locking performed by the clock circuit 12.

It should be added that, the clock signal for controlling the tracking circuit 10 at the current time when the clock circuit 12 is out-of-lock is received and input to the clock circuit 12, including: receiving an out-of-lock signal provided by an out-of-lock detection circuit in the clock circuit 12, controlling the tracking circuit 10 to input a clock signal at the current time to the clock circuit 12 based on the out-of-lock signal.

In this embodiment, the tracking circuit 10 is configured to be connected to the clock circuit 12, and configured to receive a clock signal input by the clock circuit 12 and generate a clock signal at a current time based on a clock signal received at a previous time; the control circuit 11 is connected with the tracking circuit 10 and is used for controlling the tracking circuit 10 to input a clock signal at the current moment into the clock circuit 12 when the clock circuit 12 is unlocked; wherein, the tracking circuit 10 inputs the clock signal of the clock circuit 12 for the clock circuit to perform clock locking recovery.

The clock signal of the current moment when the clock circuit is unlocked can be generated based on the clock signal received by the clock circuit at the previous moment, and the clock signal is input to the clock circuit in the unlocked state so as to be used for the clock circuit to recover clock locking, so that the clock circuit can continuously obtain the clock signal of the current moment in the unlocked state, and the clock signal of the current moment is generated by the clock signal of the previous moment.

Based on the foregoing embodiments, fig. 2 is a schematic structural diagram of an optional clock signal processing apparatus according to an embodiment of the present invention, and as shown in fig. 2, the tracking circuit 10 includes: a first signal processor 101, a memory circuit 102, and a second signal processor 103; wherein the content of the first and second substances,

the first signal processor 101 is connected to the clock circuit 12, and configured to extract a signal parameter of a clock signal at a current time when the clock circuit is not out-of-lock;

the storage circuit 102 is connected to the first signal processor 101, and is configured to store a signal parameter of a clock signal at a previous time;

the second signal processor 103 is connected to the control circuit 11, and configured to obtain the clock signal at the current time according to a signal parameter of the clock signal at the previous time.

Here, the signal parameters of the clock signal include, but are not limited to, a voltage value, a duty cycle, and a frequency of the clock signal. It will be appreciated that the clock signal is generated by a clock generator which has only two levels, one low and the other high. The high level here is relative to the low level, and the high level has a higher voltage value than the low level. For example, a high level circuit value may set different voltage values depending on different circuit requirements. The voltage value generally refers To a voltage value of the clock signal at a high level, for example, a standard high-level voltage value of 5V in TTL (Time To Live value); the duty ratio refers to the ratio of the time of energization to the total time, e.g. 50%, in a pulse cycle, i.e. a time instant or a period, i.e. the duration of the high level and the low level is the same; the frequency is the reciprocal of the period of the generated clock signal in a fixed time, and can be used to determine the time interval between the clock signal at the first time and the clock signal at the second time.

Here, the first signal processor 101 receives the clock signal at the current time input by the clock circuit 12, and extracts signal parameters of the clock signal at the current time, including, but not limited to, voltage, duty ratio, and frequency generated by the clock signal at the current time. In practical applications, the clock circuit 12 will continuously send a clock signal to the tracking circuit 10 in the locked state.

It is understood that, in the locked state of the clock circuit 12, the storage circuit 102 may store the signal parameters of the clock signal at a plurality of times extracted in the first signal processor 101. In order to save the storage space, the clock signals at the latest moments can be stored; or only the clock signal at the previous time is stored, for example, the storage circuit 102 may store and record only the signal parameter of the clock signal at the previous time before the next clock signal arrives, and discard the signal parameter of the clock signal at the previous time. So that the clock signal at the next moment cannot arrive, or the clock circuit 12 is unlocked, the signal parameter of the clock signal at the previous moment, that is, the signal parameter of the clock signal at the previous moment, can be timely provided to the second signal processor 103, and the second processor 103 processes the signal parameter of the clock signal at the previous moment to obtain the clock signal at the current moment, so that the clock signal at the current moment is output to the clock circuit 12 based on the control of the control circuit 11, and the locking of the clock circuit 12 is recovered.

Here, the second signal processor 103 can perform processing based on the signal parameters of the clock signal stored in the memory circuit 102, such as a voltage value, a duty ratio, and a frequency, and restore the signal parameters of the clock signal to the corresponding clock signal and input the clock signal to the clock circuit 12.

In another embodiment, the control circuit 11 is further configured to control the second processor 103 to obtain the clock signal at the current time based on a signal parameter of the clock signal at the previous time when the lock is lost. That is, only when the lock is lost, the second processor 103 performs processing on the signal parameter of the clock signal at the previous time to obtain the clock signal at the current time. Therefore, the burden of processing data can be reduced for the second signal processor, and the energy consumption of the second signal processor is saved.

In another embodiment, the storage circuit 102 may be configured to store signal parameters of clock signals at multiple times, and the second signal processor 103 may be further configured to extract and analyze the signal parameters of the clock signals at the multiple times to obtain a more accurate signal parameter of the clock signal, and then process the signal parameter of the clock signal to obtain the clock signal at the current time. Specifically, the second signal processor 103 may compare and analyze signal parameters of the clock signals at multiple times, determine that the signal parameter of the clock signal at one of at least two consecutive times is the signal parameter of the clock signal at the previous time, that is, the signal parameter of the clock signal at the previous time of losing lock, when the difference between the same signal parameters of the clock signals at the at least two consecutive times is smaller than the threshold, and process the signal parameter according to the signal parameter of the clock signal at the previous time to obtain the clock signal at the current time, and provide the clock signal to the clock circuit 12 for the lock recovery of the clock circuit 12. In this way, the second processor 103 can compare and analyze the signal parameters of the clock signal at multiple times stored in the storage circuit 102, so as to obtain the signal parameters of the relatively stable clock signal, and the signal parameters of the relatively stable clock signal are used as the signal parameters of the clock signal of the clock circuit in the locked state, thereby ensuring the accuracy of obtaining the signal parameters of the clock signal at the previous time.

Based on the above embodiment, the tracking circuit 10 further includes: a comparison circuit and an algorithm control circuit, wherein the comparison circuit comprises:

and the algorithm control circuit is connected with the output end at one end and the storage circuit at the other end and is used for controlling the signal parameters of the clock information stored in the storage circuit to be equal to the signal parameters of the clock signal at the current moment according to the comparison result and a preset algorithm rule.

Specifically, the storage circuit 102 may store a signal parameter value of an initial clock signal in advance, where the signal parameter of the initial clock signal may be a signal parameter of a clock signal generated by a previously connected clock circuit, or may be a signal parameter of a clock signal set by default in factory.

In one embodiment, the signal parameter of the initial clock signal of the memory circuit 102 is a signal parameter of a clock signal generated by a previously accessed clock circuit, and may be, for example, a signal parameter of a clock signal provided by a clock circuit of the integrated circuit a; now, if the clock circuit 12 needs to be used in the integrated circuit B, the clock circuit 12 needs to be able to provide the clock signal required by the integrated circuit B, and since the signal parameter of the clock signal of the integrated circuit B is different from the signal parameter of the clock signal of the integrated circuit a, at this time, the signal parameter of the clock signal of the integrated circuit a (the signal parameter of the stored initial clock signal) originally stored in the storage circuit 102 needs to be adjusted to the signal parameter of the clock signal at the previous time when the clock circuit of the integrated circuit B is out-of-lock based on the signal parameter of the clock signal at the current time of the clock circuit 12 of the integrated circuit B.

In another embodiment, the signal parameter of the initial clock signal of the memory circuit 102 is a default signal parameter of the clock signal set by factory default, and the tracking circuit can be used to adjust the initial clock signal stored in the memory circuit 102 to the signal parameter of the clock signal provided by the clock circuit connected to the initial clock signal, and finally can store the signal parameter of the clock signal of the clock circuit at the previous moment of losing lock, so that the clock circuit can obtain the clock signal at the current moment based on the signal parameter of the clock signal at the previous moment to restore the lock state of the clock circuit.

It should be noted that, in practical applications, when a signal propagates through a transmission medium, a part of energy is converted into heat energy or absorbed by the transmission medium, so that the signal intensity is continuously attenuated. Even signal parameters cannot avoid unnecessary losses during the transmission of the cable. Based on this, the stored signal parameters of the clock signal and the signal parameters of the clock signal at the current time need to be continuously compared and adjusted, so that a more accurate signal parameter of the clock signal closer to the current time is obtained and stored in the storage circuit.

Specifically, a first input end of the comparison circuit is connected to the first signal processor 101, and is configured to receive a signal parameter of the clock signal at the current time output from the first signal processor 101; a second input terminal, for receiving a signal parameter of the stored clock signal sent by the storage circuit 102, where the signal parameter of the stored clock signal may be the signal parameter of the initial clock signal; then the output end of the comparison circuit outputs the comparison result of the signal parameter of the clock signal at the current moment and the stored signal parameter of the clock signal, and further, the algorithm control circuit controls the signal parameter of the clock signal stored in the storage circuit to be equal to the signal parameter of the clock signal at the current moment based on the comparison result and a preset algorithm rule. It can be understood that the comparison circuit and the algorithm control circuit will continuously compare the clock signal at the current time with the signal parameters of the clock signal stored in the storage circuit 102, and adjust the signal parameters of the clock signal in the storage circuit 102 according to the comparison result of each comparison, and finally adjust the signal parameters of the clock signal closest to the signal parameters of the clock signal at the current time when the clock signal is not out-of-lock, as the signal parameters of the clock signal at the previous time when the lock is out-of-lock.

In one embodiment, the algorithm control circuit adjusts the stored signal parameter of the clock signal to be equal to the signal parameter of the clock signal at the current time according to the comparison result and a rule of a preset threshold value of the comparison result. Specifically, taking the signal parameter of the clock signal as the voltage value as a case, if the comparison result is that the voltage value of the clock signal at the current time is greater than the voltage value of the stored clock signal, and the difference between the voltage value of the clock signal at the current time and the voltage value of the stored clock signal is greater than a preset threshold value, the voltage value of the stored clock signal is increased based on the comparison result. On the contrary, if the comparison result is that the voltage value of the clock signal at the current moment is smaller than the voltage value of the stored clock signal, and the difference value between the voltage value of the stored clock signal and the voltage value of the clock signal at the current moment is larger than the preset threshold value, the voltage value of the stored clock signal is adjusted to be smaller based on the comparison result. And then the comparison of the next round is performed.

Here, the preset threshold may be an error value of a voltage value of the clock signal that can be allowed for the clock circuit to maintain the lock state. When the difference value between the voltage value of the clock signal at the current moment and the voltage value of the stored clock signal is larger than the preset threshold value, the voltage value of the stored clock signal is required to be adjusted, and the problem that when the clock circuit suddenly loses the lock, the voltage value of the clock signal stored in the storage circuit at present is insufficient to provide the voltage value required by the clock circuit for recovering the clock signal in the locked state is avoided.

In another embodiment, the algorithm control circuit will adjust the signal parameter of the stored clock signal to be equal to the signal parameter of the clock signal at the present moment in dependence on the comparison result and in accordance with the rule for adjusting the first predetermined value. Specifically, taking the example of increasing the voltage value of the stored clock signal, the increasing the circuit value of the stored clock signal includes increasing the voltage value of the stored clock signal by a first predetermined value based on the comparison result, where the first predetermined value may be a preset value for slowly adjusting the voltage value of the clock signal, and it should be noted that, in order to avoid an erroneous adjustment phenomenon caused by an error in the comparison result, the output instability phenomenon under the large adjustment caused by the erroneous determination may be avoided by setting the first predetermined value to slowly adjust the signal parameter of the stored clock signal.

Accordingly, the reducing the voltage value of the stored clock signal includes reducing the voltage value of the stored clock signal by a first predetermined value based on the comparison result.

In practical applications, the comparison circuit generally consists of a comparator, and the comparator can only output a high level or a low level, specifically, when the voltage value input by the positive input end is higher than the voltage value input by the negative input end, the comparator outputs the high level; and when the voltage value input by the positive input end is lower than the voltage value input by the negative input end, outputting a low level. The high level is represented by 1 and the low level is represented by 0. That is, the comparison of the signal parameter of the clock signal at the present time with the stored signal parameter of the clock signal based on the comparator has only two results. In the case of a comparison process which is carried out using only one comparator, the adjustment of the stored signal parameters of the initial clock signal to the signal parameters of the clock signal at the preceding instant is effected by introducing the following algorithm rules.

Specifically, the predetermined algorithm rule further includes a bisection algorithm, the signal parameter of the clock signal is still exemplified by a voltage value, the positive input end of the comparator is connected to the first input end, the negative input end of the comparator is connected to the second input end, that is, the positive input end of the comparator receives the voltage value of the clock signal at the current time, the negative input end of the comparator receives the voltage value of the clock signal stored in the storage circuit, and the signal parameter of the initial clock signal is adjusted to the signal parameter of the clock signal at the previous time based on the comparison result and the bisection algorithm. If the comparison result is high level, the opposite process is executed, namely, the voltage value is doubled, and when the comparison result is low level, the value between the voltage value regulated last time and the voltage value after half-and-half operation of the voltage value regulated last time is taken as the voltage value of the clock signal at the previous moment.

Here, the specific implementation process of the dichotomy algorithm is described by taking the voltage value as a decimal value as an example. Assuming that the voltage value of the initial clock signal is 10v and the voltage value of the clock signal at the current time is 2v, and the voltage value of the clock signal at the current time is received at the positive input terminal of the comparator, and the voltage value of the clock signal stored in the storage circuit is received at the negative input terminal of the comparator, it is obvious that, in the present embodiment, after the first comparison, the comparator will output a low level, the voltage value of the clock signal stored in the storage circuit is adjusted to 5v, and then the comparison is continued by using 5v and 2v, while the comparator still outputs a low level, then 5v is compared with 2v after half-and-half operation, and a comparison result of 2.5v and 2v is obtained, while the comparator still outputs a low level, 2.5v is compared with 2v after half-and a comparison result of 1.25v and 2v is obtained, while the comparison result is a high level, and an intermediate value between 1.25v and 1.25v is also two times 2.5v is used as a storage parameter 102 of the voltage value of the clock signal at the previous time 102. It can be seen that the signal parameters of the clock signal stored in the memory circuit can be aligned to the signal parameters of the clock signal approaching the current time by the bisection algorithm.

In practical applications, the voltage value stored in the storage circuit 102 should be a binary value, and the principle of the binary algorithm is the same as that of the decimal algorithm, and the same operation method is adopted to find the value of the signal parameter of the clock signal close to the current time. Specifically, assume that the voltage value of the initial clock signal stored in the storage circuit is 2^ (N-1); if the comparator outputs high level, the voltage value of the initial clock signal is 2^ (N-1) minus 2^ (N-2), otherwise plus 2^ (N-2); judging whether the output result of the comparator is high level or low level again at the next moment, if so, subtracting 2^ (N-3) from the high level, and adding 2^ (N-3) from the low level, and so on until the Nth adjustment, obtaining the voltage value of the clock signal at the previous moment; wherein, N is the binary digit number that the memory circuit can store.

It should be added that, since the storage circuit 102 stores digital signals, the tracking circuit further includes a digital-to-analog converter, one end of the digital-to-analog converter is connected to the storage circuit 102, and the other end of the digital-to-analog converter is connected to the clock circuit 12, and is configured to convert digital signals in signal parameters of the clock signal at the previous time into analog signals and output the analog signals to the clock circuit.

It should be noted that, in order to simplify the circuit design, the signal parameter of the time signal of the initial signal stored in the storage circuit is adjusted to the signal parameter of the clock signal at the current time only by using the comparator, the adjustment time can be saved by using the introduced dichotomy algorithm, and the adjusted value can substantially approximate to the value of the signal parameter of the clock signal at the previous time.

In order to further precisely determine the signal parameters of the clock signal at the previous time, the predetermined algorithm may further comprise a comparison algorithm. And on the basis of the signal parameter of the adjusted initial clock signal obtained by the dichotomy algorithm, adjusting the signal parameter of the adjusted initial clock signal based on the comparison algorithm to finally obtain the signal parameter of the clock signal at the previous moment.

Here, the comparison algorithm is an algorithm that increases or decreases a second predetermined value based on the comparison result, specifically, the voltage value of the initial clock signal is still 10v, the voltage value of the clock signal at the current time is 2v, the positive input terminal of the comparator is connected to the first input terminal, the negative input terminal of the comparator is connected to the second input terminal, that is, the voltage value of the clock signal at the current time is received by the positive input terminal of the comparator, the voltage value of the clock signal stored in the storage circuit is received by the negative input terminal of the comparator, the adjusted voltage value is 1.875 after the adjustment based on the binary algorithm, if the second predetermined value is 0.1, the adjusted voltage value 1.875 is compared with the voltage value 2 of the clock signal at the current time, and if the output is low level, 0.1 is added to obtain the final voltage value 1.975 of the clock signal at the previous time after the adjustment, which is higher than the accuracy of the voltage value adjusted only based on the binary method. In a binary comparison algorithm, a predetermined value is set to 1, and 1 is added if the predetermined value is high, and 1 is subtracted if the predetermined value is low.

In this embodiment, the comparison circuit and the algorithm control circuit can be used to adjust the stored signal parameter of the clock signal at the previous time to be more accurate, which is beneficial to the stability of the lock losing recovery of the clock circuit.

Based on the above embodiment, the tracking circuit 10 further includes:

the third signal processor is connected with the clock circuit and used for extracting the signal parameters of the clock signal at the current moment if the clock signal at the current moment of the clock circuit is received and counting the signal parameters of the clock signal at the current moment received in a specified number of periods;

Here, it should be noted that, if the input end of the tracking circuit receives the clock signal input by the clock circuit again after losing lock, it indicates that the clock circuit may have recovered to be normal at this time, and in order to prevent misjudgment, the third processor extracts the signal parameter of the clock signal at the current time, and counts the signal parameter of the clock signal at the current time received in a specified number of cycles; here, the specified number of cycles is generally two or more cycles. That is to say, the third processor extracts the voltage value of the clock signal at the current time, and counts the voltage values of the clock signals received at the current time in at least two cycles. At this time, the control circuit is further configured to compare signal parameters of the clock signals counted in two adjacent periods, that is, compare the two adjacent periods, or when a difference between voltage values of the clock signals at two adjacent times is smaller than a threshold, it may be determined that the clock circuit has recovered to a locked state, and a stable clock signal can be provided for the integrated circuit.

It should be added that the specified number of cycles is generally determined by different circuits and is preset to adapt to the allowable statistical error of different circuits. In some embodiments, the frequency of the clock signal is affected by the temperature variation, and therefore, when considering the specified number of statistical cycles, the specified number of statistical cycles should be determined taking into account the effect of the temperature variation on the frequency.

In this embodiment, the lock recovery of the clock circuit may be determined based on the clock signal at the current time when the clock circuit is received again. Meanwhile, extracting the signal parameters of the clock signal of the clock circuit at the current moment through a third processor, and counting the signal parameters of the clock signal of the current moment received by the specified number of cycles; judging that the difference value between the signal parameters of the clock signals counted in two adjacent periods is smaller than a threshold value; to prevent the misjudgment of the clock circuit for recovering the lock.

In another embodiment, the third signal processor, connected to the clock circuit, is configured to, if a clock signal and a feedback clock signal at the current time of the clock circuit are received, extract a signal parameter of the clock signal and a signal parameter of the feedback clock signal, compare the signal parameter of the clock signal with the signal parameter of the feedback clock signal, and when the same type of signal parameter of the clock signal is the same as the same type of signal parameter of the feedback clock signal, for example, the frequency of the clock signal is the same as the frequency of the feedback clock signal, it may be considered that the clock circuit has recovered locking; the control circuit controls the tracking circuit not to input the clock signal of the current moment to the clock circuit. The method can be used for judging whether the clock circuit with the synchronous frequency requirements of the reference clock signal and the feedback clock signal exits from the lock losing state, and the judging method is quick and simple.

Based on the above embodiment, the apparatus further comprises at least one buffer,

In one embodiment, at least one buffer is disposed between the output terminal of the clock circuit and the input terminal of the tracking circuit to buffer the input clock signal.

In another embodiment, at least one buffer is provided between the output of the tracking circuit and the input of the clock circuit to buffer the clock signal of the current time output by the tracking circuit to the clock circuit.

An embodiment of the present invention further provides a clock signal processing method, and fig. 3 is a schematic flow chart of the clock signal processing method provided in the embodiment of the present invention, and as shown in fig. 3, the method includes:

step 301: receiving a clock signal input by the clock circuit;

step 302: generating a clock signal of a current time based on a clock signal received at a previous time;

step 303: and when the clock circuit is unlocked, inputting the clock signal of the current moment to the clock circuit so as to recover the clock locking of the clock circuit.

The signal processing method provided by the above embodiment includes: receiving a clock signal input by the clock circuit; generating a clock signal of a current time based on a clock signal received at a previous time; and when the clock circuit is unlocked, inputting the clock signal of the current moment to the clock circuit so as to recover the clock locking of the clock circuit. The clock signal at the current moment when the clock circuit is unlocked can be generated based on the clock signal received at the previous moment when the clock circuit is unlocked and input to the clock circuit in the unlocked state so as to recover the clock locking of the clock circuit, so that the clock circuit can continuously obtain the clock signal at the current moment when the clock circuit is unlocked in the unlocked state, and the clock signal at the current moment is generated by the clock signal at the previous moment, therefore, the clock signal at the current moment output by the clock circuit which is unlocked can be a normal clock signal, thereby providing a stable clock signal for an integrated circuit with the clock circuit, and further ensuring the stability of the output of the integrated circuit or the smooth switching of the output when the clock signal is interrupted or suddenly changed.

Optionally, the

steps

301 and 302 further include:

storing the signal parameter of the clock signal at the previous moment;

Optionally, the method further comprises:

receiving a signal parameter of a clock signal at the current moment;

receiving signal parameters of the stored clock information;

Optionally, the method further comprises:

if the clock signal of the clock circuit at the current moment is received, extracting the signal parameter of the input clock signal, and counting the signal parameter of the clock signal of the current moment received in a specified number of periods;

and if the difference value between the signal parameters of the clock signals counted in two adjacent periods is smaller than a threshold value, controlling the tracking circuit not to input the clock signal of the current moment to the clock circuit.

Here, it should be noted that: the above description of the method embodiment, similar to the above description of the apparatus embodiment, has similar beneficial effects as the apparatus embodiment.

The embodiment of the present invention further provides a specific embodiment, in this embodiment, the clock circuit takes phase-locked loops as an example, and the phase-locked loops are all represented by phase-locked loops (PLLs). It is understood that a PLL is a phase-locked loop, which is a typical feedback control circuit, and uses an externally input reference clock signal to control the frequency and phase of an internal oscillation signal of the loop, so as to achieve automatic tracking of the frequency of an output signal to the frequency of an input signal, and is generally used in a closed-loop tracking circuit. Referring to fig. 7, fig. 7 is a schematic circuit diagram of a phase-locked loop according to an embodiment of the present invention, and as shown in fig. 7, the PLL is composed of a phase frequency detector 71, a charge pump 72, a loop filter 73, a voltage-controlled oscillator 74, and a configurable distributor 75, where the phase frequency detector is also called a phase comparator and is configured to detect a phase difference between an input signal and an output signal, convert the detected phase difference signal into a Ud (t) voltage signal, and output the Ud (t) voltage signal, where the Ud (t) voltage signal is filtered by the loop filter 73 to form a control voltage Uc (t) of the voltage-controlled oscillator 74, so as to control the frequency of the output signal of the voltage-controlled oscillator 74. When the reference clock of the PLL is lost instantaneously, the phase frequency detector 71 generates a periodic high level pulse signal at the output after the reference clock and the feedback clock are discriminated, so that the charge pump is charged/discharged continuously, the input control circuit of the voltage controlled oscillator 74 is abnormal, the PLL loses lock in a transient state, and the output frequency of the PLL changes suddenly.

In this embodiment, to maintain the output stability and smooth switching of the output of the PLL, it is necessary to ensure that the reference clock signal and the feedback clock signal of the PLL are maintained stable, where the voltage-controlled voltage Uc (t) output by the voltage-controlled oscillator 74 of the PLL is processed, and Uc (t) will be denoted by VTUNE, which is generated based on the clock signal of the phase-locked loop, so that VTUNE itself has clock characteristics and can be applied to the above embodiments as the clock signal. It can be understood that the present embodiment processes VTUNE to enable the PLL to remain locked when the clock signal is lost to maintain a stable output of the PLL.

Referring to fig. 4a, fig. 4a is a schematic diagram illustrating a circuit principle of a clock circuit in a locked state according to an embodiment of the present invention, as shown in fig. 4a, the comparator 42 has the same function as the above comparator, the algorithm control circuit 43 has the same function as the above algorithm control circuit, and the DAC (Digital to analog converter) 44 integrates the above memory circuit and also has a Digital to analog conversion function, and can convert a Digital signal stored in the memory device into an analog signal for output. In the present embodiment, the tracking circuit should be understood as a circuit composed of the comparator 42, the algorithm control circuit 43, and the DAC 44. The

switches

45 and 47 are part of the control circuit, and can control the

switches

45 and 47 to close upon receiving the clock circuit is unlocked, that is, the tracking circuit is controlled to input the clock signal of the current time into the clock circuit.

In the present embodiment, in the PLL lock state, the switch 45 and the switch 47 are in the off state, the clock signal of the PLL enters the negative input terminal of the comparator 42 via the buffer 41, and is compared with the signal parameter of the stored clock signal output from the output terminal of the DAC44, and based on the comparison result, the algorithm control circuit 43 adjusts the signal parameter of the clock signal stored in the DAC44 to the signal parameter of the clock signal of the PLL in the lock state or to the signal parameter of the clock signal immediately before the loss of lock.

Fig. 4b is a schematic diagram of a circuit principle of the clock circuit in an out-of-lock state according to the specific embodiment of the present invention, as shown in fig. 4b, in the out-of-lock state of the PLL, the switch 45 and the switch 47 are closed, the clock signal at the current time is obtained from the signal parameter of the clock signal at the previous time stored in the DAC44, and is sent to the PLL for the PLL to recover the clock lock, that is, to keep VTUNE in the PLL at the time before the out-of-lock, so as to ensure stable output and smooth switching of the PLL.

Hereinafter, a clock signal is denoted by DAC _ CLK; DAC _ HOLD < N-1 > represents a signal parameter of the clock signal stored in the DAC, and may be an N-bit digital signal. N represents the number of binary bits that the DAC can store.

Specifically, referring to fig. 5, fig. 5 is a schematic flow chart illustrating a method for adjusting a signal parameter of a clock signal according to an embodiment of the present invention; as shown in fig. 5, the method is mainly applied to tracking processing of the input clock signal in a locked state, and specifically includes:

the method for coarse tuning, that is, the method for adjusting the initial clock signal by using the dichotomy algorithm, includes:

step 501: detecting whether the PLL is locked; when the PLL is locked, step 502 is performed.

Step 502: outputting DAC _ HOLD < N-1 > =2^ (N-1) on DAC _ CLK clock rising edge.

Step 503: is the next DAC CLK clock rising edge decision comparator output high? If yes, go to step 504; otherwise, step 505 is performed.

Step 504: outputting DAC _ HOLD < N-1 > =2^ (N-2) on DAC _ CLK clock rising edge.

Step 505: output on DAC _ CLK rising edge

DAC_HOLD<N-1:0>＝2^(N-1)+2^(N-2)

Step 506: the appropriate DAC value is found using a dichotomy.

The fine tuning method, that is, the method for adjusting the initial clock signal adjusted based on the bisection method by using the comparison method, includes:

step 507: does the comparator output go high on the next DAC _ CLK clock rising edge? If yes, go to step 508; if not, go to step 509.

Step 508: DAC _ HOLD < N-1 > minus 1.

Step 509: DAC _ HOLD < N-1 > plus 1.

Starting DAC value tracking under the condition of locking of the analog PLL, firstly giving an initial value of DAC _ HOLD, searching a correct DAC value by adopting a dichotomy, wherein DAC _ HOLD is Nbit, and searching for N times at most to obtain a final value. This part is coarse tuning. After the coarse adjustment finds a proper DAC value (signal parameter), a fine adjustment process is executed, the comparison result of the comparator is detected, and if the comparison result is low level, the DAC _ HOLD < N-1 > is added by one; if the comparison result is high, DAC _ HOLD < N-1 > is decremented by one. In the tracking process, the lock state of the PLL is detected at any time when necessary, tracking is stopped when the PLL is out of lock, and the tracking is restarted from rough adjustment.

In this embodiment, when the reference clock is switched or lost, the PLL outputs an out-of-lock indication signal, the switch is closed to enter a hold state, the digital-to-analog converter stops tracking at this time, the voltage-controlled voltage of the voltage-controlled oscillator 74 is switched to the voltage-controlled voltage stored by the digital-to-analog converter at the moment before the loss of lock, and the output frequency of the voltage-controlled oscillator 74 is stable.

Fig. 6 is a flowchart illustrating a processing method of the clock circuit after the clock circuit is out of lock according to an embodiment of the present invention, as shown in fig. 6,

step 601: PLL locking;

step 602: is PLL out of lock, VTUNE enters hold state? If yes, go to step 603; if not, go to step 604;

step 603: counting the high-frequency clock at the rising edges of the reference clock and the feedback clock until the next rising edge is counted; respectively storing the clock counting result into fbclk _ num and refclk _ num registers;

specifically, in this embodiment, counting statistics for at least two cycles are performed on both the reference clock and the feedback clock, respectively, where the fbclk _ num register is used to store the count value of the reference clock, and the refclk _ num register is used to store the count value, that is, the cycle number, of the feedback clock.

It should be noted that the method further includes step 604: the influence of temperature change on the output frequency of the VCO is detected in advance, and the influence of temperature on the frequency is added into the counting precision.

Since the change in temperature has a certain influence on the output frequency of the voltage controlled oscillator 74 of the PLL, it is necessary to add the influence of temperature on the frequency to the accuracy of counting in order to avoid erroneous determination when counting the statistical period.

Step 605: the error period threshold value is less than or equal to | refclk _ num-fbclk _ num |; if yes, go to step 606, if no, go to step 607;

step 606: the counter hold _ exit _ cnt exiting the lock losing is added with 1;

step 607: the counter hold _ exit _ cnt that exited the lost lock is cleared.

Step 608: is hold _ exit _ cnt ≧ the exit out-of-lock period threshold set in advance? If yes, go to step 609, otherwise, go back to step 603;

wherein the hold _ exit _ cnt is the number recorded by the counter of exit loss of lock. Here, in order to realize smooth handover, handover may be performed when the hold _ exit _ cnt is greater than the threshold value

Step 609: the PLL exits out-of-lock.

In this embodiment, the out-of-lock state is exited by detecting the frequency of the reference clock, and switching back to the locked state when the frequency of the feedback clock is the same. Specifically, after the PLL is out of lock, once a reference clock input is detected, the high frequency clock (the clock divided by the output of the voltage controlled oscillator 74) is counted at the rising edge of the reference clock and the rising edge of the feedback clock, respectively, and the count is performed until the next rising edge arrives, the two count results are compared, when the error is smaller than the threshold, the two frequencies are considered to be the same, the voltage controlled voltage is switched back to the output voltage of the charge pump, and the PLL restarts the locking process.

Further, when the counted number of times of lock release is greater than the threshold, it is indicated that the PLL does not briefly lose lock, or temporarily lose the clock signal caused by switching clocks, but may have stopped operating, or shut down, so that the PLL does not need to be locked again.

In the embodiment, the effect of smooth transition of the output of the PLL when the reference clock is lost or the master/slave clock is switched can be realized only by a simple circuit.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. The scope of the invention is to be determined by the scope of the appended claims.

Claims

1. A clock signal processing apparatus, characterized in that the apparatus comprises:

the control circuit is connected with the tracking circuit and used for controlling the tracking circuit to input a clock signal at the current moment into the clock circuit when the clock circuit is unlocked; the tracking circuit inputs a clock signal of the clock circuit and is used for recovering clock locking of the clock circuit; wherein, the first and the second end of the pipe are connected with each other,

the tracking circuit includes: the third signal processor is connected with the clock circuit and used for extracting the signal parameters of the clock signal at the current moment and counting the signal parameters of the clock signal at the current moment received in a specified number of periods if the clock signal input by the clock circuit is received;

2. The apparatus of claim 1, wherein the tracking circuit further comprises: the device comprises a first signal processor, a storage circuit and a second signal processor; wherein the content of the first and second substances,

the first signal processor is connected with the clock circuit and used for extracting signal parameters of the clock signal at the current moment when the clock circuit is not unlocked;

the output end of the second signal processor is connected with the clock circuit, and the second signal processor is used for obtaining the clock signal at the current moment according to the signal parameter of the clock signal at the previous moment stored by the storage circuit.

3. The apparatus of claim 2, wherein the tracking circuit further comprises a comparison circuit and an algorithm control circuit, wherein the comparison circuit comprises:

and the algorithm control circuit is connected with the output end at one end and the storage circuit at the other end, and is used for controlling the signal parameter of the clock signal stored in the storage circuit to be equal to the signal parameter of the clock signal at the current moment according to the comparison result and a preset algorithm rule.

4. The apparatus of claim 1, further comprising at least one buffer,

5. A clock signal processing method, the method comprising:

receiving a clock signal input by a clock circuit;

when the received clock circuit is unlocked, the clock signal of the current moment is input to the clock circuit so as to be used for the clock circuit to recover clock locking, wherein,

the method further comprises the following steps:

6. The method of claim 5,

the receiving the clock signal input by the clock circuit, and generating the clock signal of the current time based on the clock signal received at the previous time includes:

storing a signal parameter of a clock signal at a previous moment;

7. The method of claim 6, further comprising:

receiving a signal parameter of a clock signal at the current moment;

receiving signal parameters of the stored clock information;