JP2011055402A - Synchronous transmission apparatus and jitter suppression method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a peak jitter generated near a zero-cross point of frequency deviation between an input clock and a system clock, in a synchronous transmission apparatus and a jitter suppression method. <P>SOLUTION: A synchronous transmission apparatus includes: a digital circuit 15_1 for generating a reference clock by re-timing an input clock in accordance with a system clock in the apparatus; a PLL circuit 15_2 for generating an output clock synchronized with the reference clock; a frequency deviation proximity detecting section 1_1 for detecting proximity between frequency deviation of the input clock and frequency deviation of the system clock; and a frequency adjusting section 1_2 which adjusts an oscillation frequency of an oscillator 1_3 of the system clock so as to increase the difference of the frequency deviation when the proximity of the frequency deviation is detected. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a synchronous transmission apparatus and a jitter suppression method. The present invention is applied to, for example, a clock synchronization circuit in a synchronous transmission apparatus such as SONET (Synchronous Optical Network) / SDH (Synchronous Digital Hierarchy).

  A synchronous transmission device such as SONET / SDH includes a clock synchronization circuit for performing subordinate synchronization. A typical circuit configuration example of the clock synchronization circuit is shown in FIG. FIG. 15 shows a configuration example of a clock synchronization circuit using a digital PLL circuit. The digital PLL circuit includes a digital circuit 15_1, a PLL (Phase Locked Loop) circuit 15_2, and a fixed oscillator (OSC) 15_3.

  The digital circuit 15_1 generates a reference clock from the input clock. The PLL circuit 15_2 generates an output clock synchronized with the phase of the reference clock generated by the digital circuit 15_1. A fixed oscillator (OSC) 15_3 supplies a system clock to the digital circuit 15_1.

  The input clock is a network synchronization clock of the transmission network, and is a clock extracted from a DCS (Digital Clock Supply) or CSM (Clock Supply Module) serving as a clock source or a main signal of the transmission path. The output clock is a clock for main signal transfer in the apparatus or a clock source used when transmitting the main signal to the transmission line, and is a clock dependently synchronized with the input clock.

  The fixed oscillator (OSC) 15_3 is an oscillator that outputs a system clock having a sufficiently high frequency to digitally process an input clock to generate a reference clock, and the reference clock can be easily generated from the input clock. An oscillator having a frequency that is an integer multiple of several tens to several hundreds of the input clock is used.

  The digital circuit 15_1 operates with a system clock supplied from the fixed oscillator (OSC) 15_3, and generates a reference clock supplied to the PLL circuit 15_2 by dividing the system clock of the fixed oscillator (OSC) 15_3. Therefore, the frequency stability of the fixed oscillator (OSC) 15_3 becomes the stability of the reference clock and the stability of the output clock of the PLL circuit 15_2, and finally the clock stability of the entire device. A high crystal oscillator is used.

  Here, in order to simply output the output clock synchronized with the input clock, the input clock may be directly input to the PLL circuit 15_2, and the output clock synchronized with the input clock may be generated by the PLL circuit 15_2. And the fixed oscillator (OSC) 15_3 is unnecessary.

  However, a synchronous transmission device or the like is required to have a function of normally maintaining transmission of a main signal even when an input clock becomes abnormal (input interruption or signal quality degradation). For this purpose, the digital circuit 15_1 stores the frequency (period) and phase values of the input clock when normal, and regenerates the reference clock based on the stored frequency (period) and phase values when the input clock is abnormal. , It has a configuration that runs on its own.

  Since the digital circuit 15_1 operates with the system clock from the fixed oscillator (OSC) 15_3, the phase of the reference clock is controlled in units of the period of the system clock. The phase of the PLL circuit 15_2 to which the reference clock is input is also controlled in units of the system clock period from the fixed oscillator (OSC) 15_3.

  Therefore, the output clock output from the PLL circuit 15_2 has a phase fluctuation of one cycle of the system clock of the fixed oscillator (OSC) 15_3. However, the phase fluctuation in the PLL circuit 15_2 due to the attenuation characteristic with respect to the phase fluctuation ( Jitter) is suppressed. However, the gradual movement fluctuation cannot be suppressed in the PLL circuit 15_2.

  FIG. 16 shows an example of clock frequency variation in the synchronous transmission apparatus. 16_1 shows a time series graph of frequency deviation of the input clock, and 16_2 shows a time series graph of frequency deviation of the system clock of the fixed oscillator (OSC). Since the frequency of the input clock and the system clock (fixed oscillator OSC) has a deviation from the center frequency and constantly fluctuates, the difference in frequency deviation between both clocks becomes zero irregularly, and the frequency deviation between both clocks. The time series graphs may cross. At the intersection points 16_3, 16_4, and 16_5, wander occurs in the output clock.

  In a state where the difference between the frequency deviation of the input clock and the frequency deviation of the system clock is very close, the phase of the reference clock input to the PLL circuit 15_2 changes at a low frequency, so that the phase fluctuation is suppressed by the PLL circuit 15_2. Therefore, peak jitter (wander) occurs near the intersection of frequency deviations.

  FIG. 17 shows a configuration example of the digital circuit 15_1 in FIG. 15, and FIG. 18 shows a timing chart of the operation of the digital circuit 15_1. The digital circuit 15_1 will be described with reference to these. The digital circuit 15_1 includes a sampling unit 17_1, a clock cycle count unit 17_2, a clock cycle count value storage unit 17_3, and a reference clock generation unit 17_4.

  The sampling unit 17_1 samples the input clock input to the digital circuit 15_1 with the system clock and performs retiming. The clock cycle count unit 17_2 counts the retimed cycle of the input clock with the system clock and digitizes it. That is, the number of cycles of the system clock corresponding to the input clock is quantified.

  At this time, since the system clock has a frequency that is an integral multiple of the input clock, the count value is almost the same every time (here, this value is n). For example, if the input clock is 64 kHz and the system clock is 32.768 MHz, 32.768M / 64K = 512, and the count value n is 512.

  However, the input clock and the system clock are asynchronous, the phase difference between the two clock edges is indefinite, and the period of the retimed input clock varies by ± 1 clock of the system clock. Although this occurrence probability is quite low, the count value of the clock cycle count unit 17_2 is n + 1 or n-1 when variations occur.

  18A shows a case where the count value of the input clock cycle is n, FIG. 18B shows a case where the count value of the input clock cycle is n + 1, and FIG. Indicates a case where the count value of the input clock period is n-1.

  Nevertheless, if the frequency deviation between the input clock and the system clock is completely equal, +1 and -1 occur alternately, the frequency of occurrence is equal, and the average value is completely n. There is no value error. For example, when the input clock is 64 KHz and the system clock is 32.768 MHz, the count value is 511 to 513, but the average value is 512.

  When the frequency deviation of the input clock is different from the frequency deviation of the system clock, and the frequency deviation is slightly shifted, a difference occurs in the generation rate of the count value n + 1 and the count value n-1. When the frequency deviation of the system clock is high with respect to the input clock, the count result of the clock period is large, so the number of count values n + 1 is increased, and conversely, the frequency deviation of the system clock is low with respect to the input clock. When the count value n−1 is generated, the number of occurrences increases.

  However, a clear difference is detected in the number of occurrences of the count value n + 1 and the count value n−1 because the difference between the input clock frequency deviation and the system clock frequency deviation exceeds one cycle of the system clock. This is when the phase difference is accumulated. Therefore, the generation interval is relatively long and the frequency component is low.

  For example, if the input clock frequency is 64 KHz, the deviation is +1 ppm (part per million), the system clock frequency is 32.768 MHz, and the deviation is +2 ppm, the difference in frequency deviation is 1 ppm. The count value of the clock cycle is almost 512, but the count value 513 is included at a ratio of 1 / 1,000,000. That is, the generation cycle in which the count value increases by 1 is about 1/32 second interval, and its frequency component is about 32 Hz (= 32.768 MHz ÷ 1,000,000).

  The clock cycle count value storage unit 17_3 includes a memory and its access control circuit, and sequentially writes and stores the values counted by the clock cycle count unit 17_2. The reference clock generation unit 17_4 includes a counter circuit, and generates a reference clock by dividing the system clock by the count value read from the clock cycle count value storage unit 17_3.

  Since the reference clock generation unit 17_4 generates the reference clock with the count value including ± 1 variation counted by the clock cycle counting unit 17_2, the reference clock is accurately reproduced as a clock obtained by retiming the input clock with the system clock. .

  FIG. 19 shows a configuration example of the PLL circuit 15_2 in FIG. FIG. 20 shows a timing chart of the operation of the PLL circuit. The PLL circuit will be described with reference to these. In FIG. 19, the phase comparator 19_1 compares the phase of the output clock divided and fed back by the frequency divider 19_4 with the phase of the reference clock to generate a phase comparison signal.

  20A shows the waveform of the reference clock, FIG. 20B shows the waveform of the output clock that is divided and fed back by the frequency divider 19_4, and FIG. 20C shows the phase comparison output from the phase comparator 19_1. The signal waveform is shown. The phase comparison signal becomes high level at the rising edge of the reference clock and becomes low level at the rising edge of the divided output clock. In the reference clock, a frequency / phase variation corresponding to the frequency / phase variation of the input clock appears, and the frequency / phase variation appears at the rising edge of the phase comparison signal.

  The filter 19_2 is a low-pass filter, which allows components below the predetermined frequency to pass through the fluctuation frequency of the phase comparison signal output from the phase comparison unit 19_1, but attenuates components above the predetermined frequency with a predetermined inclination and outputs them. Gives attenuation characteristics. Therefore, a waveform obtained by smoothing the phase comparison signal is output as shown in FIG. This predetermined frequency determines the cutoff frequency (fc) of the PLL circuit. (Strictly speaking, the cutoff frequency (fc) of the PLL circuit is determined by the frequency division ratio of the frequency divider 19_4 and the cutoff frequency of the filter 19_2.)

  When the cut-off frequency (fc) is determined, the PLL circuit has a characteristic that suppresses a component exceeding the cut-off frequency (fc) with respect to the fluctuation frequency of the input clock (that is, an attenuation characteristic substantially equal to the integration circuit). give. Further, the lock range of the PLL circuit is determined by the cutoff frequency (fc). Therefore, when the frequency band of the phase variation of the input clock to be synchronized is wide, the cut-off frequency (fc) cannot be set to a very low frequency.

  The voltage controlled oscillator (VCO) 19_3 oscillates at a center frequency equal to or several to several hundred times the input clock, and oscillates at an oscillation frequency controlled by the center voltage of the smooth waveform output from the filter 19_2. An output clock synchronized with the input reference clock is generated.

  The control voltage input to the voltage controlled oscillator (VCO) 19_3 is smoothed by the filter 19_2, but is not necessarily a flat voltage signal. Nevertheless, since the frequency / voltage response characteristic of the voltage controlled oscillator (VCO) 19_3 is not so sensitive, the voltage controlled oscillator (VCO) 19_3 oscillates at a frequency corresponding to the average voltage of the control voltage and sends out an output clock. To do.

  The frequency divider 19_4 is a counter circuit that divides the output clock sent from the voltage controlled oscillator (VCO) 19_3 so as to have the same frequency as the reference clock, and feeds back the frequency-divided output clock to the phase comparator 19_1. To do.

  The transfer characteristics of the PLL circuit are shown in FIG. In FIG. 21A, the horizontal axis represents the fluctuation frequency (jitter component) of the input (reference clock), and the vertical axis represents the output level (amplification degree) with respect to the input level. The PLL circuit provides an attenuation characteristic having a characteristic close to that of the integrating circuit in a frequency band in which the fluctuation frequency of the input (reference clock) is higher than the cutoff frequency (fc). On the other hand, in the frequency band lower than the cut-off frequency (fc), the input is transmitted and output as it is, and has the characteristic of following the frequency fluctuation of the input and outputting.

  This characteristic is a jitter attenuation characteristic that attenuates and stabilizes the phase component of the input clock that oscillates at a high speed, and the phase component of the input clock that oscillates at a low speed (that is, the input clock phase that changes slowly). The frequency response characteristic generates an output clock that follows the phase.

  When the configuration example of the digital circuit and the PLL circuit shown in FIGS. 17 and 19 is used in the clock synchronization circuit of FIG. 15, wander generated in the clock synchronization circuit will be described. As described with reference to FIG. 17, the reference clock with which the PLL circuit synchronizes is a reproduction of the frequency and phase of the input clock retimed by the system clock, and causes a phase fluctuation periodically and intermittently. It has the property to become.

Among the jitter, the jitter of the high frequency component is attenuated by the transfer characteristic of the PLL circuit shown in FIG. 21A, but the jitter of the low frequency component is output as it is. The output low frequency component jitter is caused by the following factors.
(1) Reference clock phase fluctuation due to input clock fluctuation (2) Reference clock phase fluctuation due to retiming

  Of the above factors, the response of the factor (1) needs to be followed and the jitter of the low frequency component should be output as it is, but the factor (2) occurs inside the apparatus. Since it is jitter (wander), the jitter (wander) of the low frequency component should not be output.

  As shown in FIG. 21B, the jitter due to this retiming is such that when the difference between the frequency deviation of the input clock and the frequency deviation of the system clock is extremely small (close), jitter of an extremely low frequency component is present. Appears as peak jitter in the output clock. Since the jitter of this component is on the lower frequency side than the cutoff frequency (fc), it cannot be attenuated by the PLL circuit.

  It is difficult to realize a PLL circuit that gives a sufficient amount of attenuation to jitter in a low frequency band whose fluctuation frequency is near zero Hz. This jitter is called zero-crossing jitter and is a peak jitter that inevitably appears in the configuration of the digital PLL circuit. This peak jitter is output as a wander generated from within the apparatus itself.

  In order to improve the clock quality, there is a characteristic that wander is more likely to occur as the frequency stability is increased and the frequency deviation is decreased. Therefore, if the quality / accuracy of the fixed oscillator (OSC) that generates the system clock of the apparatus is made too high, wander is likely to occur. For this reason, even if the clock quality of the clock supply device (DCM, CSM, etc.) is increased, the quality of the system clock inside the device cannot be increased so much, so there is a limit to improving the clock quality of the entire synchronous network. .

  As described above, the synchronous transmission device using the digital PLL circuit has a structure in which the device itself becomes a wander generation source. However, the actual synchronous transmission device is synchronized with the opposite device following the wander. Therefore, there is almost no hindrance to signal transmission. Furthermore, in the SONET / SDH transmission network and its transmission device, the frequency accuracy and stability of the clock are not so good that this phenomenon can be seen on a daily basis, and it slowly changes gradually over several hours to several days. Therefore, wander occurs only at the point where the frequency deviation happens to cross. The frequency accuracy is ± 40 ppm, and the stability is about ± 4 ppm.

  In addition, even if this wander is tried to be captured, it is a phenomenon that occurs accidentally in various environmental conditions such as individual differences of the fixed oscillator (OSC), accidental combination with the input clock, and power supply and temperature. Because it is difficult to capture and observe this wander, it is very difficult to verify.

  For a digital PLL circuit, a fixed frequency reproduction clock is output, and the reproduction clock is switched to either a reproduction clock whose fixed frequency is lower than the minimum frequency of the reference clock or a reproduction clock higher than the maximum frequency of the reference clock. A digital PLL circuit that supplies a clock that does not include a low-frequency jitter component is known, for example, from Patent Document 1 below.

Japanese Patent Laid-Open No. 7-250051

  A synchronous transmission device using a digital PLL circuit has a wander (peak jitter near the zero crossing point of the frequency deviation) when the difference between the frequency deviation of the input clock and the frequency deviation of the system clock is very close. Will occur. This is a phenomenon that is more likely to occur as the frequency stability is increased to improve clock quality and the frequency deviation is reduced. This is the limiting point for preventing wander while improving the clock quality of the transmission network. It becomes. However, in order to achieve high-quality clock transmission, it is essential to improve clock stability. The present invention aims to suppress peak jitter that occurs near the zero crossing point of the frequency deviation between the input clock and system clock. And

  A synchronous transmission apparatus that solves the above problems includes a digital circuit that generates a reference clock in which an input clock is retimed by a system clock in the apparatus, a PLL circuit that generates an output clock synchronized with the reference clock, and the input clock A frequency deviation approach detecting means for detecting an approach between the frequency deviation of the system clock and the frequency deviation of the system clock; and when the approach of the frequency deviation is detected, the frequency of the system clock is adjusted to increase Frequency adjusting means.

  The disclosed synchronous transmission device can adjust the frequency of the system clock so that a difference occurs between the frequency deviation of the input clock and the system clock when the proximity of the frequency deviation between the input clock and the system clock is detected. Peak jitter that occurs near the zero crossing point can be suppressed.

It is a figure which shows the structural example of a clock synchronous circuit. It is a figure which shows the example of the frequency deviation at the time of performing frequency control of a system clock. It is a figure which shows the structural example of a frequency deviation approach detection part. It is a figure which shows the structural example of a frequency adjustment part. FIG. 5 is a diagram illustrating a configuration example of a clock synchronization circuit to which the configuration examples of FIGS. 3 and 4 are applied. It is a figure which shows the structural example of the frequency deviation approach detection part which monitors a reference clock and detects the approach of a frequency deviation. It is a figure which shows the structural example of the frequency deviation approach detection part which monitors a phase comparison signal and detects the approach of a frequency deviation. It is a figure which shows the timing chart of the structural example of FIG. It is a figure which shows the structural example which changes the oscillation frequency of a fixed oscillator (OSC) by control of a power supply voltage. It is a figure which shows the structural example which changes the oscillation frequency of a fixed oscillator (OSC) by control of ambient temperature. It is a figure which shows the example which used the clock synchronous circuit for the trunk line network apparatus. It is a figure which shows the clock waveform observed with the apparatus which the wander emitted. It is a figure which shows the phase difference fluctuation | variation of the clock synchronous circuit of a redundant structure. It is a figure which shows the example of the network apparatus which performs multistage relay of a clock. It is a figure which shows the general circuit structural example of a clock synchronous circuit. It is a figure which shows the example of the frequency variation of the clock in a synchronous transmission apparatus. It is a figure which shows the structural example of a digital circuit. It is a timing chart of operation of a digital circuit. It is a figure which shows the structural example of a PLL circuit. 3 is a timing chart of the operation of the PLL circuit. It is a figure which shows the transfer characteristic of a PLL circuit, and the peak jitter of a digital PLL circuit.

  The peak jitter (wander) near the zero crossing point of the frequency deviation between the input clock and the system clock is the low frequency phase fluctuation of the reference clock in the PLL circuit when the difference between the frequency deviations of the input clock and the system clock is very close. It is caused by not being able to suppress. Therefore, by providing a certain difference between the frequency deviation of the input clock and the frequency deviation of the system clock, the frequency of the phase fluctuation of the reference clock is increased, and suppression by the PLL circuit becomes possible.

  However, the input clock and the system clock constantly fluctuate within a predetermined frequency accuracy range, and it is difficult to maintain a certain difference in the frequency deviation between the input clock and the system clock. In addition, a method of causing a difference in frequency deviation by providing a system clock having a frequency deviation in a region outside the frequency deviation region of the input clock can be considered. However, in such a method, the input clock is accurately used as a reference clock. As it becomes difficult to play.

Therefore, in order to have a difference in frequency deviation between the input clock and the system clock, the frequency deviation of the system clock may be controlled by monitoring the frequency deviation of the input clock. A specific configuration example for this purpose is shown in FIG. In FIG. 1, in order to change the frequency of the system clock, a frequency deviation approach detecting unit 1_1 and a frequency adjusting unit 1_2 are added to the configuration example of FIG. 15, and an oscillator whose oscillation frequency is variable instead of the fixed oscillator (OSC) 15_3. (OSC) 1_3 is provided. The frequency deviation approach detection unit 1_1 monitors the frequency deviation between the input clock and the system clock and detects that the deviation is approaching. The frequency adjustment unit 1_2 adjusts the oscillation frequency of the oscillator (OSC) 1_3 based on the detection result of the frequency deviation approach detection unit 1_1.
It is a thing.

  FIG. 2 shows a time series graph of an example of frequency deviation when frequency control is performed on the system clock oscillator (OSC) 1_3. 2_1 is a time series graph of the frequency deviation of the input clock, and 2_2 is a time series graph of the frequency deviation of the system clock of the oscillator (OSC).

  In this example, the frequency deviation of the input clock and the system clock crosses at the point (A), but the frequency adjustment of the oscillator (OSC) is started before this crossing point, and the frequency deviation from the reverse direction at the point (B). By maintaining the frequency adjustment of the oscillator (OSC) until the crossing point is exceeded, a frequency difference of a certain level or more is maintained as indicated by 2_3.

  Note that the change from point (A) to point (B) depends on the characteristics of the oscillator (OSC) and therefore cannot be determined unconditionally. However, in FIG. 2, if frequency control is not performed, the change is originally output from the oscillator (OSC). The frequency deviation of the oscillator (OSC) is indicated by a dotted curve.

  This frequency control is performed so slowly that it is almost indistinguishable from the frequency fluctuation originally possessed by the system clock oscillator (OSC). Therefore, frequency fluctuation is hardly observed in short-time observation. Therefore, wander can be prevented without affecting the operation of the original digital PLL circuit at all (operating in the same manner as the operation for the original error fluctuation).

Hereinafter, the configuration example of FIG. 1 will be described in detail.
[1] Configuration Example for Detecting Frequency Deviation Approach by Monitoring Input Clock FIG. 3 shows a configuration example of the frequency deviation approach detection unit 1_1 in FIG. In FIG. 3, a sampling unit 17_1, a cycle count unit 17_2, a clock cycle count value storage unit 17_3, and a reference clock generation unit 17_4 are the same as those in the digital circuit 15_1 described in FIG. A block surrounded by a broken line is a circuit added in this configuration example, and includes a + fluctuation detecting unit 3_1, a-fluctuation detecting unit 3_2, an up / down counter 3_3, a ± 2 fluctuation detecting unit 3_4, and an occurrence time monitoring unit 3_5.

  The count value of the clock cycle count unit 17_2 that counts the number of samplings of one cycle of the input clock is any one of n, n + 1, and n-1 as described with reference to FIG. The + fluctuation detecting unit 3_1 and the − fluctuation detecting unit 3_2 monitor the count value and detect that the center value n has changed to +1 or −1.

  The up / down counter 3_3 is a counter that counts up based on the detection output of the + fluctuation detecting unit 3_1 and counts down based on the detection output of the − fluctuation detecting unit 3_2. Normally, the count value of the up / down counter 3_3 does not deviate from 0 or ± 1.

  However, if there is a difference between the frequency deviations of the input clock and the system clock, a difference occurs between the occurrence probability of +1 and the occurrence probability of −1. Therefore, the up / down counter 3_3 detects either +1 or −1. May occur continuously, resulting in a fluctuation range of ± 2. The ± 2 fluctuation detector 3_4 monitors the occurrence of this ± 2 fluctuation and detects that there is a difference in frequency deviation between the input clock and the system clock.

  When detecting the occurrence of ± 2 fluctuations, the ± 2 fluctuation detecting unit 3_4 causes the up / down counter 3_3 and the occurrence time monitoring unit 3_5 to clear the count value and the monitoring time, and return them to the initial values. The occurrence time monitoring unit 3_5 monitors the occurrence time interval of ± 2 fluctuations detected by the ± 2 fluctuation detection unit 3_4. When the occurrence time interval is not cleared and becomes a value equal to or longer than the set time, the input clock And the system clock frequency deviation is approaching.

  In addition, the occurrence time monitoring unit 3_5 determines whether the ± 2 fluctuation detected by the ± 2 fluctuation detection unit 3_4 is the positive side or the negative side, and the frequency deviation between the input clock and the system clock is close. , + Side frequency deviation approach detection information indicating that it is from the + side direction, or − side frequency deviation approach detection information that indicates that it is from the − side direction.

  The set time of the timer of the generation time monitoring unit 3_5 determines the frequency deviation at which the input clock and the system clock reapproach. This becomes the lowest frequency component of the fluctuation frequency of the phase of the reference clock, and at the same time, becomes the lowest jitter frequency component of the output clock, and is determined based on the jitter frequency attenuation characteristic by the cutoff frequency (fc) of the PLL circuit.

  As an example, a case will be described in which the system clock frequency is 32.768 MHz, the cutoff frequency (fc) of the PLL circuit is 50 Hz, and the allowable jitter is 50 ns or less. The phase of the system clock ± 1 period is 1 / 32.768 MHz × 2 = 61 ns. In order to suppress the 61 ns jitter to 50 ns or less, it is necessary to attenuate to 1 / 12.2 by the PLL circuit.

  Since it can be attenuated to 1/20 or less with respect to a frequency of 1 KHz or more from the cutoff frequency (fc) of the PLL circuit, control is performed so that the reference clock fluctuation is always 1 KHz or more. Since the period of 1 KHz is 1 ms, the timer of the generation time monitoring unit 3_5 is set to this value.

  Further, since 1 KHz is about 30.5 ppm of the system clock (= 1 KHz ÷ 32.768 MHz), the frequency deviation in which the input clock and the system clock approach again is also about 30.5 ppm. At the same time, the lowest frequency component of the output clock jitter is also limited to 1 KHz. In this example, the above condition is used to simplify the calculation. Actually, however, the cutoff frequency (fc) of the PLL circuit is calculated from the allowable jitter output and the frequency deviation between the input clock and the system clock. It will be a work to decide.

[2] Configuration Example of Frequency Adjustment Circuit When Voltage-Controlled Oscillator is Used as Oscillator (OSC) FIG. 4 shows a frequency adjustment unit 1_2 when a voltage-controlled oscillator is used as the oscillator (OSC) 1_3 in FIG. The example of a structure is shown. The frequency adjustment unit 1_2 includes a + side frequency adjustment unit 4_1 and a-side frequency adjustment unit 4_2. The + side frequency adjustment unit 4_1 and the − side frequency adjustment unit 4_2 respectively input + side frequency deviation approach detection information and − side frequency deviation approach detection information from the generation time monitoring unit 3_5. As described with reference to FIG. 3, the difference in frequency deviation between the input clock and the system clock is detected as a difference in frequency of occurrence on the + side or − side of the clock cycle count unit 17_2.

  The approach of the frequency deviation is detected by decreasing the occurrence frequency. The approach includes a case of approaching from the + side and a case of approaching from the-side. When the approach of the frequency deviation from the + side is detected, when the system clock frequency is high with respect to the input clock, and the approach is such that the difference is small, the peak jitter will be Will begin to occur. Therefore, when the + side frequency deviation approach detection information is input, the frequency of the oscillator (OSC) 1_3 is controlled by the + side frequency adjustment unit 4_1 to increase the oscillation frequency, thereby giving a difference in the frequency difference deviation.

  On the other hand, when the approach of the frequency deviation on the minus side is detected, when the system clock frequency is low with respect to the input clock, the approach is such that the difference becomes smaller, and the approach further proceeds as it is. Similarly, the generation of peak jitter starts. Therefore, when the + side frequency deviation approach detection information is input, the − side frequency adjustment unit 4_2 controls the frequency of the oscillator (OSC) 1_3 to lower the oscillation frequency so as to have a difference in frequency deviation.

  The + side frequency adjustment unit 4_1 and the − side frequency adjustment unit 4_2 can be configured by a circuit that converts a digital signal informing the approach of the frequency deviation into an analog amount of voltage or pulse width. This analog amount is determined depending on the frequency / voltage characteristic of the oscillator (OSC) 1_3, and an analog amount corresponding to an appropriate change amount of the system clock frequency that is changed when one approach of the frequency deviation is detected is output.

  Although not necessarily required depending on the circuit configuration, an adjustment amount correction unit 4_3 may be provided, and the adjustment amount correction unit 4_3 may correct the frequency adjustment width and sensitivity. In that case, the frequency change direction is instructed by the + side frequency adjustment unit 4_1 and the − side frequency adjustment unit 4_2, and the adjustment amount correction unit 4_3 performs conversion to an analog amount in accordance with the frequency / voltage characteristics of the oscillator (OSC) 1_3. It can be set as the structure to perform.

  In addition, depending on the response characteristics of the oscillator (OSC) 1_3, for example, when correcting the slope of the frequency / voltage characteristics, or when starting up the device, in order to create a stable frequency state at a high speed, the frequency adjustment must be made strongly and greatly. During operation (during the main signal communication service), the adjustment amount correction unit 4_3 may perform adjustment of the control amount, such as control that is as weak or small as the handling of the frequency fluctuation error.

[3] Configuration Example of Clock Synchronization Circuit FIG. 5 shows a configuration example of a clock synchronization circuit to which the configuration example of frequency deviation approach detection shown in FIG. 3 and the frequency adjustment configuration example shown in FIG. 4 are applied. Each component in the clock synchronization circuit shown in FIG. 5 is the same as that in the configuration examples shown in FIGS. 3, 4, 17, 19 and the like, and the same components are denoted by the same reference numerals and overlapped. The explanations made are omitted.

[4] Configuration Example for Detecting Frequency Deviation Approach by Monitoring Reference Clock FIG. 6 is a configuration example of a frequency deviation approach detection unit 1_1 that monitors the reference clock of the PLL circuit and detects the frequency deviation approach. . When the digital circuit 15_1 of the digital PLL circuit is configured as an LSI internal circuit, it is difficult to add a circuit surrounded by a broken line as shown in FIG. Therefore, as shown in FIG. 6, the approach of the frequency deviation can be detected by using the reference clock signal output from the digital circuit 15_1. This configuration example is an alternative to the configuration example of FIG.

  In FIG. 6, the clock cycle count unit 6_1 counts one cycle of the reference clock with the system clock. The count value is either n or n ± 1 as in the clock cycle counting unit 17_2 in FIG. The count value obtained by the clock cycle counting unit 6_1 is processed by the + fluctuation detecting unit 6_2, the-fluctuation detecting unit 6_3, the up / down counter 6_4, the ± 2 fluctuation detecting unit 6_5, and the occurrence time monitoring unit 6_6. The processing operation by them is the same as the + variation detecting unit 3_1 to the occurrence time monitoring unit 3_5 described in FIG.

[5] Example of Configuration for Detecting Frequency Deviation Approach by Monitoring Phase Comparison Signal of PLL Circuit FIG. 7 shows a frequency deviation approach detection unit that monitors the phase comparison signal of the PLL circuit and detects the approach of frequency deviation. A configuration example is shown. In this configuration example, the approach of the frequency deviation is detected by using a signal line that can be easily connected from the outside as in FIG. 6, and serves as an alternative to the configuration example in FIG. 3.

  The phase comparison signal output from the phase comparison unit 19_1 of the PLL circuit is often configured by using an LSI external component such as a resistor and a capacitor as the filter (low-pass filter) 19_2 of the PLL circuit. The signal is easier to extract from the outside than the configuration example.

  FIG. 8 shows a timing chart of the configuration example of FIG. The operation of the configuration example of FIG. 7 will be described with reference to FIG. The phase comparison unit 19_1, the filter 19_2, the voltage controlled oscillator (VCO) 19_3, and the frequency division unit 19_4 are the same as those described in FIG. In FIG. 7, the components surrounded by the broken line are the components added in this configuration example. The advance detection unit 7_1, the delay detection unit 7_2, the up / down counter 7_3, the ± 2 fluctuation detection unit 7_4, the occurrence time monitoring unit 7_5, the synchronization A pull-in state detection unit 7_6 and a mask unit 7_7 are provided.

  8A to 8D show timing charts of input / output waveforms in the PLL circuit described with reference to FIG. (E) of FIG. 8 has shown the phase comparison signal input into the advance detection part 7_1, the delay detection part 7_2, and the synchronous acquisition state detection part 7_6.

  As shown in FIG. 8F, the advance detection unit 7_1 and the delay detection unit 7_2 monitor the reference clock side edge of the phase comparison signal output from the phase comparison unit 19_1, and the phase of the reference clock is in the advance direction. It is monitored whether it fluctuates in the direction of delay or in the direction of delay. Here, one cycle of the reference clock in the PLL circuit 15_2 is counted by the system clock, and appears as a lead / lag of the phase of the reference clock according to the count value n ± 1. The up / down counter 7_3 to the occurrence time monitoring unit 7_5 is the same as the up / down counter 3_3 to the occurrence time monitoring unit 3_5 illustrated in FIG.

  As shown in FIG. 8G, the synchronization pull-in state detection unit 7_6 monitors the output clock side edge of the phase comparison signal output from the phase comparison unit 19_1, and the PLL 15_2 circuit operates in synchronization with the reference clock. Monitor whether or not

  When the phase of the reference clock is pulled in and in a synchronized state, the time until the edge on the output clock side of the phase comparison signal fluctuates requires a certain time width (one clock of the reference clock). When not in the pull-in state, it varies in a short time depending on the specification of the voltage controlled oscillator (VCO) 19_3.

  When the synchronous pull-in state detection unit 7_6 is not in the synchronous pull-in state, the mask unit 7_7 masks the generation time monitoring unit 7_5 so that the + side frequency deviation approach detection information or the −side frequency deviation approach detection information is not output. Since the peak jitter can be suppressed after the PLL circuit 15_2 has been synchronized, when the PLL circuit 15_2 is not synchronized, priority is given to the synchronization circuit of the PLL circuit 15_2 and the frequency of the system clock is not changed. Mask like so.

[6] Configuration Example for Adjusting System Clock Frequency by Controlling Power Supply Voltage FIG. 9 shows a configuration example for changing the oscillation frequency of the fixed oscillator (OSC) by controlling the power supply voltage. In FIG. 9, a digital circuit 15_1, a PLL circuit 15_2, and an oscillator (OSC) 1_3 are the same as those shown in FIG. The frequency deviation approach detection unit 1_1 can use any one of the configuration examples of [1], [4], and [5] described above.

  The frequency adjusting unit 9_1 converts the digital signal that notifies the approach of the frequency deviation from the frequency deviation approach detecting unit 1_1 into an analog signal that adjusts the power supply voltage of the fixed oscillator (OSC) 15_3. The power supply circuit 9_2 is a power supply circuit that supplies power to the fixed oscillator (OSC) 15_3, and a power supply circuit such as a DC-DC converter or a power supply regulator can be used.

  The analog amount output from the frequency adjustment unit 9_1 depends on the circuit configuration of the power supply circuit 9_2 and the characteristics of the fixed oscillator (OSC) 15_3, and is determined according to the influence of individual differences of the fixed oscillator (OSC) 15_3. The adjustment value of the voltage / resistance value of the power supply circuit 9_2 can be generated from the number of times of input of the digital signal for notifying the approach of the frequency deviation and the frequency control direction (polarity).

  In this configuration example, it is difficult to finely adjust the frequency, and the power supply voltage is expected to vary to some extent due to the influence of external factors such as the environmental temperature. However, since the effect of suppressing the temporary peak jitter can be sufficiently obtained only by shifting the frequency deviation of the fixed oscillator (OSC) 15_3 by a certain value or more with respect to the input clock, the frequency deviation approach detection unit 1_1 Even if the power supply voltage is changed slowly until the output is lost, and the control is stopped only when the output is lost, the generation of wander can be prevented, which can be an inexpensive alternative to the configuration example of FIG.

[7] Example of Configuration for Adjusting System Clock Frequency by Controlling Ambient Temperature FIG. 10 shows a configuration example for changing the oscillation frequency of the fixed oscillator (OSC) by controlling the ambient temperature of the fixed oscillator (OSC). Show. In FIG. 10, a digital circuit 15_1, a PLL circuit 15_2, and a fixed oscillator (OSC) 15_3 are the same as those shown in FIG. The frequency deviation approach detection unit 1_1 can use any one of the configuration examples of [1], [4], and [5] described above.

  The frequency adjustment unit 10_1 converts the digital signal that notifies the approach of the frequency deviation from the frequency deviation approach detection unit 1_1 into an analog signal that adjusts the temperature of the fixed oscillator (OSC) 15_3. The temperature element 10_2 is a heating / cooling element or a heating element for adjusting the ambient temperature of the fixed oscillator (OSC) 15_3.

  The analog amount output from the frequency adjustment unit 10_1 depends on the attribute of the temperature element 10_2 and the characteristics of the fixed oscillator (OSC) 15_3, and is determined according to the variation curve to the ambient temperature by the temperature element 10_2. This configuration example, like the configuration example [6], is difficult to finely adjust the frequency and is affected by external factors such as environmental temperature and air volume. I can do it.

  1. Some inexpensive SONET / SDH devices are manufactured on the premise of a complete clock synchronization state in which no pointer action or staff occurs. In such a device, the timing phase of the clock to which the device is synchronized and the input transmission signal must match within a very narrow range, depending on the circuit configuration of the device itself. In many cases, the time is around 1 byte of the transmission frame.

  The wander in question is likely to approach that range and may cause transmission errors. As shown in FIG. 11, such a device is often used for a transmission device 11_3 in a lower layer than the trunk network devices 11_1 and 11_2. Therefore, clock wander can be prevented by using the above-described clock synchronization circuit for the higher-layer trunk network devices 11_1 and 11_2.

  2. In the apparatus that generates the wander of the problem, as shown in FIG. 12A, when the waveforms of the input clock and the output clock are observed simultaneously, if the frequencies are the same, as shown in FIG. The phase of the output clock oscillates with respect to the input clock, and low-speed jitter is observed. Further, when the output frequency is high and the amount of low-speed jitter is larger than one period of the output clock, as shown in (c) of FIG. 12, the waveform completely flows and is not synchronized at first glance. It looks like a state.

  As described above, this phenomenon occurs because the frequency deviation between the input clock and the system clock is close by chance, and the frequency of occurrence varies depending on the environment and the individual differences of the devices. In addition, since the waveforms of the clocks seem to flow without being synchronized, it is difficult to determine that this state is in the clock synchronized state at first glance.

  The means for confirming that the clock is in a synchronized state in device debugging, testing, etc., observes the input clock and the output clock at the same time, and confirms that the phase fluctuation of the output clock with respect to the input clock is stationary. However, this confirmation may not be possible if wander occurs. In the above-described clock synchronization circuit, it is possible to reliably create a state in which the phase variation of the output clock is stationary.

  3. In a device having a redundant configuration in a clock synchronization circuit, such as a SONET / SDH device, the clocks of the redundant configuration circuits may appear to be in an asynchronous state depending on a wander problem. FIG. 13 shows this example. The clock synchronization circuit 13_1 on the operation (W) side happens to have no jitter because the frequency deviation between the system clock and the input clock is different, but the standby (P) side. In the clock synchronization circuit 13_2, the frequency deviation approaches and jitter occurs. Accordingly, clocks having different phases are generated on the operation (W) side and the standby (P) side.

  FIG. 13A shows a case where the low-speed jitter is smaller than one clock cycle, and shows how the low-speed jitter is observed in the output clock on the standby (P) side. FIG. 13B shows a case where the low speed jitter is larger than one clock cycle, and shows a state where the waveform of the output clock on the standby (P) side flows and is observed.

  In the main signal circuit 13_3, one of the clocks of the operation (W) side and the standby (P) side clock synchronization circuit is selected and used. At this switching, a phase difference due to jitter occurs. Therefore, if the switching selection is repeated a plurality of times, the frequency / phase difference between the main signal and the input clock may be accumulated / expanded, and stuffing processing or a signal error may occur. The above-described clock synchronization circuit can prevent such a phenomenon and generate a redundant clock having no phase difference fluctuation.

  4). In a network device that performs multistage relay via a trunk network transmission line such as a SONET / SDH apparatus, the clock is also relayed to each network apparatus (node) 14_1 to 14_5 through the transmission line as shown in FIG. If there is a network device (node) that generates a wander problem during the relay, the subsequent network device (node) relays and transmits the wander.

  For this reason, when a plurality of network devices (nodes) that generate wander accidentally occur simultaneously, the wander is accumulated and superimposed. Such a phenomenon is due to an accidental combination and the occurrence frequency is very low, but it is impossible to verify and measure the accumulated peak jitter amount. The above-described clock synchronization circuit can prevent the occurrence of such an uncertain element.

  5. As already explained, due to the wander phenomenon of the problem, the SONET / SDH device cannot improve the clock accuracy of the entire network no matter how much the clock accuracy of the clock supply device is improved. Further, improving the clock accuracy of the device causes wander. However, these problems are solved by the above-described clock synchronization circuit, and the clock accuracy of the entire network is improved, so that signal transmission requiring a higher accuracy clock becomes possible. An example of signal transmission that requires such a high-precision clock is frame transmission of a broadcast video signal.

  6). The problem wander (zero crossing jitter) is an inevitable phenomenon that occurs due to the frequency difference between the system clock and the input clock of the digital PLL circuit. Therefore, the above-described clock synchronization circuit is applied in a situation where the same digital PLL circuit is used. Thus, wander (zero crossing jitter) can be prevented.

1_1 Frequency deviation approach detection unit 1_2 Frequency adjustment unit 1_3 Oscillator (OSC)
15_1 Digital circuit 15_2 PLL circuit

Claims (6)

A digital circuit that generates a reference clock in which the input clock is retimed by the system clock in the device;
A PLL circuit that generates an output clock synchronized with the reference clock;
A frequency deviation approach detecting means for detecting an approach between the frequency deviation of the input clock and the frequency deviation of the system clock;
A frequency adjusting means for adjusting a frequency of the system clock so that a difference in the frequency deviation increases when an approach of the frequency deviation is detected;
A synchronous transmission device comprising:   When the frequency deviation approach detecting means detects that the period of the input clock is counted by the system clock and that the count value counted by the clock period count unit does not change for a predetermined time or more, The synchronous transmission device according to claim 1, further comprising: means for detecting approach of deviation.   When the frequency deviation approach detecting means detects that the period of the reference clock is counted by the system clock and that the count value counted by the clock period count unit does not change for a predetermined time or more, The synchronous transmission device according to claim 1, further comprising: means for detecting approach of deviation.   The frequency deviation approach detecting means monitors a phase comparison signal output from a phase comparison unit that compares the phases of the reference clock and the output clock in the PLL circuit, and the phase comparison signal is advanced or delayed. 2. The synchronous transmission device according to claim 1, wherein when a change is not detected for a certain period of time is detected, an approach of the frequency deviation is detected.   As the frequency adjusting means, a means for adjusting the control voltage of the voltage controlled oscillator, a means for adjusting the power supply voltage of the oscillator whose oscillation frequency fluctuates due to fluctuations in the power supply voltage, or an oscillator whose oscillation frequency varies due to fluctuations in the ambient temperature. 5. The synchronous transmission apparatus according to claim 1, wherein means for adjusting the ambient temperature is used. A jitter suppression method for a clock synchronization circuit, comprising: a digital circuit that generates a reference clock in which an input clock is retimed by a system clock in the device; and a PLL circuit that generates an output clock synchronized with the reference clock.
Detecting an approach between a frequency deviation of the input clock and a frequency deviation of the system clock;
Adjusting the frequency of the system clock to increase the difference in frequency deviation when an approach in the frequency deviation is detected; and
A jitter suppression method.

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