CN101183928A - Clock switch method, clock switch unit, clock device and system - Google Patents
Clock switch method, clock switch unit, clock device and system Download PDFInfo
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- CN101183928A CN101183928A CNA2007101953673A CN200710195367A CN101183928A CN 101183928 A CN101183928 A CN 101183928A CN A2007101953673 A CNA2007101953673 A CN A2007101953673A CN 200710195367 A CN200710195367 A CN 200710195367A CN 101183928 A CN101183928 A CN 101183928A
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Abstract
The invention discloses a method embodiment for the clock switching, belonging to the technical field of the electronic communication, which comprises: judging whether the first clock signal output by the first clock module needs to be switched to the second clock signal output by the second clock module, if yes, the first clock signal with lower frequency is produced; the second clock signal and the first clock signal after the frequency decreasing are detected, and when the phases of the two clock signals are synchronous, the indicating information of the clock switching which switches the output clock signal of the first clock module to the output clock signal of the second clock module is output; according to the indicating information of the clock switching, the clock signal output by the first clock module is switched to the clock signal output by the second clock module. The invention also discloses a corresponding clock switching unit, a clock device and a system. The invention has an advantage of improving the harmful effects of the system performances caused by the clock switching.
Description
Technical field
The present invention relates to the electronic communication field, relate in particular to the method, clock switch unit, clock apparatus and the system that realize clock switch.
Background technology
In some electronics or communication system,, in system, dispose more than one clock module through regular meeting for improving the reliability of clock module.To dispose two clock modules is example (below be called first clock module and second clock module), in system's running, first clock module and second clock module all are in running status, if wherein first clock module is in main with state (first clock module is the active clock module accordingly), provide clock signal to business board, and the second clock module is when being in stand-by state (second clock module accordingly for standby clock module), if first clock module breaks down, for continuing to provide correct clock signal to business board, the second clock module can be become the main state of using, and first clock module is become stand-by state, make the second clock module provide clock signal to business board.
Fig. 1 is the clock system structure chart in a kind of communication system of prior art, and this system comprises first clock module, second clock module and business board;
First clock module is exported first clock signal to business board, and the first activestandby state indication information that is used to indicate the first clock module current state; The second clock module is to business board output second clock signal, and the second activestandby state indication information that is used to indicate second clock module current state.
Business board comprises main-slave control cell and selected cell; The main-slave control cell main-slave control cell is according to the first activestandby state indication information and the second activestandby state indication information, and output is used to indicate the clock selecting information of current active clock module; Selector selects the clock signal of the indicated current active clock module output of clock selecting information to export from first clock signal and second clock signal.
The clock switch process of above-mentioned clock system is: first clock module is in to be led when using state, the second clock module is in stand-by state, at this moment, the clock selecting information of main-slave control cell output is that indication first clock module is current active clock module, and selector then selects first clock signal to export.If first clock module breaks down (or receiving the state variation indication), first control unit with the first activestandby state indication information from before first clock module be main be that first clock module is a stand-by state with Status Change, second control unit is that to change to the second clock module be to lead the state of using to stand-by state with the second activestandby state indication information from the second clock module of indication before then.Main-slave control cell is according to the above-mentioned variation of the first activestandby state indication information and the second activestandby state indication information, the clock selecting information-change of output makes selector select the second clock signal to export for indication second clock module is current active clock module.
In above-mentioned clock switch process, when first clock module breaks down (or receiving the state variation indication), first control unit and second control unit can change the activestandby state indication information of exporting immediately, selector is switched from first clock signal be the second clock signal, yet, if when switching, first clock signal and second clock signal all are and the satellite clock signal Synchronization, owing to there is time-delay between the different clocks module, and the phase-locked difference of phase-locked loop in the different clocks module, making win clock signal and second clock signal usually is with homophase frequently but not, like this, in the clock switch process, produce unnecessary clock pulse probably, or the clock cycle have greatly changed (can referring to figs. 2 and 3), thereby cause system to automatically reset or systematic function produced other harmful effects.
Summary of the invention
The technical problem that the embodiment of the invention will solve is to realize method, clock switch unit, clock apparatus and the system of clock switch.
For solving the problems of the technologies described above, embodiments of the invention provide following technical scheme:
A kind of method that realizes clock switch comprises:
Judge whether and to switch the second clock signal of exporting into the second clock module from first clock signal of first clock module output, if then produce first clock signal that frequency reduces;
First clock signal after described second clock signal and the reduction of described frequency is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module;
According to described clock switch indication information, switch the clock signal of exporting into the second clock module from the clock signal of first clock module output.
A kind of clock switch unit comprises judging unit and detecting unit:
Judging unit is used to judge whether and need switches the second clock signal of exporting into the second clock module from first clock signal of first clock module output;
The result that detecting unit is used in above-mentioned judgement is under the condition that is, first clock signal after described second clock signal and the frequency reduction is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
A kind of clock apparatus comprises star card unit, clock phase-locked loop unit and clock switch unit;
Described star card unit is used for according to satellite reference signal outputting standard signal;
Described clock phase-locked loop unit is used for according to described standard signal, and producing also, output frequency is first clock signal of specific objective value;
Described clock switch unit is used to judge whether and need switches the second clock signal of exporting into another clock module from first clock signal;
It is under the condition that is that described clock phase-locked loop unit also is used in above-mentioned judged result, produces also first clock signal of output frequency reduction;
The result that described clock switch unit also is used in above-mentioned judgement is under the condition that is, first clock signal after described second clock signal and the reduction of described frequency is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
A kind of clock system comprises first clock module, second clock module, clock switch unit and clock switch performance element;
Described first clock module is used to produce and output frequency is first clock signal of a specific objective value;
Described second clock module is used to produce and output frequency is the second clock signal of described specific objective value;
Described clock switch unit is used to judge whether to switch from first clock signal and is the second clock signal;
The result that described first clock module also is used in above-mentioned judgement is under the condition that is, produces also first clock signal of output frequency reduction;
The result that described clock switch unit also is used in above-mentioned judgement is under the condition that is, the first clock clock signal after described second clock signal and the reduction of described frequency is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module;
When described clock switch performance element is used for according to described clock switch indication information, switch clock signal into the output of second clock module from the clock signal of first clock module output.
In the embodiment of the invention, only take place just to switch when synchronous in the phase place of determining first clock signal and second clock signal, thereby can avoid the unnecessary clock pulse of contingent generation in the prior art scheme, or clock cycle problem such as have greatly changed.Because before needs carry out clock switch, first clock signal and second clock signal usually are with homophase frequently but not, for making two signals that Phase synchronization can take place, the embodiment of the invention takes to make the frequency of first clock signal to reduce, the mode that the frequency of second clock signal then remains unchanged, like this, first clock signal and second clock signal are bound to take place Phase synchronization in certain particular moment.To sum up, the embodiment of the invention can be improved the harmful effect that clock switch brings systematic function.
Description of drawings
Fig. 1 is the structure chart of a kind of clock system of prior art;
Fig. 2 is the clock signal schematic diagram that produces unnecessary clock pulse in the prior art clock switch process;
Fig. 3 is the clock signal schematic diagram that the clock cycle changes in the prior art clock switch process;
Fig. 4 is the structure chart of clock system embodiment one of the present invention;
Fig. 5 is the structure chart of clock system embodiment two of the present invention;
Fig. 6 is the structure chart of clock switch of the present invention unit embodiment one;
Fig. 7 is the structure chart of clock apparatus embodiment one of the present invention;
Fig. 8 is the structure chart of clock apparatus embodiment two of the present invention;
Fig. 9 is the flow chart that the present invention realizes the method embodiment one of clock switch;
Figure 10 is the clock signal schematic diagram of clock switch process of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiment of method, clock switch unit, clock apparatus and the system of realization clock switch provided by the invention is described in detail.
Clock system embodiment one of the present invention; With reference to figure 4, described system comprises first clock module 410, second clock module 420, clock switch unit 430 and clock switch performance element 440; Wherein:
The result that first clock module 410 also is used in above-mentioned judgement is under the condition that is, produces also first clock signal of output frequency reduction.
The result that clock switch unit 430 also is used in above-mentioned judgement is under the condition that is, respectively the first clock clock signal after second clock signal and the frequency reduction is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
Clock switch performance element 440 when being used for according to described clock switch indication information, is switched clock signal into the second clock module from the clock signal of first clock module.
Clock system embodiment two of the present invention; With reference to figure 5, described system comprises first clock module 510, second clock module 520, clock switch unit 530 and clock switch performance element 540; Wherein:
First clock module 510 is used to produce and output frequency is first clock signal of a specific objective value; Comprise that specifically the first star card unit 511 and 512: the first star cards unit, the first clock phase-locked loop unit 511 are used for according to satellite reference signal outputting standard signal; The first clock phase-locked loop unit 512 is used for according to standard signal, and producing also, output frequency is first clock signal of described specific objective value; Wherein, described standard signal can be pulse per second (PPS) (1PPS) signal.
Second clock module 520 is used to produce and output frequency is the second clock signal of described specific objective value; Comprise that specifically the second star card unit 521 and 522: the second star cards of second clock phase locked-loop unit unit 521 are used for according to satellite reference signal outputting standard signal; Second clock phase locked-loop unit 522 is used for according to standard signal, and producing also, output frequency is the second clock signal of described specific objective value; Wherein, described standard signal can be the 1PPS signal.
Clock switch unit 530 comprises judging unit 531, is used to judge whether to switch from first clock signal be the second clock signal; Wherein, whether judging unit 531 can break down by detecting first clock module, or detects the state variation whether receive first clock module and indicate to judge whether to switch from first clock signal and be the second clock signal.
The result that the first clock phase-locked loop unit 512 also is used in above-mentioned judgement is under the condition that is, produces also first clock signal of output frequency reduction.
Clock switch unit 530 also comprises detecting unit 532, the result who is used in above-mentioned judgement is under the condition that is, respectively first clock signal after second clock signal and the frequency reduction is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
Clock switch performance element 540 is used for according to described clock switch indication information, switches the clock signal of exporting into the second clock module from the clock signal of first clock module output.
Wherein, the first clock phase-locked loop unit 512 further comprises logical block 5121, D/A conversion unit 5122, the first low frequency filtering unit 5123, reference clock generation unit 5124, the second phase demodulation unit 5125, the second low frequency filtering unit 5126 and output clock generating unit 5127;
Logical block 5121 comprises that specifically the first phase demodulation unit 5128, switch unit 5129 and 5130: the first phase demodulation unit 5128 of selected cell are used for the reference clock signal of standard signal and 5124 generations of reference clock generation unit is carried out phase demodulation, by the specific control algolithm that presets the phase difference that phase demodulation obtains is handled, obtained exporting after the numerical frequency control signal; The result that switch unit 5129 is used in the judgement of clock switch unit 530 is under the condition that is, exports after the numerical frequency control signal that acquisition reduces the frequency of first clock signal; Selected cell 5130 is used for selecting one of them to export from the numerical frequency control signal of the numerical frequency control signal of the first phase demodulation unit, 5128 outputs and switch unit 5129 outputs, specifically, result in the judgement of clock switch unit 530 is under the condition that is, select the numerical frequency control signal of switch unit 5129 outputs to export, in the result who judges is under the condition not, selects the numerical frequency control signal of the first phase demodulation unit, 5128 outputs to export.
D/A conversion unit 5122 is used for the numerical frequency control signal of selected cell 5130 outputs is carried out digital-to-analogue conversion, obtains the first analog frequency control signal.
The first low frequency filtering unit 5123 is used for the described first analog frequency control signal is carried out low frequency filtering.
Reference clock generation unit 5124 is used to export by the reference clock signal that carries out the first analog frequency generation that control signal is controlled behind the low frequency filtering.
The second phase demodulation unit 5125 is used for reference clock signal that reference clock generation unit 5124 is produced and first clock signal that output clock generating unit 5127 produces and simulates phase demodulation, obtains the second analog frequency control signal.
The second low frequency filtering unit 5126 is used for the described second analog frequency control signal is carried out low frequency filtering.
Output clock generating unit 5127 is used to export first clock signal by carrying out the filtered second analog frequency generation that control signal is controlled.
When selecting the numerical frequency control signal of the unit 5130 output first phase demodulation unit, 5128 outputs, reference clock generation unit 5124 produces the canonical reference clock signal, and it is first clock signal of described specific objective value that output clock generating unit 5127 produces frequency; When selecting the numerical frequency control signal of unit 5130 output switch units, 5129 outputs, reference clock generation unit 5124 produces the reference clock signal that frequency reduces, and 5127 of output clock generating unit produce first clock signal that the frequency equal proportion reduces.
Clock system embodiment three of the present invention; Present embodiment and clock system embodiment one of the present invention or embodiment two are similar, and the difference part is that in the present embodiment, detecting unit comprises:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase;
Idol pps pulse per second signal detecting unit, be used for the PP2S signal of described first clock module and the generation of described second clock module is detected, when the PP2S signal of described first clock module and the generation of described second clock module all is high level, output high level indication information;
Clock switch indication information output unit, when being used for receiving at the same time Phase synchronization indication information and high level indication information, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
In code division multiple access (CDMA) 2000 clock systems, can use the PP2S signal of clock module that the clock signal of output is counted, if the cycle at PP2S cycle internal clock signal surpasses a particular value, beyond retrieve mistake will appear in the bottom layer driving of system, therefore, in the embodiment of the invention, the clock switch unit only takes place synchronously in the phase place that detects described two clock signals, and when the PP2S signal that first clock module and second clock module produce all is high level, just exports from first clock signal and switch clock switch indication information into the second clock signal.
In the more embodiment of clock system of the present invention, the second clock phase locked-loop unit can adopt the two-stage phase-locked loop manner to realize.
In the more embodiment of clock system of the present invention, first clock module also comprises first control unit, is used for the clock switch indication information according to the output of clock switch unit, and output indication first clock module is in the first activestandby state indication information of stand-by state; The second clock module also comprises second control unit, is used for the clock switch indication information according to the output of clock switch unit, and output indication second clock module is in the main first activestandby state indication information with state.The clock switch performance element can comprise main-slave control cell and selected cell: main-slave control cell is used for according to the first activestandby state indication information and the second activestandby state indication information, and output indication second clock module is the clock selecting information of current active clock module; Selected cell is used for selecting the second clock signal to export from first clock signal and second clock signal.
In the more embodiment of clock system of the present invention, described clock switch unit also can be integrated in first clock module.
Clock switch of the present invention unit embodiment one; With reference to figure 6, described clock switch unit comprises judging unit 610 and detecting unit 620:
Judging unit 610 is used to judge whether and need switches the second clock signal of exporting into the second clock module from first clock signal of first clock module output; Wherein, whether judging unit 610 can break down by detecting first clock module, or detects the state variation whether receive first clock module and indicate to judge whether to switch from first clock signal and be the second clock signal.
The result that detecting unit 620 is used in above-mentioned judgement is under the condition that is, respectively first clock signal after second clock signal and the frequency reduction is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
Clock switch of the present invention unit embodiment two; Present embodiment and clock switch of the present invention unit embodiment one are similar, and the difference part is that in the present embodiment, detecting unit comprises:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase;
Clock switch indication information output unit is used for when receiving described Phase synchronization indication information, and output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
Clock switch of the present invention unit embodiment three; Present embodiment and clock switch of the present invention unit embodiment one are similar, and the difference part is that in the present embodiment, detecting unit comprises:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase.
Idol pps pulse per second signal detecting unit, be used for the PP2S signal of described first clock module and the generation of described second clock module is detected, when the PP2S signal of described first clock module and the generation of described second clock module all is high level, output high level indication information.
Clock switch indication information output unit, when being used for receiving at the same time Phase synchronization indication information and high level indication information, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
Clock apparatus embodiment one of the present invention, with reference to figure 7, described clock apparatus comprises star card unit 710, clock phase-locked loop unit 720 and clock switch unit 730;
Star card unit 710 is used for according to satellite reference signal outputting standard signal.
Clock phase-locked loop unit 720 is used for according to standard signal, and producing also, output frequency is first clock signal of specific objective value; Wherein, described standard signal can be the 1PPS signal.
It is under the condition that is that clock phase-locked loop unit 720 also is used in above-mentioned judged result, produces also first clock signal of output frequency reduction.
The result that clock switch unit 730 also is used in above-mentioned judgement is under the condition that is, respectively first clock signal after second clock signal and the frequency reduction is detected, take place when synchronous in the phase place that detects described two clock signals, output is switched clock signal clock switch indication information into the second clock module from the clock signal of first clock module.
Clock apparatus embodiment two of the present invention; With reference to figure 8, described clock apparatus comprises star card unit 810, clock phase-locked loop unit 820 and clock switch unit 830;
Clock phase-locked loop unit 820 is used for according to standard signal, and producing also, output frequency is first clock signal of specific objective value; Wherein, described standard signal can be the 1PPS signal.
It is under the condition that is that clock phase-locked loop unit 820 also is used in above-mentioned judged result, produces also first clock signal of output frequency reduction.
The result that clock switch unit 830 also is used in above-mentioned judgement is under the condition that is, respectively first clock signal after second clock signal and the frequency reduction is detected, take place when synchronous in the phase place that detects described two clock signals, output is switched clock signal clock switch indication information into the second clock module from the clock signal of first clock module.
Wherein, clock phase-locked loop unit 820 specifically comprises logical block 821, D/A conversion unit 822, the first low frequency filtering unit 823, reference clock generation unit 824, the second phase demodulation unit 825, the second low frequency filtering unit 826 and output clock generating unit 827;
Logical block 821 specifically comprises the first phase demodulation unit 828, switch unit 829 and selected cell 800:
The first phase demodulation unit 828 is used for the reference clock signal of standard signal and 824 generations of reference clock generation unit is carried out phase demodulation, by the specific control algolithm that presets the phase difference that phase demodulation obtains is handled, and obtains exporting after the numerical frequency control signal.
The result that switch unit 829 is used in the judgement of clock switch unit 830 is under the condition that is, exports after the numerical frequency control signal that acquisition reduces the frequency of first clock signal.
D/A conversion unit 822 is used for the numerical frequency control signal of selected cell 800 outputs is carried out digital-to-analogue conversion, obtains the first analog frequency control signal.
The first low frequency filtering unit 823 is used for the described first analog frequency control signal is carried out low frequency filtering.
Reference clock generation unit 824 is used to export by the reference clock signal that carries out the first analog frequency generation that control signal is controlled behind the low frequency filtering.
The second phase demodulation unit 825 is used for reference clock signal that reference clock generation unit 824 is produced and first clock signal that output clock generating unit 827 produces and simulates phase demodulation, obtains the second analog frequency control signal.
The second low frequency filtering unit 826 is used for the described second analog frequency control signal is carried out low frequency filtering.
Output clock generating unit 827 is used to export first clock signal by carrying out the filtered second analog frequency generation that control signal is controlled.
When selecting the numerical frequency control signal of the unit 800 output first phase demodulation unit, 828 outputs, reference clock generation unit 824 produces the canonical reference clock signal, and it is first clock signal of described specific objective value that output clock generating unit 827 produces frequency; When selecting the numerical frequency control signal of unit 830 output switch units, 829 outputs, reference clock generation unit 824 produces the reference clock signal that frequency reduces, and 827 of output clock generating unit produce first clock signal that the frequency equal proportion reduces.
In the more embodiment of clock apparatus of the present invention, the clock switch unit comprises:
Judging unit is used to judge whether and need switches the second clock signal of exporting into the second clock module from first clock signal of first clock module output.
Detecting unit, the result who is used in above-mentioned judgement is under the condition that is, first clock signal after described second clock signal and the frequency reduction is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.Described detecting unit can comprise.
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase.
Clock switch indication information output unit is used for when receiving described Phase synchronization indication information, and output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
In the more embodiment of clock apparatus of the present invention, described detecting unit also can comprise:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase.
Idol pps pulse per second signal detecting unit, be used for the PP2S signal of described first clock module and the generation of described second clock module is detected, when the PP2S signal of described first clock module and the generation of described second clock module all is high level, output high level indication information.
Clock switch indication information output unit, when being used for receiving at the same time Phase synchronization indication information and high level indication information, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
In the more embodiment of clock apparatus of the present invention, described clock switch unit is integrated in the clock phase-locked loop unit.
The present invention realizes the method embodiment one of clock switch; With reference to figure 9, present embodiment provides the basic procedure that the present invention realizes clock switch, comprising:
Whether A1, clock switch unit judges need to switch the second clock signal of exporting into the second clock module from first clock signal of first clock module output, if then produce first clock signal that frequency reduces.
Wherein, whether the clock switch unit can break down by detecting first clock module, or detects the state variation whether receive first clock module and indicate to judge whether to switch from first clock signal and be the second clock signal.
A2, described clock switch unit detect first clock signal after second clock signal and the frequency reduction respectively, take place when synchronous in the phase place of described two clock signals, switch clock switch indication information from the clock signal of first clock module into the clock signal of second clock module to business board output.
A3, described business board are switched the clock signal of exporting into the second clock module according to described clock switch indication information from the clock signal of first clock module output.
The present invention realizes the method embodiment two of clock switch; This method comprises:
Whether B1, clock switch unit judges need to switch the second clock signal of exporting into the second clock module from first clock signal of first clock module output, if then produce first clock signal that frequency reduces.
B2, described clock switch unit detect first clock signal after second clock signal and the frequency reduction respectively, take place when synchronous in the phase place of described two clock signals, if the PP2S signal that detects first clock module and second clock module all is a high level, then switch clock switch indication information from the clock signal of first clock module into the clock signal of second clock module to business board output.
B3, described business board are switched the clock signal of exporting into the second clock module according to described clock switch indication information from the clock signal of first clock module output.
Realize among each embodiment of method of clock switch in the present invention, can produce first clock signal that frequency reduces by the following method:
The numerical frequency control signal that C1, acquisition reduce the frequency of first clock signal.
C2, the numerical frequency Control Parameter that is obtained is carried out digital-to-analogue conversion, obtain the first analog frequency control signal.
C3, the first analog frequency control signal is carried out low frequency filtering.
The first module frequency control signal that C4, basis are carried out behind the low frequency filtering produces the reference clock signal that frequency reduces.
C5, the described reference clock signal and first clock signal are simulated phase demodulation, obtain the second analog frequency control signal.
C6, the described second analog frequency control signal is carried out low frequency filtering.
The second module frequency control signal that C7, basis are carried out behind the low frequency filtering produces first clock signal that the frequency equal proportion reduces.
Realizing that in the present invention among each embodiment of method of clock switch, the clock switch unit can be integrated on the first clock template or second clock template or other physical entities, can also be an independent entity.
In various embodiments of the present invention, described satellite clock signal can be meant global positioning system (GlobalPosition System, be called for short GPS) clock signal, or GLONASS (Global Navigation Satellite System) (Global NavigationSatellite System is called for short GLONASS) clock signal.
In various embodiments of the present invention, described output clock generating unit can be VCXO (VCXO), and described reference clock generation unit can be a thermostatic control formula crystal oscillator (OCXO).
In various embodiments of the present invention, first clock signal that described generation frequency reduces specifically can be: produce with first clock signal of first clock module previous moment output and compare, frequency reduce amplitude less than ten thousand/ first clock signal.
In various embodiments of the present invention, described level variation can be meant from low level and become high level, also can be meant from high level to become low level.
In various embodiments of the present invention, whether first clock signal after can detecting frequency by the following method and reducing and the phase place of second clock signal take place synchronously: after a level that detects first clock signal after frequency reduces changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described frequency first clock signal after reducing change the preceding once equidirectional level that occurs in the second clock signal change before the time, confirm that the phase place of described two clock signals takes place synchronously.
With reference to Figure 10, in the embodiment of the invention, only take place just to switch when synchronous, thereby can avoid the unnecessary clock pulse of contingent generation in the prior art scheme in the phase place of determining first clock signal and second clock signal, or clock cycle problem such as have greatly changed.Because before needs carry out clock switch, first clock signal and second clock signal usually are with homophase frequently but not, for making two signals that Phase synchronization can take place, the embodiment of the invention takes to make the frequency of first clock signal to reduce, the mode that the frequency of second clock signal then remains unchanged, like this, first clock signal and second clock signal are bound to take place Phase synchronization in certain particular moment.To sum up, the embodiment of the invention can be improved the harmful effect that clock switch brings systematic function.
More than method, clock switch unit, clock apparatus and the system of the realization clock switch that the embodiment of the invention provided is described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and thought thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (14)
1. a method that realizes clock switch is characterized in that, comprising:
Judge whether and to switch the second clock signal of exporting into the second clock module from first clock signal of first clock module output, if then produce first clock signal that frequency reduces;
First clock signal after described second clock signal and the reduction of described frequency is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module;
According to described clock switch indication information, switch the clock signal of exporting into the second clock module from the clock signal of first clock module output.
2. the method for realization clock switch as claimed in claim 1, it is characterized in that, whether the phase place that detects described two clock signals by the following method takes place synchronously: after a level that detects first clock signal after described frequency reduces changes the equidirectional level variation that occurs in described second clock signal, and the preceding once equidirectional level of described frequency first clock signal after reducing change the preceding once equidirectional level that occurs in described second clock signal change before the time, confirm that the phase place of described two clock signals takes place synchronously.
3. the method for realization clock switch as claimed in claim 2 is characterized in that, produces first clock signal that frequency reduces by the following method:
The numerical frequency control signal that acquisition reduces the frequency of first clock signal;
The numerical frequency Control Parameter that is obtained is carried out digital-to-analogue conversion, obtain the first analog frequency control signal;
Produce the reference clock signal that frequency reduces according to the described first analog frequency control signal;
Described reference clock signal and described first clock signal are simulated phase demodulation, obtain the second analog frequency control signal;
Produce first clock signal that frequency reduces according to the described second analog frequency control signal.
4. as the method for claim 2 or 3 described realization clock switch, it is characterized in that, first clock signal that described generation frequency reduces is specifically: produce with first clock signal of first clock module previous moment output and compare, frequency reduce amplitude less than ten thousand/ first clock signal.
5. as the method for claim 2 or 3 described realization clock switch, it is characterized in that described level variation specifically is meant from low level and becomes high level.
6. as the method for claim 1 or 2 or 3 described realization clock switch, it is characterized in that, take place when synchronous in the phase place of described two clock signals, if detecting the even pulse per second (PPS) PP2S signal of described first clock module and described second clock module generation all is high level, just carry out the step of described output clock switch indication information.
7. a clock switch unit is characterized in that, comprises judging unit and detecting unit:
Judging unit is used to judge whether and need switches the second clock signal of exporting into the second clock module from first clock signal of first clock module output;
The result that detecting unit is used in above-mentioned judgement is under the condition that is, first clock signal after described second clock signal and the frequency reduction is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
8. clock switch as claimed in claim 7 unit is characterized in that, described detecting unit comprises:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase;
Clock switch indication information output unit is used for when receiving described Phase synchronization indication information, and output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
9. clock switch as claimed in claim 7 unit is characterized in that, described detecting unit comprises:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase;
Idol pps pulse per second signal detecting unit, be used for the PP2S signal of described first clock module and the generation of described second clock module is detected, when the PP2S signal of described first clock module and the generation of described second clock module all is high level, output high level indication information;
Clock switch indication information output unit, when being used for receiving at the same time Phase synchronization indication information and high level indication information, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
10. a clock apparatus is characterized in that, comprises star card unit, clock phase-locked loop unit and clock switch unit;
Described star card unit is used for according to satellite reference signal outputting standard signal;
Described clock phase-locked loop unit is used for according to described standard signal, and producing also, output frequency is first clock signal of specific objective value;
Described clock switch unit is used to judge whether and need switches the second clock signal of exporting into another clock module from first clock signal;
It is under the condition that is that described clock phase-locked loop unit also is used in above-mentioned judged result, produces also first clock signal of output frequency reduction;
The result that described clock switch unit also is used in above-mentioned judgement is under the condition that is, first clock signal after described second clock signal and the reduction of described frequency is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
11. clock apparatus as claimed in claim 10 is characterized in that, described clock phase-locked loop unit specifically comprises logical block, D/A conversion unit, reference clock generation unit, the second phase demodulation unit and output clock generating unit;
Described logical block specifically comprises the first phase demodulation unit, switch unit and selected cell;
The described first phase demodulation unit is used for the reference clock signal of standard signal and the generation of described reference clock generation unit is carried out phase demodulation, by the specific control algolithm that presets the phase difference that phase demodulation obtains is handled, and obtains exporting after the numerical frequency control signal;
The result that described switch unit is used in the judgement of described clock switch unit is under the condition that is, exports after the numerical frequency control signal that acquisition reduces the frequency of first clock signal;
Described selected cell is used for selecting one of them to export from the numerical frequency control signal of the numerical frequency control signal of described first phase demodulation unit output and the output of described switch unit; Wherein, result in the judgement of described clock switch unit is under the condition that is, selecting the numerical frequency control signal of described switch unit output to export, is under the condition not in the result who judges, selects the numerical frequency control signal of described first phase demodulation unit output to export;
Described D/A conversion unit is used for the numerical frequency control signal of described selected cell output is carried out digital-to-analogue conversion, obtains the first analog frequency control signal;
Described reference clock generation unit is used to export the reference clock signal by the described first analog frequency generation that control signal is controlled;
The described second phase demodulation unit is used for first clock signal of the reference clock signal of described reference clock generation unit generation and the generation of described output clock generating unit is simulated phase demodulation, obtains the second analog frequency control signal;
Described output clock generating unit is used to export first clock signal that is produced by described second analog frequency control signal control.
12., it is characterized in that described detecting unit comprises as claim 10 or 11 described clock apparatus:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase;
Clock switch indication information output unit is used for when receiving described Phase synchronization indication information, and output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
13., it is characterized in that described detecting unit comprises as claim 10 or 11 described clock apparatus:
The Phase synchronization detecting unit, be used for first clock signal after described second clock signal and the frequency reduction is detected, after a level that detects described first clock signal changes the equidirectional level variation that occurs in the second clock signal, and the preceding once equidirectional level of described first clock signal change the preceding once equidirectional level that occurs in the second clock signal change before the time, the synchronous indication information of output phase;
Idol pps pulse per second signal detecting unit, be used for the PP2S signal of described first clock module and the generation of described second clock module is detected, when the PP2S signal of described first clock module and the generation of described second clock module all is high level, output high level indication information;
Clock switch indication information output unit, when being used for receiving at the same time Phase synchronization indication information and high level indication information, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module.
14. a clock system is characterized in that, comprises first clock module, second clock module, clock switch unit and clock switch performance element;
Described first clock module is used to produce and output frequency is first clock signal of a specific objective value;
Described second clock module is used to produce and output frequency is the second clock signal of described specific objective value;
Described clock switch unit is used to judge whether to switch from first clock signal and is the second clock signal;
The result that described first clock module also is used in above-mentioned judgement is under the condition that is, produces also first clock signal of output frequency reduction;
The result that described clock switch unit also is used in above-mentioned judgement is under the condition that is, the first clock clock signal after described second clock signal and the reduction of described frequency is detected, take place when synchronous in the phase place of described two clock signals, output is switched clock switch indication information into the clock signal of second clock module from the clock signal of first clock module;
When described clock switch performance element is used for according to described clock switch indication information, switch clock signal into the output of second clock module from the clock signal of first clock module output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101953673A CN101183928A (en) | 2007-12-13 | 2007-12-13 | Clock switch method, clock switch unit, clock device and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101953673A CN101183928A (en) | 2007-12-13 | 2007-12-13 | Clock switch method, clock switch unit, clock device and system |
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| CN101183928A true CN101183928A (en) | 2008-05-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101953673A Pending CN101183928A (en) | 2007-12-13 | 2007-12-13 | Clock switch method, clock switch unit, clock device and system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958762A (en) * | 2009-07-14 | 2011-01-26 | 中兴通讯股份有限公司 | Main and standby clock switching device and method |
| CN102833064A (en) * | 2011-06-13 | 2012-12-19 | 中兴通讯股份有限公司 | Clock recovery method for microwave transmission and device |
| CN101615965B (en) * | 2009-07-13 | 2013-08-07 | 中兴通讯股份有限公司 | Method and device for switching master/backup clock |
| WO2019109356A1 (en) * | 2017-12-08 | 2019-06-13 | 深圳开阳电子股份有限公司 | Clock system, electronic apparatus, and processing method |
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2007
- 2007-12-13 CN CNA2007101953673A patent/CN101183928A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101615965B (en) * | 2009-07-13 | 2013-08-07 | 中兴通讯股份有限公司 | Method and device for switching master/backup clock |
| CN101958762A (en) * | 2009-07-14 | 2011-01-26 | 中兴通讯股份有限公司 | Main and standby clock switching device and method |
| CN101958762B (en) * | 2009-07-14 | 2014-08-13 | 中兴通讯股份有限公司 | Main and standby clock switching device and method |
| CN102833064A (en) * | 2011-06-13 | 2012-12-19 | 中兴通讯股份有限公司 | Clock recovery method for microwave transmission and device |
| CN102833064B (en) * | 2011-06-13 | 2017-10-24 | 中兴通讯股份有限公司 | The clock recovery method and device of a kind of microwave transmission |
| WO2019109356A1 (en) * | 2017-12-08 | 2019-06-13 | 深圳开阳电子股份有限公司 | Clock system, electronic apparatus, and processing method |
| CN111418158A (en) * | 2017-12-08 | 2020-07-14 | 深圳开阳电子股份有限公司 | Clock system, electronic device and processing method |
| CN111418158B (en) * | 2017-12-08 | 2024-04-09 | 深圳开阳电子股份有限公司 | Clock system, electronic device and processing method |
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