CN105406838B - Digital frequency multiplication circuit and the method for correcting clock duty cycle - Google Patents
Digital frequency multiplication circuit and the method for correcting clock duty cycle Download PDFInfo
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Abstract
The invention discloses digital frequency multiplication circuit and the method for correcting clock duty cycle, digital frequency multiplication circuit corrects circuit, reset signal generative circuit and clock generation circuit including delay circuit, Edge check alignment circuit, duty ratio；It is characterized in that：Delay circuit includes the first delayed sequence, the second delayed sequence, third delayed sequence and the 4th delayed sequence, and each delayed sequence is controlled by the same delay control parameter of edge alignment circuit output；Edge check alignment circuit receives the signal of the 4th delayed sequence output, while receives the signal with reference clock same-phase, and two signals are carried out phase bit comparison, output delay control parameter to four delayed sequences；Duty ratio corrects the clock signal that circuit receives clock generation circuit output, while receives the signal of the first delayed sequence output, generates frequency multiplied clock signal；Circuit stability of the present invention is reliable, has many advantages, such as that area is small, portable good, can be widely used in the fields such as communication.
Description
Technical field
The present invention relates to frequency multiplier circuits, and in particular to digital frequency multiplication circuit and the method for correcting clock duty cycle.
Background technology
Simple in structure to have area advantage, for the digital frequency multiplication circuit of high accuracy in digital circuit, application is very universal.
In some communication devices, such as RFID, hand-held mobile terminal, to small area, low-power consumption, low temperature sensitivity digital frequency multiplier
Propose demand.
Traditional frequency multiplier circuit is provided usually using phaselocked loop, however the occasion of phaselocked loop is not used in system, individually
A frequency doubling clock is provided for circuit and introduces phaselocked loop, it is clear that can area increased cost.And in totally digital circuit application scenario,
This obviously can also increase the complexity of system.
Using the basic delay cell of reverser pair, it can be translated in the case where not influencing clock waveform,
Error is only limited by device delay precision.But it for the input clock of duty ratio non-50%, then needs to carry out special place
Reason, otherwise exporting frequency doubling clock will show significantly to shake.
Invention content
The technical problems to be solved by the invention are to provide digital frequency multiplication circuit and digital frequency multiplication circuit modifications clock duty
The method of ratio in the case of ensureing that input reference clock duty cycle is not 50%, is generated without the frequency doubling clock significantly shaken.
In order to solve the above-mentioned technical problem, first technical solution of the invention is：A kind of digital frequency multiplication circuit, including prolonging
Slow circuit, Edge check alignment circuit, duty ratio correct circuit, reset signal generative circuit and clock generation circuit；Its feature
It is：
Delay circuit includes the first delayed sequence, the second delayed sequence, third delayed sequence and the 4th delayed sequence, each
Delayed sequence is controlled by the same delay control parameter of Edge check alignment circuit output；To ensure each delayed sequence
Postpone identical phase.
Clock generation circuit receives external input clock signal, when generating the benchmark with external input clock signal same frequency
Clock signal is output to the first delayed sequence, Edge check alignment circuit and duty ratio and corrects circuit；And clock generation circuit is also
The reset signal of reset signal generative circuit output is received, to adjust the duty ratio of reference clock signal；
First delayed sequence receives the reference clock signal of clock generation circuit output, and week is set to the signal delay received
The second delayed sequence is output to after phase and duty ratio corrects circuit；
Second delayed sequence receives the signal of the first delayed sequence output, is exported after setting the period to the signal delay received
To third delayed sequence and reset signal generative circuit；
Third delayed sequence receives the signal of the second delayed sequence output, is exported after setting the period to the signal delay received
To the 4th delayed sequence；
4th delayed sequence receives the signal of third delayed sequence output, to being exported after the signal delay setting time that receives
To Edge check alignment circuit；When the signal of the second delayed sequence output postpones half period than reference clock signal, the 4th
The signal of delayed sequence output postpones a cycle than reference clock signal；
Edge check alignment circuit receives the signal of the 4th delayed sequence output, while receives clock generation circuit output
This two signals are carried out phase bit comparison, output delay control parameter to four delayed sequences by reference clock signal；
Reset signal generative circuit receives the signal of the second delayed sequence output, and generation reset signal is output to clock generation
Circuit；To be modified to the clock signal that clock generation circuit exports, when the signal of the second delayed sequence output is than benchmark
During clock signal delay half period, the reset signal of generation makes the clock signal that clock generation circuit output duty cycle is 50%；
Duty ratio corrects the clock signal that circuit receives clock generation circuit output, while receives the output of the first delayed sequence
Signal, after being handled, export frequency multiplied clock signal, with prevent output clock jitter.
The present invention checks that input clock edge and the 4th delayed sequence export clock edge by Edge check alignment circuit
Phase, when the 4th time-delayed sequence output clock is aligned with reference clock edge, it is ensured that each 90 ° of time-delayed sequence delay
Phase, the signal of the second time-delayed sequence output at this time are just in reference clock signal half period position.Again by by benchmark
Clock signal carries out logical operation with the second delayed sequence output clock signal, can obtain the standard time clock that duty ratio is 50%.
In order to obtain frequency doubling clock, 90 ° of time delayed signals by reference clock and the output of the first delayed sequence is needed to carry out xor operation, are
Prevent output clock jitter, 90 ° of time delayed signals must use duty ratio for 50% clock.The present invention is transported by a series of logics
It calculates, has dexterously been multiplexed four necessary time-delayed sequences, construct the clock for being 50% with the duty ratio of frequency with reference clock, from
And it avoids the frequency doubling clock caused by duty ratio and shakes.
The preferred embodiment of digital frequency multiplication circuit according to the present invention, each delayed sequence include n delay cell
With a selector, n takes positive integer；N delay cell is connected in series with, and each delay cell outputs signals to selector；
Selector is postponed controlling for control parameter by Edge check alignment circuit output, is exported after selecting the signal received.
The preferred embodiment of digital frequency multiplication circuit according to the present invention, each delay cell is by 2 reversers series connection structures
Into.
The present invention second technical solution be：A kind of method of digital frequency multiplication circuit modifications clock duty cycle, including such as
Lower step：
(1), judge the 4th delayed sequence output signal ratio clock generation circuit output reference clock signal delay whether
It it has been more than a clock cycle, if being not above a clock cycle, adjustment delay control parameter makes the 4th delayed sequence defeated
Go out signal and be more than a clock cycle than reference clock signal delay；
(2) when the reference clock signal delay for detecting the output of the 4th delayed sequence output signal ratio clock generation circuit
It has been more than a clock cycle, adjustment delay control parameter reduced for the 4th delayed sequence output signal delay time, even if the
Rising edge of the rising edge of four delayed sequence output signals to reference clock signal in next clock cycle approaches；
(3), judge the rising edge of the 4th delayed sequence output signal with reference clock signal in next clock cycle
Whether rising edge exists without phase difference when can't detect the 4th delayed sequence output signal rising edge for the first time with reference clock signal
There are during phase difference, record delay parameter, label blind area top for the rising edge of next clock cycle；Continue adjustment delay control
Parameter processed, make the rising edge of the 4th delayed sequence output signal again to reference clock signal next clock cycle rising
Along close and cross；When detecting the 4th delayed sequence output signal rising edge and reference clock signal in next clock again
The rising edge in period records delay parameter there are during phase difference, marks blind area bottom；
(4) go out the position of blind area central point, adjustment delay control ginseng according to the mathematic interpolation with blind area bottom at the top of blind area
Number, makes the rising edge of the 4th delayed sequence output signal be in this position of the central point.
The problem of this method solve rising edge check frequency central point is found, digital circuit device precision band can be eliminated
The error come, can obtain the maximal accuracy under the conditions of digital circuit.
The preferred embodiment of the method for digital frequency multiplication circuit modifications clock duty cycle according to the present invention, each postpones sequence
Row include n delay cell and a selector, n take positive integer；N delay cell is connected in series with, and each delay cell
Output signals to selector；Selector is postponed controlling for control parameter by Edge check alignment circuit output, to what is received
Signal exports after being selected.
The preferred embodiment of the method for digital frequency multiplication circuit modifications clock duty cycle according to the present invention, each delay are single
Member is in series by 2 reversers.
It digital frequency multiplication circuit of the present invention and corrects the advantageous effect of method of clock duty cycle and is：It is examined by edge
Slowdown monitoring circuit is aligned clock and its delay output, so as to be divided into a series of 90 ° of output clocks between obtaining；Simultaneously with delay
The output of half period is modified reference clock, obtains the clock signal of 50% duty ratio, avoids because of duty cycle error
Clock jitter is exported caused by and, output error is only influenced by device delay precision；The present invention is by answering time-delayed sequence
With, simplify structure, solve the problems, such as find rising edge check frequency central point, digital circuit device precision band can be eliminated
The error come, can obtain the maximal accuracy under the conditions of digital circuit；Invention circuit stability is reliable, small with area, portable
Property it is good, it is applied widely the advantages that, can be widely used in communication etc. fields.
Description of the drawings
Fig. 1 is the functional block diagram of digital frequency multiplication circuit of the present invention.
Fig. 2 is the functional block diagram of time-delayed sequence.
Fig. 3 is the flow chart of the method for the present invention for correcting clock duty cycle.
Fig. 4 is the approximate procedure of Edge check alignment in start-up course.
Fig. 5 is that the new clock of 50% duty ratio generates process.
Fig. 6 is that frequency doubling clock generates process.
Specific embodiment
Referring to Fig. 1, a kind of digital frequency multiplication circuit corrects electricity including delay circuit 1, Edge check alignment circuit 2, duty ratio
Road 3, reset signal generative circuit 4 and clock generation circuit 5；
Delay circuit 1 includes the first delayed sequence 11, the second delayed sequence 12, third delayed sequence 13 and the 4th and postpones sequence
Row 14, each delayed sequence are controlled by the same delay control parameter that Edge check alignment circuit 2 exports；To ensure it
Delay phase be identical；Clock generation circuit 5 is made of register, and newly-generated signal is exported by the Q ends of register
Clk, this signal are delayed by four time-delayed sequences, and time-delayed sequence is somebody's turn to do according to delay selection of control parameter clock output phase
Delay control parameter is exported by Edge check alignment circuit 2, and four sequences are using same parameters to ensure the delay of each sequence
It is identical, it is finally reached the effect of 90 ° of phase shifts.
Clock generation circuit 5 receives reference clock signal, generates the clock signal clk with reference clock same-phase, output
Circuit 3 is corrected to the first delayed sequence, Edge check alignment circuit 2 and duty ratio；And clock generation circuit 5 also receives reset
The reset signal that signal generating circuit 4 exports, to adjust the duty ratio of reference clock signal；
First delayed sequence 11 receives the signal that clock generation circuit 5 exports, after setting the period to the signal delay received,
First delayed sequence exports clk_d1 and corrects circuit 3 to the second delayed sequence and duty ratio；
Second delayed sequence 12 receives the signal of the first delayed sequence output, after setting the period to the signal delay received,
Second delayed sequence exports clk_d2 to third delayed sequence and reset signal generative circuit 4；
Third delayed sequence 13 receives the signal of the second delayed sequence output, after setting the period to the signal delay received,
Third delayed sequence exports clk_d3 to the 4th delayed sequence；
4th delayed sequence 14 receives the signal of third delayed sequence output, after setting the period to the signal delay received,
4th delayed sequence exports clk_d4 to Edge check alignment circuit 2；When the signal of the second delayed sequence output compares reference clock
During signal delay half period, the signal of the 4th delayed sequence 14 output postpones a cycle than reference clock signal；
Edge check alignment circuit 2 receives the signal of the 4th delayed sequence output, while receives clock generation circuit 5 and export
Reference clock signal clk, and this two signals are subjected to phase bit comparisons, export same delay control parameter to the first delay
Sequence 11, the second delayed sequence 12,13 and the 4th delayed sequence 14 of third delayed sequence；
Reset signal generative circuit 4 receives the signal of the second delayed sequence output, and generation reset signal is output to clock production
Raw circuit 5；When the signal of the second delayed sequence output postpones half period than reference clock signal, the reset signal of generation makes
5 output duty cycle of clock generation circuit is 50% clock signal；Using the reset signal of clk_d2 generations clk, thus adjust
The duty ratio of clk reaches 50%.
Duty ratio corrects circuit 3 and receives the clock signal that clock generation circuit 5 exports, while it is defeated to receive the first delayed sequence
The signal gone out, generation frequency multiplied clock signal output, can prevent output clock jitter.
Referring to Fig. 2, in a particular embodiment, each delayed sequence includes n delay cell and a selector, n take
Positive integer；N delay cell is connected in series with, and each delay cell outputs signals to selector；Selector is by Edge check
The control for the delay control parameter that alignment circuit 2 exports, exports after selecting the signal received；N is true according to circuit precision
Fixed, n values are bigger, and circuit precision is higher.Each delay cell can be in series by 2 reversers.
Referring to Fig. 3 and Fig. 4, to the method that above-mentioned digital frequency multiplication circuit is modified clock duty cycle, include the following steps：
First, judge 14 output signal clk_d4 of the 4th delayed sequence than reference clock signal that clock generation circuit 5 exports
Whether clk delays have been more than a clock cycle, if being not above a clock cycle, using big step-length mode, increase is prolonged
Slow control parameter makes 14 output signal clk_d4 of the 4th delayed sequence be more than a clock week than reference clock signal clk delays
Phase；Even if the rising edge of 14 output signal clk_d4 of the 4th delayed sequence is to reference clock signal clk in next clock cycle
Rising edge quickly approach and be more than；
Two ought detect that 14 output signal clk_d4 of the 4th delayed sequence believes than the reference clock that clock generation circuit 5 exports
Number clk has been delayed over a clock cycle, i.e. the rising edge of 14 output signal clk_d4 of the 4th delayed sequence compares reference clock
Rising edges of the signal clk in next clock cycle is delayed, and by the way of fine tuning, is reduced delay control parameter, is made the 4th to prolong
Slow 14 output signal clk_d4 delay times of sequence reduce, though the rising edge of 14 output signal clk_d4 of the 4th delayed sequence to
Rising edges of the reference clock signal clk in next clock cycle approaches；
3rd, judge whether 14 output signal clk_d4 of the 4th delayed sequence only postpones a week than reference clock signal clk
Phase judges that the rising edge of 14 output signal clk_d4 of the 4th delayed sequence and reference clock signal clk are all in next clock
Whether the rising edge of phase is without phase difference, and due to digital circuit precision, when can't detect for the first time, the 4th delayed sequence 14 is defeated
Go out signal clk_d4 rising edges and reference clock signal clk in the rising edge of next clock cycle there are during phase difference, remember
Record delay parameter, label blind area top；Continue adjustment delay control parameter, make 14 output signal clk_ of the 4th delayed sequence again
The delay time of d4 reduces, even if the rising edge of 14 output signal clk_d4 of the 4th delayed sequence is again to reference clock signal
Clk is close in the rising edge of next clock cycle and crosses；When detecting 14 output signal clk_ of the 4th delayed sequence again
D4 rising edges and reference clock signal clk next clock cycle rising edge there are during edge difference, record delay parameter,
Mark blind area bottom；
Four go out the position of blind area central point, adjustment delay control ginseng according to the mathematic interpolation with blind area bottom at the top of blind area
Number makes the rising edge of the 4th delayed sequence 14 at a time output signal clk_d4 be in this position.
The present invention is on clock edge alignment detection algorithm, using approaching stage by stage, the mode for the valuation that is averaged.First with big
Step-length is by close-target edge and surmounts, secondly fine adjustment delay parameter, reduces delay time to obtain the position on check frequency top, then
It is secondary to continue to reduce parameter, until detecting edge difference, blind area bottom position being obtained at this time, the two is averaged, estimation detection is blind
The center position in area excludes the influence that the check frequency brought due to device precision is aligned edge, Hou Zheshi with this
The major reason that frequency doubling clock is caused to shake.
The operation principle of the present invention as shown in Figures 4 to 6, represents check frequency in dotted line frame, i.e., due to device precision original
Cause, within this range, Edge check alignment circuit 2 can not judge the difference between reference clock and delay output, if finally prolonging
Slow clock edge can not be fallen in central point Z location, then frequency doubling clock necessarily has apparent shake.Therefore it is detected in clock edge
On, using approaching stage by stage, average valuation obtains the algorithm of central point.In the 1. stage, delay parameter is increased with big step-length, makes the
The rising edge of four delayed sequences, 14 output signal clk_d4 is fast in the rising edge of next clock cycle to reference clock signal clk
Speed approaches and is more than, to obtain the effect quickly approached.When Edge check alignment circuit 2 detects that clk_d4 believes than reference clock
Number rising edges of the clk in next clock cycle is delayed, into the 2. stage.Parameter is finely tuned, delay is gradually decreased, is connect to blind area
Closely.When the difference between Edge check alignment circuit 2 can not detect the two clocks, it is blind to represent that clk_d4 comes into
Area then obtains the information at the top of blind area, enters the 3. stage at this time.Continue to finely tune parameter, reduce delay parameter, work as Edge check
When alignment circuit 2 tells the difference between rising edge clock again, represent that clk_d4 steps out blind area, then obtain blind area bottom
Information, into the 4. stage.In 4. stage, the data at blind area both ends are averaged, obtain the position of central point.Last delay
Effect is as shown in the 5. stage, this also indicates that circuit enters lock-out state, and the output of four delayed sequences is 90 ° of delay
Phase.
At this point, it is 180 ° of phases that the second sequence, which exports clk_d2 than clk delays, using this signal as amendment clock signal
The reset signal of clk, as shown in figure 5, the new clock clk_x of 50% duty ratio thus can be obtained.The first delayed sequence is defeated at this time
Go out clk_d1 and 90 ° of phases are just differed with clk_x, the two exclusive or generates frequency doubling clock clk_2x, as shown in Figure 6.
The input reference clock of non-50% duty ratio is present invention can be suitably applied to, automatically adjusts duty ratio, and use centainly
Algorithm optimization phase alignment improves frequency doubling clock precision.It can be applied to totally digital circuit, economization area, the system of reducing are answered
Miscellaneous degree.The technology of the present invention can be applied in RFID label chip and other low-power consumption IC chips.
Claims (3)
1. a kind of method of digital frequency multiplication circuit modifications clock duty cycle, which includes delay circuit (1), edge
Detect alignment circuit (2) and clock generation circuit (5)；
Delay circuit (1) prolongs including the first delayed sequence (11), the second delayed sequence (12), third delayed sequence (13) and the 4th
Slow sequence (14), each delayed sequence is by the control of the same delay control parameter of Edge check alignment circuit (2) output；
It is characterized in that：Include the following steps：
(1), judge the reference clock signal delay of the 4th delayed sequence (14) output signal ratio clock generation circuit (5) output
Whether it has been more than a clock cycle, if being not above a clock cycle, adjustment delay control parameter makes the 4th delay sequence
It arranges the delay of (14) output signal ratio reference clock signal and is more than a clock cycle；
(2) when the reference clock signal for detecting the output of the 4th delayed sequence (14) output signal ratio clock generation circuit (5) prolongs
It has been more than late a clock cycle, adjustment delay control parameter reduced for the 4th delayed sequence (14) output signal delay time,
Even if rising edge of the rising edge of the 4th delayed sequence (14) output signal to reference clock signal in next clock cycle is forced
Closely；
(3), judge the rising edge of the 4th delayed sequence (14) output signal with reference clock signal in next clock cycle
Whether rising edge is believed without phase difference when can't detect the 4th delayed sequence (14) output signal rising edge for the first time with reference clock
Number next clock cycle rising edge there are during phase difference, delay parameter is recorded, at the top of label blind area；Continue adjustment to prolong
Slow control parameter makes the rising edge of the 4th delayed sequence (14) output signal again to reference clock signal in next clock week
The rising edge of phase is close and crosses；When detecting the 4th delayed sequence (14) output signal rising edge and reference clock signal again
There are during phase difference, record delay parameter, label blind area bottom for rising edge in next clock cycle；
(4) going out the position of blind area central point according to the mathematic interpolation with blind area bottom at the top of blind area, adjustment postpones control parameter,
The rising edge of the 4th delayed sequence (14) output signal is made to be in this position of the central point.
2. a kind of method of digital frequency multiplication circuit modifications clock duty cycle according to claim 1, it is characterised in that：Each
Delayed sequence includes n delay cell and a selector, n take positive integer；N delay cell is connected in series with, and is each prolonged
Slow unit outputs signals to selector；Selector is postponed the control of control parameter by Edge check alignment circuit (2) output,
It is exported after selecting the signal received.
3. a kind of method of digital frequency multiplication circuit modifications clock duty cycle according to claim 2, it is characterised in that：Each
Delay cell is in series by 2 reversers.
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110719071B (en) * | 2019-08-20 | 2023-03-21 | 广州润芯信息技术有限公司 | Frequency multiplier circuit with calibration and control method |
| CN110459161B (en) * | 2019-08-23 | 2023-04-07 | 北京集创北方科技股份有限公司 | Receiving device, driving chip, display device and electronic equipment |
| JP2021048523A (en) * | 2019-09-19 | 2021-03-25 | 株式会社東芝 | Led drive control circuit, electronic circuit, and method for controlling led drive |
| CN113364468A (en) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | Serial-to-parallel conversion alignment circuit and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1349683A (en) * | 1999-04-30 | 2002-05-15 | 睦塞德技术公司 | Frequency-multiplying delay locked loop |
| CN101087132A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Adjustment method of clock fifty percent idle percent based on phone mixing |
| US7602166B1 (en) * | 2005-10-12 | 2009-10-13 | National Semiconductor Corporation | System and method for providing a digital self-adjusting power supply that provides a substantially constant minimum supply voltage with regard to variations of PVT, load, and frequency |
| CN103051337A (en) * | 2011-10-17 | 2013-04-17 | 联发科技股份有限公司 | Duty ratio correcting device and related method |
| CN103684437A (en) * | 2013-02-04 | 2014-03-26 | 中国科学院电子学研究所 | A time-delay chain control code self-adaptive rapid delay lock loop |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6750689B2 (en) * | 2001-03-29 | 2004-06-15 | Intel Corporation | Method and apparatus for correcting a clock duty cycle in a clock distribution network |
-
2015
- 2015-12-02 CN CN201510875586.0A patent/CN105406838B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1349683A (en) * | 1999-04-30 | 2002-05-15 | 睦塞德技术公司 | Frequency-multiplying delay locked loop |
| US7602166B1 (en) * | 2005-10-12 | 2009-10-13 | National Semiconductor Corporation | System and method for providing a digital self-adjusting power supply that provides a substantially constant minimum supply voltage with regard to variations of PVT, load, and frequency |
| CN101087132A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Adjustment method of clock fifty percent idle percent based on phone mixing |
| CN103051337A (en) * | 2011-10-17 | 2013-04-17 | 联发科技股份有限公司 | Duty ratio correcting device and related method |
| CN103684437A (en) * | 2013-02-04 | 2014-03-26 | 中国科学院电子学研究所 | A time-delay chain control code self-adaptive rapid delay lock loop |
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