CN111418158A - Clock system, electronic device and processing method - Google Patents

Clock system, electronic device and processing method Download PDF

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Publication number
CN111418158A
CN111418158A CN201780091708.4A CN201780091708A CN111418158A CN 111418158 A CN111418158 A CN 111418158A CN 201780091708 A CN201780091708 A CN 201780091708A CN 111418158 A CN111418158 A CN 111418158A
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China
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module
phase
locked loop
clock signal
pll
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CN201780091708.4A
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CN111418158B (en
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刘敬波
刘俊秀
王雅君
石岭
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Ark Pioneer Microelectronics Shenzhen Co ltd
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Ark Pioneer Microelectronics Shenzhen Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

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Abstract

The invention discloses a clock system (100), and the clock system (100) comprises a reference clock module (110), a phase-locked loop module (120), a phase-locked loop power supply module (130), a phase-locked loop fault monitoring module (140) and a phase-locked loop fault processing module (150). The reference clock module (110) is used for outputting a reference clock signal. The phase-locked loop module (120) is configured to output a process clock signal based on the reference clock signal. The phase-locked loop power module (130) is used for supplying power to the phase-locked loop module (120). The phase-locked loop fault monitoring module (140) is used for determining the working state of the phase-locked loop module (120) according to the power supply voltage and the processing clock signal of the phase-locked loop power supply module (130). The phase-locked loop fault processing module (150) is used for controlling the phase-locked loop module (120) and/or the phase-locked loop power supply module (130) according to the working state of the phase-locked loop module (120) and determining an output clock signal. The invention also discloses a processing method and an electronic device.

Description

Clock system, electronic device and processing method Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a clock system, an electronic apparatus, and a processing method.
Background
In the related art, a clock system using a phase-locked loop is prone to a problem of an abnormal operation when the phase-locked loop malfunctions, particularly a clock system requiring high reliability, such as a military or railway signal control clock system.
Disclosure of Invention
The embodiment of the invention provides a clock system, an electronic device and a processing method.
The present invention provides a clock system comprising:
a reference clock module to output a reference clock signal;
a phase-locked loop module for outputting a processing clock signal according to the reference clock signal;
the phase-locked loop power supply module is used for supplying power to the phase-locked loop module;
the phase-locked loop fault monitoring module is used for determining the working state of the phase-locked loop module according to the power supply voltage of the phase-locked loop power supply module and the processing clock signal; and
the phase-locked loop fault processing module is used for controlling the phase-locked loop module and/or the phase-locked loop power supply module and determining an output clock signal according to the working state of the phase-locked loop module.
The invention provides an electronic device comprising the clock system.
The invention provides a processing method, which is used for a clock system, wherein the clock system comprises a reference clock module, a phase-locked loop power supply module, a phase-locked loop fault monitoring module and a phase-locked loop fault processing module, the phase-locked loop power supply module is used for supplying power for the phase-locked loop module, and the processing method comprises the following steps:
the reference clock module outputs a reference clock signal;
the phase-locked loop module outputs a processing clock signal according to the reference clock signal;
the phase-locked loop fault monitoring module determines the working state of the phase-locked loop module according to the power supply voltage of the phase-locked loop power supply module and the processing clock signal; and
and the phase-locked loop fault processing module controls the phase-locked loop module and/or the phase-locked loop power supply module and determines to output a clock signal according to the working state of the phase-locked loop module.
The clock system, the electronic device and the processing method of the embodiment of the invention monitor the working state of the phase-locked loop module through the phase-locked loop fault monitoring module, control the phase-locked loop module and determine the output clock signal according to the working state of the phase-locked loop module, so that the clock system can work normally when the phase-locked loop module has a fault, and can realize the self-correction of the phase-locked loop module, thereby improving the reliability of the clock system.
Additional aspects and advantages of embodiments of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a block schematic diagram of a clock system of an embodiment of the present invention;
FIG. 2 is a schematic flow diagram of a treatment process according to an embodiment of the invention;
FIG. 3 is another block diagram of a clock system in accordance with an embodiment of the present invention;
FIG. 4 is another schematic flow diagram of a treatment process according to an embodiment of the invention;
FIG. 5 is a schematic diagram of yet another module of the clock system of an embodiment of the present invention;
FIG. 6 is a further schematic flow diagram of a treatment process according to an embodiment of the invention;
FIG. 7 is yet another block diagram of a clock system in accordance with an embodiment of the present invention;
FIG. 8 is yet another schematic flow diagram of a treatment process according to an embodiment of the invention;
FIG. 9 is yet another block diagram of a clock system in accordance with an embodiment of the present invention;
FIG. 10 is yet another schematic flow diagram of a treatment process according to an embodiment of the invention;
FIG. 11 is yet another block diagram of a clock system in accordance with an embodiment of the present invention;
FIG. 12 is yet another schematic flow diagram of a treatment process according to an embodiment of the invention;
FIG. 13 is yet another schematic flow diagram of a treatment process according to an embodiment of the invention;
FIG. 14 is yet another block diagram of a clock system in accordance with an embodiment of the present invention;
FIG. 15 is yet another flow diagram of a treatment method in accordance with an embodiment of the present invention.
Description of the drawings with the main elements symbols:
the clock system 100, the reference clock module 110, the phase-locked loop module 120, the phase detector 122, the filter 124, the voltage-controlled oscillator 126, the frequency divider 128, the phase-locked loop power supply module 130, the phase-locked loop fault monitoring module 140, the analog-to-digital converter 142, the phase-locked loop clock frequency analyzing unit 144, the phase-locked loop clock jitter analyzing unit 146, the phase-locked loop fault processing module 150, and the clock output control unit 152.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless otherwise explicitly stated or limited. Either mechanically or electrically. Either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, a clock system 100 according to an embodiment of the invention includes a reference clock module 110, a Phase-locked loop module (Phase L keyed L oop, P LL) 120, a Phase-locked loop power module 130, a Phase-locked loop fault monitoring module 140, and a Phase-locked loop fault handling module 150, where the reference clock module 110 is configured to output a reference clock signal, the Phase-locked loop module 120 is configured to output a processing clock signal according to the reference clock signal, the Phase-locked loop power module 130 is configured to supply power to the Phase-locked loop module 120, the Phase-locked loop fault monitoring module 140 is configured to determine an operating state of the Phase-locked loop module 120 according to a supply voltage of the Phase-locked loop power module 130 and the processing clock signal, and the Phase-locked loop fault handling module 150 is configured to control the Phase-locked loop module.
Referring to fig. 2, the processing method according to the embodiment of the invention can be applied to a clock system 100. The clock system 100 includes a reference clock module 110, a phase-locked loop module 120, a phase-locked loop power module 130, a phase-locked loop fault monitoring module 140, and a phase-locked loop fault handling module 150. The pll power module 130 is used to supply power to the pll module 120. The processing method comprises the following steps:
step S110: the reference clock module 110 outputs a reference clock signal;
step S120: the pll module 120 outputs a processing clock signal according to the reference clock signal;
step S130: the phase-locked loop fault monitoring module 140 determines the working state of the phase-locked loop module 120 according to the supply voltage of the phase-locked loop power module 130 and the processing clock signal; and
step S140: the pll fault handling module 150 controls the pll module 120 and/or the pll power module 130 and determines the output clock signal according to the operating status of the pll module 120.
The processing method according to the embodiment of the present invention may be implemented by the clock system 100 according to the embodiment of the present invention, wherein step S110 may be implemented by the reference clock module 110, step S120 may be implemented by the phase-locked loop module 120, step S130 may be implemented by the phase-locked loop fault monitoring module 140, and step S140 may be implemented by the phase-locked loop fault processing module 150.
The clock system 100 according to the embodiment of the present invention may be applied to the electronic device according to the embodiment of the present invention, or the electronic device according to the embodiment of the present invention includes the clock system 100 according to the embodiment of the present invention.
The clock system 100, the electronic device and the processing method of the embodiment of the invention monitor the working state of the phase-locked loop module 120 through the phase-locked loop fault monitoring module 140, control the phase-locked loop module 120 and determine the output clock signal according to the working state of the phase-locked loop module 120, so that when the phase-locked loop module 120 has a fault, the clock system 100 can work normally, the self-correction of the phase-locked loop module 120 can be realized, and the reliability of the clock system 100 is improved.
In some embodiments, the reference clock module 110 may include an oscillating circuit such as a crystal oscillator, an RC oscillator, an L C oscillator, and the like.
In some embodiments, the operating state of the phase-locked loop module 120 includes: normal and abnormal, the pll module 120 exception includes: and processing clock signal frequency abnormity, clock signal jitter abnormity and power supply voltage abnormity. In one embodiment, the operating status of the pll module 120 may be represented by a three-bit binary number, for example, 000 represents that the pll module 120 is normal, 001 represents that the clock signal frequency is abnormal, 010 represents that the clock signal jitter is abnormal, 100 represents that the power supply voltage is abnormal, 011 represents that the clock signal frequency is abnormal and the clock signal jitter is abnormal, 101 represents that the clock signal frequency is abnormal and the power supply voltage is abnormal, 110 represents that the clock signal jitter is abnormal and the power supply voltage is abnormal, and 111 represents that the clock signal frequency is abnormal, the clock signal jitter is abnormal and the power supply voltage is abnormal.
In some embodiments, the pll fault monitoring module 140 determines the operating state of the pll module 120 according to the supply voltage of the pll power module 130 and the processing clock signal, which may be understood as that the pll fault monitoring module 140 determines whether the operating state of the pll module 120 includes a supply voltage anomaly according to the supply voltage of the pll power module 130, and that the pll fault monitoring module 140 determines whether the operating state of the pll module 120 includes a processing clock signal frequency anomaly and a processing clock signal jitter anomaly according to the processing clock signal.
In some embodiments, the pll fault handling module 150 controls the pll module 120 and/or the pll power module 130 according to the operating status of the pll module 120, and it is understood that the pll fault handling module 150 controls the pll module 120 according to the operating status of the pll module 120, or the pll fault handling module 150 controls the pll power module 130 according to the operating status of the pll module 120, or the pll fault handling module 150 controls the pll module 120 and the pll power module 130 according to the operating status of the pll module 120. For example, when the operating state of the pll module 120 includes processing clock signal frequency abnormality and/or processing clock signal jitter abnormality, the pll fault handling module 150 may control the pll module 120; the pll fault handling module 150 may control the pll power module 130 when the operating state of the pll module 120 includes a supply voltage anomaly.
In some embodiments, the pll fault handling module 150 includes a Micro Control Unit (MCU) configured to control the reference clock module 110 and the pll module 120, where the MCU stores a configuration register and controls the pll module 120 to output a corresponding processing clock signal according to a frequency multiplier in the configuration register.
In some embodiments, when the power supply voltage of the pll power module 130 is abnormal, the pll power module 120 is in an abnormal operating state, so that the pll power module 130 may send the power supply voltage to the pll fault monitoring module 140, the pll fault monitoring module 140 determines whether the received power supply voltage is abnormal, and when the power supply voltage is abnormal, it is determined that the operating state of the pll power module 120 includes the abnormal power supply voltage. When the power supply voltage of the pll power module 130 is abnormal, the pll fault processing module 150 may change parameters in the pll voltage control register (the pll voltage control register may be located in a micro control unit of the pll fault processing module 150), and control the pll power module 130 according to the parameters in the pll voltage control register so as to recover the power supply voltage output by the pll power module 130 to normal. In one embodiment, if the pll fault monitoring module 140 determines that the supply voltage output by the pll power module 130 is insufficient, the pll fault processing module 150 increases the voltage parameter in the pll voltage control register, so as to control the pll power module 130 to increase the supply voltage according to the increased voltage parameter.
In some embodiments, the reference clock signal is the clock signal output by the reference clock module 110. The processing clock signal is a clock signal output by the pll module 120, and the processing clock signal is generally a frequency multiplication of the reference clock signal, for example, the processing clock signal is a frequency multiplication, and a frequency multiplication of the reference clock signal, where the processing clock signal is approximately the same as the reference clock signal when the processing clock signal is a frequency multiplication of the reference clock signal. The output clock signal is the clock signal that the clock system 100 finally outputs.
Referring to fig. 3, in some embodiments, the pll fault monitoring module 140 includes an Analog-to-Digital Converter (ADC) 142, the ADC 142 is configured to convert the supply voltage into a Digital voltage, and the pll fault monitoring module 140 is configured to compare the Digital voltage with a predetermined voltage to determine an operating state of the pll module 120.
Referring to fig. 4, in some embodiments, the pll fault monitoring module 140 includes an analog-to-digital converter 142, and step S130 includes:
step S132: the analog-to-digital converter 142 converts the supply voltage into a digital voltage;
step S134: the phase-locked loop fault monitoring module 140 compares the digital voltage to a predetermined voltage to determine the operational state of the phase-locked loop module 120.
That is, step S132 may be implemented by the analog-to-digital converter 142, and step S134 may be implemented by the phase-locked loop fault monitoring module 140.
In this way, the analog-to-digital converter 142 can determine whether the power supply voltage is abnormal.
Specifically, since the power supply voltage of the pll power module 130 is generally an analog voltage, in order to determine whether the power supply voltage is abnormal or not, the analog power supply voltage may be first converted into a digital voltage, so as to compare the digital voltage with the predetermined voltage by using the pll fault monitoring module 140, for example, determine whether the digital voltage is within a voltage error range of the predetermined voltage, if the digital voltage is within the voltage error range of the predetermined voltage, it may be determined that the power supply voltage is normal, thereby determining that the operating state of the pll module 120 includes that the power supply voltage is normal, and if the digital voltage is outside the voltage error range of the predetermined voltage, it may be determined that the power supply voltage is abnormal, thereby determining that the operating state of the pll module 120 includes that the.
It should be noted that the predetermined voltage and the voltage error range may be determined according to an actually adopted operating voltage required by the phase-locked loop module 120, or may be determined according to a preset input by an operator, and are not specifically limited herein. In one embodiment, the predetermined voltage is 3V, and the voltage error range is ± 0.1V, that is, when the supply voltage is in the range of 2.9V to 3.1V, the supply voltage is normal, and when the supply voltage is less than 2.9V or greater than 3.1V, the supply voltage is abnormal.
In some embodiments, analog-to-digital converter 142 comprises a successive approximation register type analog-to-digital converter (SAR ADC) that may be employed to reduce power consumption of clock system 100.
Referring to fig. 5, in some embodiments, the pll fault monitoring module 140 includes a pll clock frequency analyzing unit 144, where the pll clock frequency analyzing unit 144 is configured to obtain a frequency of the processing clock signal and determine an operating state of the pll module 120 according to a comparison result between the frequency of the processing clock signal and a predetermined frequency.
Referring to fig. 6, in some embodiments, the pll fault monitoring module 140 includes a pll clock frequency analyzing unit 144, and step S130 includes:
step S136: the phase-locked loop clock frequency analyzing unit 144 acquires the frequency of the processing clock signal and determines the operation state of the phase-locked loop module 120 according to the comparison result of the frequency of the processing clock signal and the predetermined frequency.
That is, step S136 may be implemented by the phase-locked loop clock frequency analyzing unit 144.
In this way, it can be determined whether the frequency of the processing clock signal is abnormal, thereby determining the operating state of the phase-locked loop module 120.
Specifically, the pll clock frequency analyzing unit 144 processes the processing clock signal to obtain a frequency of the processing clock signal, compares the frequency of the processing clock signal with a predetermined frequency, and determines whether the frequency of the processing clock signal is within a frequency error range of the predetermined frequency, when the frequency of the processing clock signal is within the error range of the predetermined frequency, it may be determined that the operating state of the pll module 120 includes that the frequency of the processing clock signal is normal, and if the frequency of the processing clock signal is outside the error range of the predetermined frequency, it may be determined that the operating state of the pll module 120 includes that the frequency of the processing clock signal is abnormal.
It should be noted that the predetermined frequency and the frequency error range may be determined according to an actually required clock frequency, or may be determined according to a preset input by an operator, and are not limited specifically herein. In one embodiment, the predetermined frequency is 200MHz, and the frequency error range is ± 1MHz, that is, when the frequency of the processing clock signal is in the range from 199MHz to 201MHz, the frequency of the processing clock signal is normal, and when the frequency of the processing clock signal is less than 199MHz or greater than 201MHz, the frequency of the processing clock signal is abnormal.
In some embodiments, when the processing clock signal frequency is abnormal, the parameter in the pll frequency control register (the pll frequency control register may be located in a micro-control unit of the pll fault processing module 150) may be changed, and the pll module 120 is controlled according to the parameter in the pll frequency control register to recover the processing clock signal output by the pll module 120. In one embodiment, if the pll clock frequency analyzing unit 144 determines that the frequency of the processing clock signal is higher, the pll fault handling module 150 decreases the frequency parameter in the pll frequency control register, so as to control the pll module 120 to decrease the frequency of the output processing clock signal according to the decreased frequency parameter.
Referring to fig. 7, in some embodiments, the pll fault monitoring module 140 includes a pll clock jitter analyzing unit 146, and the pll clock jitter analyzing unit 146 is configured to receive the reference clock signal and compare the reference clock signal with the processed clock signal to determine an operating state of the pll module 120.
Referring to fig. 8, in some embodiments, the pll fault monitoring module 140 includes a pll clock jitter analyzing unit 146, and step S130 includes:
step S138: the phase locked loop clock jitter analysis unit 146 receives the reference clock signal and compares the reference clock signal to the process clock signal to determine the operational state of the phase locked loop module 120.
That is, step S138 may be implemented by the phase-locked loop clock jitter analyzing unit 146.
In this way, it can be determined whether the processing clock signal has jitter, thereby determining the operating state of the pll module 120.
Specifically, the pll clock jitter analyzing unit 146 compares the reference clock signal with the processing clock signal to determine whether the processing clock signal has jitter, for example, obtains a high level duration of the reference clock signal after a rising edge, obtains a high level duration of the processing clock signal after the same rising edge, determines that the processing clock signal has no jitter when the high level duration of the reference clock signal is consistent with the high level duration of the processing clock signal, determines that the processing clock signal has jitter when the high level duration of the reference clock signal is inconsistent with the high level duration of the processing clock signal, determines that the processing clock signal has jitter, and determines that the operating state of the pll module 120 includes processing clock signal jitter abnormality.
In some embodiments, parameters in the pll voltage control register and/or parameters in the pll frequency control register may be changed to adjust the pll module 120 (parameters in the pll voltage control register and/or parameters in the pll frequency control register, which may be understood as parameters in the pll voltage control register or parameters in the pll frequency control register, or parameters in the pll voltage control register and parameters in the pll frequency control register) when handling clock signal jitter anomalies. In one embodiment, in handling the clock jitter abnormality, the pll power module 130 is controlled to stop supplying power to the pll module 120 by the parameter in the pll voltage control register, and after a predetermined stop time, the pll power module 130 is controlled to supply power to the pll module 120 again. The predetermined stop time may be set according to the actual requirement of the user, and in order to reduce the adverse effect of the pll power supply module 130 stopping supplying power to the pll module 120, the predetermined stop time may be a small value, for example, less than 50 ms.
Referring to fig. 9, in some embodiments, the phase-locked loop module 120 includes a phase detector 122, a filter 124, a voltage-controlled oscillator 126, and a frequency divider 128, where the phase detector 122 is configured to process the reference clock signal and the feedback clock signal to determine a phase difference between the reference clock signal and the feedback clock signal and convert the phase difference into an error voltage, the filter 124 is configured to filter the error voltage, the voltage-controlled oscillator 126 is configured to output a processing clock signal according to the filtered error voltage, and the frequency divider 128 is configured to divide the processing clock signal to obtain the feedback clock signal.
Referring to fig. 10, in some embodiments, the phase-locked loop module 120 includes a phase detector 122, a filter 124, a voltage-controlled oscillator 126 and a frequency divider 128, and step S120 includes:
step S122: the phase detector 122 processes the reference clock signal and the feedback clock signal to determine a phase difference between the reference clock signal and the feedback clock signal and converts the phase difference into an error voltage;
step S124: the filter 124 filters the error voltage;
step S126: the voltage controlled oscillator 126 outputs a processing clock signal based on the filtered error voltage;
step S128: divider 128 divides the processing clock signal to obtain the feedback clock signal.
That is, step S122 may be implemented by the phase detector 122, step S124 may be implemented by the filter 124, step S126 may be implemented by the voltage controlled oscillator 126, and step S128 may be implemented by the frequency divider 128.
As such, the pll module 120 may output the processing clock signal according to the reference clock signal.
In some embodiments, the phase detector 122 includes a charge pump that amplifies the error voltage. The filter may be a low pass filter for filtering a noise portion of the amplified error voltage, thereby obtaining a more accurate error voltage.
Referring to fig. 11, in some embodiments, the number of the pll modules 120 is multiple, the pll modules 120 are configured to output multiple processing clock signals, the pll fault monitoring module 140 is configured to determine an operating status of each pll module 120 according to the supply voltage and the multiple processing clock signals, and the pll fault handling module 150 is configured to control each pll module 120 and/or the pll power module 130 and determine an output clock signal according to the operating status of each pll module 120.
Referring to fig. 12, in some embodiments, the number of the pll modules 120 is multiple, and the step S120 includes:
step S129: the plurality of phase-locked loop modules 120 output a plurality of processing clock signals;
the step S130 includes:
step S139: the phase-locked loop fault monitoring module 140 determines the operating state of each phase-locked loop module 120 based on the supply voltage and the plurality of processing clock signals;
the step S140 includes:
step S144: the pll fault handling module 150 controls each pll module 120 and/or pll power module 130 and determines the output clock signal based on the operating state of each pll module 120.
That is, step S129 may be implemented by the pll module 120, step S139 may be implemented by the pll fault monitoring module 140, and step S144 may be implemented by the pll fault handling module 150.
As such, when the number of pll modules 120 is plural, the pll fault monitoring module 140 may determine the operating state of each pll module 120.
Specifically, to improve the reliability of the operation of the clock system 100, the clock system 100 may include a plurality of phase-locked loop modules 120, the plurality of phase-locked loop modules 120 being configured to output a plurality of processing clock signals. The operating status of each pll module 120 may not be the same, and pll fault monitoring module 140 may determine the operating status of the corresponding pll module 120 based on the supply voltage and each processing clock signal.
In some embodiments, a plurality of pll modules 120 share a pll power module 130, and determining whether the supply voltage of the pll power module 130 is abnormal may determine whether the operating state of each pll module 120 includes a power supply abnormality. In some embodiments, different pll power modules 130 are used for the plurality of pll power modules 120, and whether the operating state of each pll power module 120 includes a power supply abnormality may be determined by determining whether the power supply voltages of the plurality of pll power modules 130 are abnormal, respectively.
Referring to fig. 11, in some embodiments, the pll failure handling module 150 is configured to control at least two pll modules 120 of the pll modules 120 to operate simultaneously.
Referring to fig. 13, in some embodiments, step S140 includes:
step S146: the pll fault handling module 150 controls at least two pll modules 120 of the pll modules 120 to operate simultaneously.
That is, step S146 may be implemented by the phase-locked loop fault handling module 150.
Thus, when the operating status of the pll module 120 is abnormal, another pll module 120 can be switched to in time to ensure that the clock system 100 can operate normally.
Specifically, because the pll module 120 needs to continuously adjust the processing clock signal according to the reference clock signal and the feedback clock signal, the pll module 120 can obtain a stable processing clock signal after a stable time generally, and in order to avoid the influence of the stable time on the normal operation of the clock system 100, the pll fault handling module 150 can control at least two pll modules 120 in the pll modules 120 to operate simultaneously, so that when the operating state of one pll module 120 is abnormal, another pll module 120 that can stably output the processing clock signal can be used to ensure that the clock system 100 can operate normally.
Referring to fig. 14, in some embodiments, the pll failure processing module 150 includes a clock output control unit 152, where the clock output control unit 152 is configured to output a processing clock signal of the pll module 120 corresponding to a predetermined operating state as an output clock signal when at least one pll module 120 corresponding to the predetermined operating state exists, and to output a reference clock signal as the output clock signal when the pll module 120 corresponding to the predetermined operating state does not exist.
Referring to fig. 15, in some embodiments, the pll fault handling module 150 includes a clock output control unit 152, and step S140 includes:
step S148: when there is at least one phase-locked loop module 120 conforming to the predetermined operating state, the clock output control unit 152 outputs a processing clock signal of the phase-locked loop module 120 conforming to the predetermined operating state as an output clock signal; and
step S149: when there is no phase-locked loop module 120 conforming to the predetermined operating state, the clock output control unit 152 outputs the reference clock signal as the output clock signal.
That is, steps S148 and S149 may be implemented by the clock output control unit 152.
In this manner, the clock system 100 may output an appropriate output clock signal through the clock output control unit 152.
Specifically, the predetermined operating state may refer to that the operating state of the pll module 120 is normal, that is, when at least one normal pll module 120 exists, the clock output control unit 152 outputs a processing clock signal of the normal pll module 120 as an output clock signal, and when no normal pll module 120 exists, the clock output control unit 152 outputs a reference signal as an output clock signal.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
In the description of the present specification, reference to the description of the terms "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example", or "some examples", etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
The logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processing module-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (IPM overcurrent protection circuit) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of embodiments of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium. The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (15)

  1. A clock system, comprising:
    a reference clock module to output a reference clock signal;
    a phase-locked loop module for outputting a processing clock signal according to the reference clock signal;
    the phase-locked loop power supply module is used for supplying power to the phase-locked loop module;
    the phase-locked loop fault monitoring module is used for determining the working state of the phase-locked loop module according to the power supply voltage of the phase-locked loop power supply module and the processing clock signal; and
    the phase-locked loop fault processing module is used for controlling the phase-locked loop module and/or the phase-locked loop power supply module and determining an output clock signal according to the working state of the phase-locked loop module.
  2. The clock system of claim 1, wherein the phase-locked loop fault monitoring module includes an analog-to-digital converter for converting the supply voltage to a digital voltage, the phase-locked loop fault monitoring module for comparing the digital voltage to a predetermined voltage to determine an operating state of the phase-locked loop module.
  3. The clock system of claim 1, wherein the phase-locked loop fault monitoring module includes a phase-locked loop clock frequency analysis unit configured to obtain a frequency of the processing clock signal and determine an operating state of the phase-locked loop module based on a comparison of the frequency of the processing clock signal and a predetermined frequency.
  4. The clock system of claim 1, wherein the phase-locked loop fault monitoring module includes a phase-locked loop clock jitter analysis unit for receiving the reference clock signal and comparing the reference clock signal to the process clock signal to determine an operating state of the phase-locked loop module.
  5. The clock system of claim 1, wherein the number of the pll modules is a plurality, a plurality of the pll modules is configured to output a plurality of the processing clock signals, the pll fault monitoring module is configured to determine an operating status of each of the pll modules based on the supply voltage and the plurality of the processing clock signals, and the pll fault handling module is configured to control each of the pll modules and/or the pll power module and determine the output clock signal based on the operating status of each of the pll modules.
  6. The clock system of claim 5, wherein the phase-locked loop fault handling module is configured to control simultaneous operation of at least two of the plurality of phase-locked loop modules.
  7. The clock system according to claim 5, wherein said phase-locked loop fault handling module includes a clock output control unit for outputting said process clock signal of said phase-locked loop module conforming to a predetermined operating state as said output clock signal when at least one of said phase-locked loop modules conforming to said predetermined operating state is present, and for outputting said reference clock signal as said output clock signal when said phase-locked loop module conforming to said predetermined operating state is not present.
  8. An electronic device, characterized in that it comprises a clock system according to any one of claims 1 to 7.
  9. A processing method is used for a clock system, and the clock system comprises a reference clock module, a phase-locked loop power supply module, a phase-locked loop fault monitoring module and a phase-locked loop fault processing module, wherein the phase-locked loop power supply module is used for supplying power for the phase-locked loop module, and the processing method comprises the following steps:
    the reference clock module outputs a reference clock signal;
    the phase-locked loop module outputs a processing clock signal according to the reference clock signal;
    the phase-locked loop fault monitoring module determines the working state of the phase-locked loop module according to the power supply voltage of the phase-locked loop power supply module and the processing clock signal; and
    and the phase-locked loop fault processing module controls the phase-locked loop module and/or the phase-locked loop power supply module and determines to output a clock signal according to the working state of the phase-locked loop module.
  10. The process of claim 9, wherein the phase-locked loop fault monitoring module includes an analog-to-digital converter, the phase-locked loop fault monitoring module determining an operating state of the phase-locked loop module based on a supply voltage of the phase-locked loop power module and the processing clock signal comprises:
    the analog-to-digital converter converts the power supply voltage into a digital voltage;
    the phase-locked loop fault monitoring module compares the digital voltage with a predetermined voltage to determine an operating state of the phase-locked loop module.
  11. The process of claim 9, wherein the pll fault monitoring module comprises a pll clock frequency analysis unit, and wherein the pll fault monitoring module determining the operating state of the pll module based on the supply voltage of the pll power module and the process clock signal comprises:
    and the phase-locked loop clock frequency analysis unit acquires the frequency of the processing clock signal and determines the working state of the phase-locked loop module according to the comparison result of the frequency of the processing clock signal and the preset frequency.
  12. The process of claim 9, wherein the pll fault monitoring module comprises a pll clock jitter analysis unit, and wherein the pll fault monitoring module determining the operating state of the pll module based on the supply voltage of the pll power module and the process clock signal comprises:
    the phase-locked loop clock jitter analyzing unit receives the reference clock signal and compares the reference clock signal with the processing clock signal to determine the working state of the phase-locked loop module.
  13. The processing method of claim 9, wherein the number of the phase-locked loop modules is plural, and the phase-locked loop module outputting the processing clock signal according to the reference clock signal comprises:
    a plurality of said phase locked loop modules outputting a plurality of said processing clock signals;
    the phase-locked loop fault monitoring module determines the working state of the phase-locked loop module according to the power supply voltage of the phase-locked loop power supply module and the processing clock signal, and comprises the following steps:
    the phase-locked loop fault monitoring module determines the working state of each phase-locked loop module according to the power supply voltage and the plurality of processing clock signals;
    the phase-locked loop fault processing module controls the phase-locked loop module and/or the phase-locked loop power supply module according to the working state of the phase-locked loop module and determines to output a clock signal, and the phase-locked loop fault processing module comprises:
    and the phase-locked loop fault processing module controls each phase-locked loop module and/or the phase-locked loop power supply module according to the working state of each phase-locked loop module and determines the output clock signal.
  14. The process of claim 13, wherein the phase-locked loop fault handling module controlling the phase-locked loop module and/or the phase-locked loop power module and determining the output clock signal based on the operational state of the phase-locked loop module comprises:
    the phase-locked loop fault processing module controls at least two phase-locked loop modules in the plurality of phase-locked loop modules to work simultaneously.
  15. The process of claim 13, wherein the pll fault handling module comprises a clock output control unit, and wherein the pll fault handling module controlling the pll module and/or the pll power module and determining the output clock signal based on the operating state of the pll module comprises:
    when at least one phase-locked loop module meeting a preset working state exists, the clock output control unit outputs the processing clock signal of the phase-locked loop module meeting the preset working state as the output clock signal; and
    and when the phase-locked loop module conforming to the preset working state does not exist, the clock output control unit outputs the reference clock signal as the output clock signal.
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