WO2019109356A1 - Clock system, electronic apparatus, and processing method - Google Patents

Abstract

A clock system (100). The clock system (100) comprises a reference clock module (110), a phase-locked loop module (120), a phase-locked loop power source module (130), a phase-locked loop fault detection module (140) and a phase-locked loop fault processing module (150), wherein the reference clock module (110) is used for outputting a reference clock signal; the phase-locked loop module (120) is used for outputting a processing clock signal according to the reference clock signal; the phase-locked loop power source module (130) is used for supplying power to the phase-locked loop module (120); the phase-locked loop fault detection module (140) is used for determining the working state of the phase-locked loop module (120) according to a power supply voltage of the phase-locked loop power source module (130) and the processing clock signal; and the phase-locked loop fault processing module (150) is used for controlling the phase-locked loop module (120) and/or the phase-locked loop power source module (130) according to the working state of the phase-locked loop module (120), and determining an output clock signal. The present invention further relates to a processing method and an electronic apparatus.

Description

Clock system, electronic device, processing method Technical field

The present invention relates to the field of electronic technologies, and in particular, to a clock system, an electronic device, and a processing method.

Background technique

In the related art, a clock system using a phase locked loop is prone to an abnormal operation problem when a phase locked loop fails, particularly a clock system requiring high reliability, such as a military or railway signal control clock system.

Summary of the invention

Embodiments of the present invention provide a clock system, an electronic device, and a processing method.

The invention provides a clock system, comprising:

a reference clock module, the reference clock module is configured to output a reference clock signal;

a phase locked loop module, wherein the phase locked loop module is configured to output a processing clock signal according to the reference clock signal;

a phase-locked loop power module, wherein the phase-locked loop power module is configured to supply power to the phase-locked loop module;

a phase-locked loop fault monitoring module, wherein the phase-locked loop fault monitoring module is configured to determine an operating state of the phase-locked loop module according to a power supply voltage of the phase-locked loop power supply module and the processing clock signal; and

The phase-locked loop fault processing module is configured to control the phase-locked loop module and/or the phase-locked loop power module according to an operating state of the phase-locked loop module and determine an output clock signal.

The present invention provides an electronic device including the clock system.

The present invention provides a processing method for a clock system, the clock system including a reference clock module, a phase locked loop module, a phase locked loop power module, a phase locked loop fault monitoring module, and a phase locked loop fault processing module, the lock The phase loop power module is configured to supply power to the phase locked loop module, and the processing method includes:

The reference clock module outputs a reference clock signal;

The phase locked loop module outputs a processing clock signal according to the reference clock signal;

The phase-locked loop fault monitoring module determines an operating state of the phase-locked loop module according to a power supply voltage of the phase-locked loop power module and the processing clock signal; and

The phase-locked loop fault processing module controls the phase-locked loop module and/or the phase-locked loop power module according to an operating state of the phase-locked loop module and determines an output clock signal.

The clock system, the electronic device and the processing method of the embodiment of the invention monitor the working state of the phase-locked loop module through the phase-locked loop fault monitoring module, control the phase-locked loop module according to the working state of the phase-locked loop module, and determine the output clock signal, thereby When the phase-locked loop module fails, the clock system can work normally, and the self-correction of the phase-locked loop module can be realized, thereby Improve the reliability of the clock system.

The additional aspects and advantages of the embodiments of the present invention will be set forth in part in the description which follows.

DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from

1 is a block diagram of a clock system according to an embodiment of the present invention;

2 is a schematic flow chart of a processing method according to an embodiment of the present invention;

3 is another schematic diagram of a module of a clock system according to an embodiment of the present invention;

4 is another schematic flowchart of a processing method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of still another module of the clock system according to an embodiment of the present invention; FIG.

6 is a schematic flow chart of still another processing method according to an embodiment of the present invention;

7 is another schematic block diagram of a clock system according to an embodiment of the present invention;

FIG. 8 is still another schematic flowchart of a processing method according to an embodiment of the present invention; FIG.

9 is another schematic block diagram of a clock system according to an embodiment of the present invention;

FIG. 10 is still another schematic flowchart of a processing method according to an embodiment of the present invention; FIG.

11 is another schematic block diagram of a clock system according to an embodiment of the present invention;

FIG. 12 is still another schematic flowchart of a processing method according to an embodiment of the present invention; FIG.

FIG. 13 is still another schematic flowchart of a processing method according to an embodiment of the present invention; FIG.

14 is another schematic block diagram of a clock system according to an embodiment of the present invention;

15 is a schematic flow chart of still another processing method of an embodiment of the present invention.

The main component symbol drawing description:

The clock system 100, the reference clock module 110, the phase locked loop module 120, the phase detector 122, the filter 124, the voltage controlled oscillator 126, the frequency divider 128, the phase locked loop power module 130, the phase locked loop fault monitoring module 140, The analog to digital converter 142, the phase locked loop clock frequency analyzing unit 144, the phase locked loop clock jitter analyzing unit 146, the phase locked loop fault processing module 150, and the clock output control unit 152.

Detailed ways

The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientations of "post", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of the description of the present invention and the simplified description, and is not intended to indicate or imply that the device or component referred to has a specific orientation, and is constructed and operated in a specific orientation. Therefore, it should not be construed as limiting the invention. Moreover, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first" or "second" may include one or more of the described features either explicitly or implicitly. In the description of the present invention, the meaning of "a plurality" is two or more unless specifically and specifically defined otherwise.

In the description of the present invention, it should be noted that the terms "installation", "connected", and "connected" are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or connected in one piece. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium, which can be the internal communication of two elements or the interaction of two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

Referring to FIG. 1 , a clock system 100 of an embodiment of the present invention includes a reference clock module 110 , a phase locked loop module (PLL) 120 , a phase locked loop power module 130 , a phase locked loop fault monitoring module 140 , and a phase locked loop . The fault handling module 150. The reference clock module 110 is for outputting a reference clock signal. The phase locked loop module 120 is configured to output a processing clock signal according to the reference clock signal. The phase locked loop power module 130 is used to supply power to the phase locked loop module 120. The phase locked loop fault monitoring module 140 is configured to determine the operating state of the phase locked loop module 120 according to the power supply voltage and the processing clock signal of the phase locked loop power module 130. The phase locked loop fault processing module 150 is configured to control the phase locked loop module 120 and/or the phase locked loop power module 130 according to the working state of the phase locked loop module 120 and determine the output clock signal.

Referring to FIG. 2, a processing method of an embodiment of the present invention may be applied to the clock system 100. The clock system 100 includes a reference clock module 110, a phase locked loop module 120, a phase locked loop power module 130, a phase locked loop fault monitoring module 140, and a phase locked loop fault processing module 150. The phase locked loop power module 130 is used to supply power to the phase locked loop module 120. Processing methods include:

Step S110: The reference clock module 110 outputs a reference clock signal;

Step S120: The phase locked loop module 120 outputs a processing clock signal according to the reference clock signal;

Step S130: The phase-locked loop fault monitoring module 140 determines the working state of the phase-locked loop module 120 according to the power supply voltage and the processing clock signal of the phase-locked loop power module 130; and

Step S140: The phase locked loop fault processing module 150 controls the phase locked loop module 120 and/or the phase locked loop power module 130 according to the working state of the phase locked loop module 120 and determines the output clock signal.

The processing method of the embodiment of the present invention may be implemented by the clock system 100 of the embodiment of the present invention. Step S110 may be implemented by the reference clock module 110, step S120 may be implemented by the phase locked loop module 120, and step S130 may be monitored by the phase locked loop fault. The module 140 is implemented, and the step S140 can be implemented by the phase locked loop fault processing module 150.

The clock system 100 of the embodiment of the present invention can be applied to the electronic device of the embodiment of the present invention, or the electronic device of the embodiment of the present invention includes the clock system 100 of the embodiment of the present invention.

The clock system 100, the electronic device, and the processing method of the embodiment of the present invention monitor the working state of the phase-locked loop module 120 through the phase-locked loop fault monitoring module 140, and control the phase-locked loop module 120 and determine the output according to the working state of the phase-locked loop module 120. The clock signal, so that when the phase locked loop module 120 fails, the clock system 100 can work normally, and the self-correction of the phase locked loop module 120 can be implemented, thereby improving the reliability of the clock system 100.

In some embodiments, the reference clock module 110 can include an oscillator circuit such as a crystal oscillator, an RC oscillator, an LC oscillator, or the like. Electronic devices include mobile phones, tablets, laptops, smart bracelets, smart watches, smart helmets, smart glasses, and the like.

In some embodiments, the operational states of the phase-locked loop module 120 include: normal and abnormal, and the phase-locked loop module 120 anomalies include: processing clock signal frequency anomalies, processing clock signal jitter anomalies, and supply voltage anomalies. In one embodiment, the operating state of the phase locked loop module 120 can be represented by a three-digit binary number, for example, 000 indicates that the phase locked loop module 120 is normal, 001 indicates that the processing clock signal frequency is abnormal, and 010 indicates that the processing clock signal jitter is abnormal, 100. Indicates that the power supply voltage is abnormal, 011 indicates that the processing clock signal frequency is abnormal and the processing clock signal jitter is abnormal, 101 indicates that the processing clock signal frequency is abnormal and the power supply voltage is abnormal, 110 indicates the processing clock signal jitter abnormality and the power supply voltage abnormality, and 111 indicates that the processing clock signal frequency is abnormal. Handle clock signal jitter and power supply voltage abnormality.

In some embodiments, the phase-locked loop fault monitoring module 140 determines the operating state of the phase-locked loop module 120 according to the supply voltage and the processing clock signal of the phase-locked loop power module 130. It can be understood that the phase-locked loop fault monitoring module 140 is The power supply voltage of the phase-locked loop power module 130 determines whether the operating state of the phase-locked loop module 120 includes the power supply voltage abnormality, and the phase-locked loop fault monitoring module 140 determines whether the operating state of the phase-locked loop module 120 includes the processing clock according to the processing clock signal. Abnormal signal frequency and whether the processing clock signal jitter is abnormal.

In some embodiments, the phase-locked loop fault processing module 150 controls the phase-locked loop module 120 and/or the phase-locked loop power module 130 according to the operating state of the phase-locked loop module 120. It can be understood that the phase-locked loop fault processing module 150 The phase-locked loop module 120 is controlled according to the working state of the phase-locked loop module 120, or the phase-locked loop fault processing module 150 controls the phase-locked loop power module 130 according to the working state of the phase-locked loop module 120, or the phase-locked loop fault processing module 150 is The working state of the phase locked loop module 120 controls the phase locked loop module 120 and the phase locked loop power module 130. For example, when the operating state of the phase locked loop module 120 includes abnormality of the processing clock signal frequency and/or abnormality of the processing clock signal, the phase locked loop fault processing module 150 can control the phase locked loop module 120; the operation of the phase locked loop module 120 When the state includes the abnormality of the power supply voltage, the phase locked loop fault processing module 150 can control the phase locked loop power supply module 130.

In some embodiments, the phase locked loop fault processing module 150 includes a micro control unit (MCU) for controlling the reference clock module 110 and the phase locked loop module 120, wherein the micro control unit stores a configuration register, and the micro control The unit controls the phase locked loop module 120 to output a corresponding processing clock signal according to the multiplication frequency in the configuration register.

In some embodiments, when the power supply voltage of the phase-locked loop power module 130 is abnormal, the phase-locked loop module 120 is in an abnormal working state, so the phase-locked loop power module 130 can send the power supply voltage to the phase-locked loop fault monitoring module. 140. The phase-locked loop fault monitoring module 140 determines whether the received power supply voltage is abnormal. When the power supply voltage is abnormal, determining the working state of the phase-locked loop module 120 includes the abnormality of the power supply voltage. The phase locked loop fault processing module 150 can change the parameters in the phase locked loop voltage control register when the power supply voltage of the phase locked loop power supply module 130 is abnormal (the phase locked loop voltage control register can be located in the micro control of the phase locked loop fault processing module 150) In the unit), and controlling the phase-locked loop power module 130 according to the parameters in the phase-locked loop voltage control register to restore the power supply voltage output by the phase-locked loop power module 130 to normal. In one embodiment, the phase-locked loop fault monitoring module 140 determines that the power supply voltage output by the phase-locked loop power module 130 is insufficient, and the phase-locked loop fault processing module 150 increases the voltage value parameter in the phase-locked loop voltage control register, thereby The voltage value parameter after the increase is controlled to control the phase locked loop power supply module 130 to increase the supply voltage.

In some embodiments, the reference clock signal is a clock signal output by reference clock module 110. The processing clock signal is a clock signal output by the phase locked loop module 120, and the processing clock signal is generally a frequency multiplication of the reference clock signal, for example, the processing clock signal is a multiple of the reference clock signal, a double frequency, a triple frequency, etc., wherein the processing When the clock signal is a multiple of the reference clock signal, the processing clock signal is approximately the same as the reference clock signal. The output clock signal is the clock signal that is ultimately output by the clock system 100.

Referring to FIG. 3, in some embodiments, the phase-locked loop fault monitoring module 140 includes an Analog-to-Digital Converter (ADC) 142 for converting a supply voltage to a digital voltage. The phase locked loop fault monitoring module 140 is configured to compare the digital voltage with a predetermined voltage to determine an operating state of the phase locked loop module 120.

Referring to FIG. 4, in some embodiments, the phase locked loop fault monitoring module 140 includes an analog to digital converter 142, and step S130 includes:

Step S132: The analog-to-digital converter 142 converts the power supply voltage into a digital voltage;

Step S134: The phase locked loop fault monitoring module 140 compares the digital voltage with the predetermined voltage to determine the operating state of the phase locked loop module 120.

That is, step S132 can be implemented by analog to digital converter 142, which can be implemented by phase locked loop fault monitoring module 140.

In this manner, it is possible to determine whether the power supply voltage is abnormal by the analog-to-digital converter 142.

Specifically, since the power supply voltage of the phase-locked loop power supply module 130 is generally an analog voltage, in order to conveniently determine whether the power supply voltage is abnormal, the analog power supply voltage may be first converted into a digital voltage, thereby using the phase-locked loop fault monitoring module 140 to compare the digital voltage and The predetermined voltage, for example, determines whether the digital voltage is within a voltage error range of the predetermined voltage. If the digital voltage is within the voltage error range of the predetermined voltage, it may be determined that the power supply voltage is normal, thereby determining the operating state of the phase locked loop module 120 including the normal supply voltage. If the digital voltage is outside the voltage error range of the predetermined voltage, then It is judged that the power supply voltage is abnormal, thereby determining that the operating state of the phase locked loop module 120 includes the abnormality of the power supply voltage.

It should be noted that the predetermined voltage and voltage error ranges may be determined according to the operating voltage required by the phase-locked loop module 120 actually used, or may be determined according to the input of the staff in advance, and are not specifically limited herein. In one embodiment, the predetermined voltage is 3V, and the voltage error range is ±0.1V, that is, when the power supply voltage is in the range of 2.9V-3.1V, the power supply voltage is normal, and when the power supply voltage is less than 2.9V or greater than 3.1V, the power supply voltage is abnormal. .

In some embodiments, the analog to digital converter 142 includes a successive approximation register type analog to digital converter (SAR ADC) that can be used to reduce the power consumption of the clock system 100.

Referring to FIG. 5, in some embodiments, the phase locked loop fault monitoring module 140 includes a phase locked loop clock frequency analyzing unit 144, and the phase locked loop clock frequency analyzing unit 144 is configured to acquire a frequency of the processing clock signal according to the processing clock signal. The comparison of the frequency and the predetermined frequency determines the operational state of the phase locked loop module 120.

Referring to FIG. 6, in some embodiments, the phase-locked loop fault monitoring module 140 includes a phase-locked loop clock frequency analyzing unit 144, and the step S130 includes:

Step S136: The phase locked loop clock frequency analyzing unit 144 acquires the frequency of the processing clock signal and determines the operating state of the phase locked loop module 120 according to the comparison result of the frequency of the processing clock signal and the predetermined frequency.

That is to say, step S136 can be implemented by the phase locked loop clock frequency analyzing unit 144.

In this way, it can be determined whether the frequency of the processing clock signal is abnormal, thereby determining the operating state of the phase locked loop module 120.

Specifically, the phase locked loop clock frequency analyzing unit 144 processes the processing clock signal to obtain the frequency of the processing clock signal, compares the frequency of the processing clock signal with a predetermined frequency, and determines whether the frequency of the processing clock signal is at a frequency error of a predetermined frequency. In the range, when the frequency of the processing clock signal is within the error range of the predetermined frequency, it can be determined that the operating state of the phase locked loop module 120 includes the processing clock signal frequency being normal, and if the frequency of the processing clock signal is outside the error range of the predetermined frequency Then, it can be determined that the operating state of the phase locked loop module 120 includes processing the clock signal frequency abnormality.

It should be noted that the predetermined frequency and the frequency error range may be determined according to the actual required clock frequency, or may be determined according to the input of the staff in advance, and are not specifically limited herein. In one embodiment, the predetermined frequency is 200 MHz, and the frequency error range is ±1 MHz, that is, when the frequency of the processing clock signal is in the range of 199 MHz to 201 MHz, the processing clock signal frequency is normal, and when the frequency of the processing clock signal is less than 199 MHz or greater than 201 MHz, The clock signal processing frequency is abnormal.

In some embodiments, the parameters in the phase locked loop frequency control register can be changed when the frequency of the processing clock signal is abnormal (the phase locked loop frequency control register can be located in the micro control unit of the phase locked loop fault processing module 150), and The phase locked loop module 120 is controlled according to the parameters in the phase locked loop frequency control register to restore the processing clock signal output by the phase locked loop module 120 to normal. In one embodiment, the phase-locked loop clock frequency analysis unit 144 determines that the frequency of the processing clock signal is too high, and the phase-locked loop fault processing module 150 lowers the frequency value parameter in the phase-locked loop frequency control register, thereby The frequency-locked loop module 120 controls the phase-locked loop module 120 to reduce the frequency of the output processing clock signal.

Referring to FIG. 7, in some embodiments, the phase locked loop fault monitoring module 140 includes a phase locked loop clock jitter analysis unit 146 for receiving a reference clock signal and comparing the reference clock signal and processing. The clock signal determines the operational state of the phase locked loop module 120.

Referring to FIG. 8, in some embodiments, the phase-locked loop fault monitoring module 140 includes a phase-locked loop clock jitter analysis unit 146, and the step S130 includes:

Step S138: The phase locked loop clock jitter analysis unit 146 receives the reference clock signal and compares the reference clock signal and the processing clock signal to determine the operating state of the phase locked loop module 120.

That is to say, step S138 can be implemented by the phase locked loop clock jitter analysis unit 146.

In this way, it can be determined whether the processing clock signal has jitter, thereby determining the operating state of the phase locked loop module 120.

Specifically, the phase-locked loop clock jitter analysis unit 146 compares the reference clock signal with the processing clock signal to determine whether the processing clock signal has jitter, for example, after a rising edge, acquires a high-level duration of the reference clock signal, After the same rising edge, the high-level duration of the processing clock signal is obtained. When the high-level duration of the reference clock signal coincides with the high-level duration of the processing clock signal, it is determined that the processing clock signal does not exhibit jitter. The working state of the phase locked loop module 120 includes that the processing clock signal jitter is normal. When the high level duration of the reference clock signal does not coincide with the high level duration of the processing clock signal, it is determined that the processing clock signal is jittery, and the phase locked loop module 120 The working state includes handling clock signal jitter anomalies.

In some embodiments, when processing the clock signal jitter anomaly, the parameters in the phase locked loop voltage control register and/or the parameters in the phase locked loop frequency control register can be changed to adjust the phase locked loop module 120 (phase locked loop voltage) The parameters in the control register and/or the parameters in the phase-locked loop frequency control register can be understood as parameters in the phase-locked loop voltage control register, or in the phase-locked loop frequency control register, or in the phase-locked loop voltage control register. The parameters in the parameters and the parameters in the phase-locked loop frequency control register). In one embodiment, when the processing clock signal jitter is abnormal, the phase-locked loop power module 130 is controlled to stop supplying power to the phase-locked loop module 120 through a parameter in the phase-locked loop voltage control register, and after the predetermined stop time, the phase-locked loop is re-controlled. The ring power module 130 supplies power to the phase locked loop module 120. The predetermined stop time may be set according to the actual needs of the user. To reduce the adverse effect of the phase-locked loop power module 130 stopping the power supply to the phase-locked loop module 120, the predetermined stop time may take a small value, for example, less than 50 milliseconds.

Referring to FIG. 9, in some embodiments, the phase locked loop module 120 includes a phase detector 122, a filter 124, a voltage controlled oscillator 126, and a frequency divider 128 for processing a reference clock signal and feedback. The clock signal determines the phase difference between the reference clock signal and the feedback clock signal and converts the phase difference into an error voltage, the filter 124 is used to filter the error voltage, and the voltage controlled oscillator 126 is configured to output the processing clock according to the filtered error voltage. The signal, frequency divider 128 is used to divide the processed clock signal to obtain a feedback clock signal.

Referring to FIG. 10, in some embodiments, the phase locked loop module 120 includes a phase detector 122, a filter 124, and a voltage Controlling the oscillator 126 and the frequency divider 128, the step S120 includes:

Step S122: the phase detector 122 processes the reference clock signal and the feedback clock signal to determine a phase difference between the reference clock signal and the feedback clock signal and convert the phase difference into an error voltage;

Step S124: The filter 124 filters the error voltage;

Step S126: the voltage controlled oscillator 126 outputs a processing clock signal according to the filtered error voltage;

Step S128: The frequency divider 128 divides the processing clock signal to obtain a feedback clock signal.

That is to say, step S122 can be implemented by phase detector 122, step S124 can be implemented by filter 124, step S126 can be implemented by voltage controlled oscillator 126, and step S128 can be implemented by frequency divider 128.

As such, the phase locked loop module 120 can output a processing clock signal according to the reference clock signal.

In some embodiments, phase detector 122 includes a charge pump for amplifying the error voltage. The filter can be a low pass filter that filters out the noise portion of the amplified error voltage to obtain a more accurate error voltage.

Referring to FIG. 11 , in some embodiments, the number of phase locked loop modules 120 is multiple, and the plurality of phase locked loop modules 120 are configured to output a plurality of processing clock signals, and the phase locked loop fault monitoring module 140 is configured to supply power according to the power supply. The voltage and the plurality of processing clock signals determine an operational state of each phase locked loop module 120, and the phase locked loop fault processing module 150 is configured to control each phase locked loop module 120 and/or according to the operating state of each phase locked loop module 120. The phase locked loop power module 130 and the output clock signal are determined.

Referring to FIG. 12, in some embodiments, the number of phase-locked loop modules 120 is multiple, and step S120 includes:

Step S129: The plurality of phase locked loop modules 120 output a plurality of processing clock signals;

Step S130 includes:

Step S139: The phase locked loop fault monitoring module 140 determines the working state of each phase locked loop module 120 according to the power supply voltage and the plurality of processing clock signals;

Step S140 includes:

Step S144: The phase locked loop fault processing module 150 controls each phase locked loop module 120 and/or the phase locked loop power supply module 130 according to the working state of each phase locked loop module 120 and determines an output clock signal.

That is to say, step S129 can be implemented by the phase locked loop module 120, step S139 can be implemented by the phase locked loop fault monitoring module 140, and step S144 can be implemented by the phase locked loop fault processing module 150.

As such, when the number of phase locked loop modules 120 is multiple, the phase locked loop fault monitoring module 140 can determine the operating state of each phase locked loop module 120.

Specifically, in order to improve the reliability of the operation of the clock system 100, the clock system 100 may include a plurality of phase locked loop modules 120 for outputting a plurality of processing clock signals. The operating state of each phase-locked loop module 120 may be different. The phase-locked loop fault monitoring module 140 may determine the operating state of the corresponding phase-locked loop module 120 according to the power supply voltage and each processing clock signal.

In some embodiments, the plurality of phase-locked loop modules 120 share a phase-locked loop power module 130, and determine whether the power-on voltage of the phase-locked loop power module 130 is abnormal, and whether the working state of each phase-locked loop module 120 is determined. Including power supply anomalies. In some embodiments, the plurality of phase-locked loop modules 120 employ different phase-locked loop power modules 130, and each phase-locked loop module 120 can be determined by determining whether the supply voltages of the plurality of phase-locked loop power modules 130 are abnormal. Whether the working status includes abnormal power supply.

Referring to FIG. 11 , in some embodiments, the phase locked loop fault processing module 150 is configured to control at least two phase locked loop modules 120 of the plurality of phase locked loop modules 120 to operate simultaneously.

Referring to FIG. 13, in some embodiments, step S140 includes:

Step S146: The phase locked loop fault processing module 150 controls at least two phase locked loop modules 120 of the plurality of phase locked loop modules 120 to work simultaneously.

That is to say, step S146 can be implemented by the phase locked loop fault processing module 150.

Thus, when the working state of the phase locked loop module 120 is abnormal, it can be switched to another phase locked loop module 120 in time to ensure that the clock system 100 can work normally.

Specifically, since the phase-locked loop module 120 needs to continuously adjust the processing clock signal according to the reference clock signal and the feedback clock signal, the phase-locked loop module 120 can generally obtain a stable processing clock signal after the stabilization time, in order to avoid the stabilization time for the clock system 100. The normal operation of the phase-locked loop fault processing module 150 can control at least two phase-locked loop modules 120 of the plurality of phase-locked loop modules 120 to work simultaneously, so that when the working state of a phase-locked loop module 120 is abnormal, The clocked loop module 120, which has been able to stably output the processed clock signal, is utilized to ensure that the clock system 100 is functioning properly.

Referring to FIG. 14, in some embodiments, the phase locked loop fault processing module 150 includes a clock output control unit 152 for outputting one when there is at least one phase locked loop module 120 that meets a predetermined working state. The processing clock signal of the phase locked loop module 120 conforming to the predetermined working state is used as an output clock signal, and is used to output a reference clock signal as an output clock signal when there is no phase locked loop module 120 conforming to a predetermined operating state.

Referring to FIG. 15, in some embodiments, the phase locked loop fault processing module 150 includes a clock output control unit 152, and the step S140 includes:

Step S148: when there is at least one phase locked loop module 120 that meets a predetermined working state, the clock output control unit 152 outputs a processing clock signal of the phase locked loop module 120 that meets a predetermined working state as an output clock signal;

Step S149: When there is no phase locked loop module 120 that meets the predetermined working state, the clock output control unit 152 outputs the reference clock signal as an output clock signal.

That is to say, steps S148 and S149 can be implemented by the clock output control unit 152.

As such, the clock system 100 can output a suitable output clock signal through the clock output control unit 152.

Specifically, the predetermined working state may refer to that the working state of the phase locked loop module 120 is normal, that is, when there is at least one normal phase locked loop module 120, the clock output control unit 152 outputs a normal phase locked loop module 120. The clock signal is used as an output clock signal, and when there is no normal phase-locked loop module 120, the clock output control unit 152 outputs a reference signal as an output clock signal.

In the present invention, the first feature "on" or "under" the second feature may include direct contact of the first and second features, and may also include first and second features, unless otherwise specifically defined and defined. It is not in direct contact but through additional features between them. Moreover, the first feature "above", "above" and "above" the second feature includes the first feature directly above and above the second feature, or merely indicating that the first feature level is higher than the second feature. The first feature "below", "below" and "below" the second feature includes the first feature directly below and below the second feature, or merely the first feature level being less than the second feature.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention. In addition, the present invention may be repeated with reference to the numerals and/or reference numerals in the various examples, which are for the purpose of simplicity and clarity, and do not indicate the relationship between the various embodiments and/or arrangements discussed. Moreover, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the use of other processes and/or the use of other materials.

In the description of the present specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples", etc. Particular features, structures, materials or features described in the examples are included in at least one embodiment or example of the invention. In the present specification, the schematic representation of the above terms does not necessarily mean the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

Any process or method description in the flowcharts or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a particular logical function or process. And the scope of the preferred embodiments of the invention includes additional implementations, in which the functions may be performed in a substantially simultaneous manner or in an opposite order depending on the functions involved, in the order shown or discussed. It will be understood by those skilled in the art to which the embodiments of the present invention pertain.

The logic and/or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable instructions for implementing logical functions, and may be embodied in any computer readable medium, Used in conjunction with, or in conjunction with, an instruction execution system, apparatus, or device (eg, a computer-based system, a system including a processing module, or other system that can fetch instructions and execute instructions from an instruction execution system, apparatus, or device) Or use with equipment. For the purposes of this specification, a "computer-readable medium" can be any any program that can contain, store, communicate, propagate, or transport the program for use in an instruction execution system, apparatus, or device, or in conjunction with the instruction execution system, apparatus, or device. Device. More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections (IPM overcurrent protection circuits) with one or more wires, portable computer disk cartridges (magnetic devices), random access memories ( RAM), read only memory (ROM), erasable editable read only memory (EPROM or flash memory), fiber optic devices, and portable compact disk read only memory (CDROM). In addition, the computer readable medium may even be a paper or other suitable medium on which the program can be printed, as it may be optically scanned, for example by paper or other medium, followed by editing, interpretation or, if appropriate, other suitable The method is processed to obtain the program electronically and then stored in computer memory.

It should be understood that portions of the embodiments of the invention may be implemented in hardware, software, firmware or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques well known in the art: having logic gates for implementing logic functions on data signals. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

One of ordinary skill in the art can understand that all or part of the steps carried by the method of implementing the above embodiments can be completed by a program to instruct related hardware, and the program can be stored in a computer readable storage medium. When executed, one or a combination of the steps of the method embodiments is included.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. The integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium. The above mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

Although the embodiments of the present invention have been shown and described, it is understood that the above-described embodiments are illustrative and are not to be construed as limiting the scope of the invention. Implementations are subject to change, modification, substitution, and variation.

Claims (15)

1. A clock system, comprising:

   a reference clock module, the reference clock module is configured to output a reference clock signal;

   a phase locked loop module, wherein the phase locked loop module is configured to output a processing clock signal according to the reference clock signal;

   a phase-locked loop power module, wherein the phase-locked loop power module is configured to supply power to the phase-locked loop module;

   a phase-locked loop fault monitoring module, wherein the phase-locked loop fault monitoring module is configured to determine an operating state of the phase-locked loop module according to a power supply voltage of the phase-locked loop power supply module and the processing clock signal; and

   The phase-locked loop fault processing module is configured to control the phase-locked loop module and/or the phase-locked loop power module according to an operating state of the phase-locked loop module and determine an output clock signal.
2. The clock system of claim 1 wherein said phase locked loop fault monitoring module comprises an analog to digital converter for converting said supply voltage to a digital voltage, said phase locked loop The fault monitoring module is configured to compare the digital voltage and the predetermined voltage to determine an operating state of the phase locked loop module.
3. The clock system according to claim 1, wherein said phase locked loop fault monitoring module comprises a phase locked loop clock frequency analyzing unit, and said phase locked loop clock frequency analyzing unit is configured to obtain a frequency of said processed clock signal And determining an operating state of the phase locked loop module according to a comparison result of the frequency of the processing clock signal and a predetermined frequency.
4. The clock system of claim 1 wherein said phase locked loop fault monitoring module comprises a phase locked loop clock jitter analysis unit, said phase locked loop clock jitter analysis unit for receiving said reference clock signals and comparing The reference clock signal and the processing clock signal determine an operational state of the phase locked loop module.
5. The clock system according to claim 1, wherein the number of the phase locked loop modules is plural, and the plurality of phase locked loop modules are configured to output a plurality of the processing clock signals, the phase locked loop The fault monitoring module is configured to determine an operating state of each of the phase locked loop modules according to the power supply voltage and a plurality of the processing clock signals, where the phase locked loop fault processing module is configured to perform according to each of the phase locked loop modules The operational state controls each of the phase locked loop modules and/or the phase locked loop power supply module and determines the output clock signal.
6. The clock system according to claim 5, wherein said phase locked loop fault processing module is configured to control at least two phase locked loop modules of said plurality of phase locked loop modules to operate simultaneously.
7. A clock system according to claim 5, wherein said phase locked loop fault processing module comprises a clock output control unit for said at least one phase locked loop in accordance with a predetermined operational state And outputting, by the module, the processing clock signal of the phase locked loop module that meets the predetermined working state as the output clock signal, and for not using the phase locked loop module that meets the predetermined working state. The reference clock signal is output as the output clock signal.
8. An electronic device comprising the clock system of any of claims 1-7.
9. A processing method for a clock system, wherein the clock system includes a reference clock module and a lock The phase loop module, the phase locked loop power module, the phase locked loop fault monitoring module, and the phase locked loop fault processing module, the phase locked loop power module is configured to supply power to the phase locked loop module, and the processing method includes:

   The reference clock module outputs a reference clock signal;

   The phase locked loop module outputs a processing clock signal according to the reference clock signal;

   The phase-locked loop fault monitoring module determines an operating state of the phase-locked loop module according to a power supply voltage of the phase-locked loop power module and the processing clock signal; and

   The phase-locked loop fault processing module controls the phase-locked loop module and/or the phase-locked loop power module according to an operating state of the phase-locked loop module and determines an output clock signal.
10. The processing method according to claim 9, wherein the phase-locked loop fault monitoring module comprises an analog-to-digital converter, and the phase-locked loop fault monitoring module is configured according to a supply voltage of the phase-locked loop power module and Processing the clock signal to determine the operating state of the phase locked loop module includes:

    The analog to digital converter converts the supply voltage into a digital voltage;

    The phase locked loop fault monitoring module compares the digital voltage with a predetermined voltage to determine an operating state of the phase locked loop module.
11. The processing method according to claim 9, wherein the phase locked loop fault monitoring module comprises a phase locked loop clock frequency analyzing unit, and the phase locked loop fault monitoring module is configured according to a supply voltage of the phase locked loop power module. And determining, by the processing clock signal, an operating state of the phase locked loop module includes:

    The phase locked loop clock frequency analyzing unit acquires a frequency of the processing clock signal and determines an operating state of the phase locked loop module according to a comparison result of a frequency of the processing clock signal and a predetermined frequency.
12. The processing method according to claim 9, wherein the phase-locked loop fault monitoring module comprises a phase-locked loop clock jitter analysis unit, and the phase-locked loop fault monitoring module is configured according to a supply voltage of the phase-locked loop power module. And determining, by the processing clock signal, an operating state of the phase locked loop module includes:

    The phase locked loop clock jitter analysis unit receives the reference clock signal and compares the reference clock signal and the processed clock signal to determine an operating state of the phase locked loop module.
13. The processing method according to claim 9, wherein the number of the phase-locked loop modules is plural, and the phase-locked loop module outputs a processing clock signal according to the reference clock signal, including:

    a plurality of the phase locked loop modules outputting a plurality of the processing clock signals;

    The phase-locked loop fault monitoring module determines, according to the power supply voltage of the phase-locked loop power module and the processing clock signal, the working state of the phase-locked loop module, including:

    The phase locked loop fault monitoring module determines an operating state of each of the phase locked loop modules according to the power supply voltage and the plurality of processing clock signals;

    The phase locked loop fault processing module controls the phase locked loop module according to an operating state of the phase locked loop module and/or The phase-locked loop power module and the determined output clock signal include:

    The phase locked loop fault processing module controls each of the phase locked loop modules and/or the phase locked loop power supply module according to an operating state of each of the phase locked loop modules and determines the output clock signal.
14. The processing method according to claim 13, wherein the phase-locked loop fault processing module controls the phase-locked loop module and/or the phase-locked loop power module according to an operating state of the phase-locked loop module and Determining the output clock signal includes:

    The phase locked loop fault processing module controls at least two phase locked loop modules of the plurality of phase locked loop modules to work simultaneously.
15. The processing method according to claim 13, wherein the phase locked loop fault processing module comprises a clock output control unit, and the phase locked loop fault processing module controls the lock according to an operating state of the phase locked loop module The phase loop module and/or the phase locked loop power module and the determined output clock signal include:

    The clock output control unit outputs the processing clock signal of the phase locked loop module in accordance with the predetermined operating state as the output clock when there is at least one phase locked loop module that meets a predetermined working state Signal; and

    The clock output control unit outputs the reference clock signal as the output clock signal when there is no phase locked loop module that conforms to the predetermined operating state.

Images