JP2004080357A - Lock discrimination circuit and pll frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lock discrimination circuit that surely prevents dissidence between a discrimination result of the circuit and an operating state when a reference signal is stopped. <P>SOLUTION: The lock discrimination circuit receives a reference signal DX and a phase error signal LOCK between a comparison signal fp and a reference signal fr to perform lock discrimination as to whether or not the phase of the comparison signal is coincident with the phase of the reference signal. A voltage adder 51 receives and monitors the reference signal DX given to the lock discrimination circuit and generates a reference signal detection signal DXA denoting whether or not the reference signal DX is stopped. An output signal of the voltage adder 51 is given to clear terminals of FFs 3,4,5 being components of a lock detection section for detecting whether or not locking is made. When the reference signal detection signal DXA of the voltage adder 51 goes to 'L' (stop of the reference signal DX) in the lock detection section, the FFs 3,4,5 are cleared and provide an output of a 0 level from the output terminals Q. As a result, a lock discrimination output signal LD goes to 'L' (unlock state). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a lock determination circuit and a PLL frequency synthesizer, and more particularly to whether a comparison signal generated from an output signal of a voltage controlled oscillator using an external reference signal and a reference signal generated from the external reference signal have the same phase. And a PLL frequency synthesizer.
[0002]
[Prior art]
2. Description of the Related Art A broadcast receiver such as a television receiver or a video tape recorder (VTR), or a wireless communication device such as a mobile phone has a PLL (Phase-Phase) for obtaining a desired reception frequency or transmission frequency. Locked Loop frequency synthesizers are used. This PLL frequency synthesizer detects whether or not the phase of a reference signal fr generated by dividing the frequency of an external reference signal OSCin, which is an oscillation signal of a predetermined frequency generated by a crystal oscillator or the like, and the comparison signal fp are aligned. A determination circuit is provided. The determination result of the lock determination circuit is output to a control unit such as a microprocessor that controls the entire device, and is used as a criterion for determining whether to start a reception or transmission operation or the like. FIG. 6 is a configuration diagram of a conventional lock determination circuit.
[0003]
The conventional lock determination circuit inputs a phase error signal LOCK between a reference signal fr and a comparison signal fp detected by a preceding-stage phase comparator, and a reference signal DX. The reference signal DX is a signal having the same phase and the same frequency as the reference signal fr. The data flip-flop (hereinafter referred to as FF) 1 inputs the phase error signal LOCK inverted by the inverter 61 to the data input terminal D, latches the output of the inverter 61 at the rise of the reference signal DX, and outputs the latched output. The AND 62 calculates the logical product of the FF1 and the output of the inverter 61. The FF 2 outputs to the FF 3 an inverted output (A) of the level value obtained by latching the output of the AND 62 at the rising edge of the reference signal DX. FF3 inputs the output (A) of FF2, FF4 inputs the output of FF3, and FF5 inputs the output of FF4 to the data input terminal D, latches and outputs the input signal at the rising edge of the inverter 61. The AND 63 calculates the logical product of the output values of the FF3, FF4, and FF5 and outputs the result as a lock determination output signal LD.
[0004]
The operation of the lock determination circuit will be described with a time chart. FIG. 7 is a time chart of the conventional lock determination circuit. (1) shows the case of the lock determination, and (2) shows the case of the unlock determination.
[0005]
The output signal (A) of the FF2 is a signal indicating whether the pulse width of the phase error signal LOCK detected using the reference signal DX as a clock signal is equal to or less than twice the width of the reference signal DX. Since the FF3, FF4, and FF5 sequentially hold data, the output of the AND 63 becomes “3” when the state where the pulse width of the phase error signal LOCK is twice or less the width of the reference signal DX is continued three times or more. H (lock) ". Also, when a phase error occurs, it becomes “L (unlocked)”. Thus, the lock determination circuit changes the lock determination output signal LD based on the reference signal DX generated from the external reference signal OSCin.
[0006]
Here, a reference signal input circuit for inputting the external reference signal OSCin will be described. FIG. 8 is a configuration diagram of a conventional reference signal input circuit. (1) is an example of a circuit including a CMOS + feedback resistor, and (2) is an example of another circuit without a feedback resistor.
[0007]
The reference signal input circuit (1) has a circuit configuration in which a feedback resistor R is connected in parallel to an inverter connected to an input terminal of an external reference signal OSCin via a capacitor, and has been often used in a conventional lock determination circuit. . On the other hand, the reference signal input circuit (2) does not include the feedback resistor R, and a bias voltage is applied between the capacitor and the inverter connected to the input terminal of the external reference signal OSCin via the capacitor. In the circuit configuration of the reference signal input circuit (2), since the external reference signal OSCin can operate stably even with a small amplitude as compared with the reference signal input circuit (1), power consumption can be reduced, and , Has become widely adopted.
[0008]
As described above, the reference signal DX generated based on the external reference signal OSCin input by the reference signal input circuit (1) or (2) is supplied to the lock determination circuit, and the lock determination circuit synchronizes with the reference signal DX. And perform the operation.
[0009]
[Problems to be solved by the invention]
However, the conventional lock determination circuit has a problem that when the external reference signal is stopped in the reference signal input circuit, the lock determination may be "locked" despite the PLL being unlocked.
[0010]
As described above, the determination result by the lock determination circuit is important information for determining the operation of the system. Since the lock determination circuit operates in synchronization with the reference signal DX generated from the external reference signal OSCin, the output value of the lock determination circuit when the external reference signal OSCin is stopped due to a failure of the crystal oscillator or the like is output from the system. Is an important issue. In particular, when the lock determination output signal LD is erroneously fixed to “lock”, a problem such as a malfunction of the system occurs.
[0011]
Since the operation of the lock determination circuit when the external reference signal OSCin stops is different depending on the configuration of the reference signal input circuit, each case of the reference signal input circuits (1) and (2) will be described.
[0012]
First, a reference signal input circuit (1) having a feedback resistor will be described. In the case of the reference signal input circuit (1), even if the external reference signal OSCin is stopped while the lock determination output signal LD is in the locked state, the feedback resistance R exists, so that the external reference signal OSCin, which is the input of the inverter, and the output are output. Oscillation continues at an arbitrary frequency until the level becomes constant. Therefore, the reference signal DX which is a clock signal is input to the lock determination circuit. Since the reference signal DX has a frequency different from that of the normal signal, the lock determination results in the unlock determination.
[0013]
Next, a case of a reference signal input circuit (2) having no feedback resistor, which has been adopted recently, will be described. In the case of the reference signal input circuit (2), the output of the reference signal input circuit stops when the external reference signal OSCin stops. In this case, if the external reference signal OSCin stops while the PLL is locked, the lock determination circuit remains “locked: LD = H” despite the PLL being unlocked.
[0014]
This will be described using respective operation waveforms. FIG. 9 shows operation waveforms when the external reference signal OSCin is stopped. (1) is an operation waveform in “CMOS + feedback resistance” of the reference signal input circuit (1). (2) is an operation waveform in the “other circuit” of the reference signal input circuit (2).
[0015]
In the case of the reference signal input circuit (1), when the external reference signal OSCin stops, the oscillation signal generated by the feedback resistor R operates for a short time from the stop of the external reference signal OSCin as the reference signal DX. Changes from lock (H) to unlock (L). However, although unlocking is determined as a result, the stop of the external reference signal OSCin is not directly monitored, so that unlocking is not determined at the same time as the stop. As described above, since the signal is used by the control unit that controls the device, it is desirable to perform the unlock determination quickly and reliably in order to prevent a malfunction.
[0016]
On the other hand, in the case of the reference signal input circuit (2), when the external reference signal OSCin stops, the reference signal DX, which is a clock signal for lock detection, stops, and the lock determination circuit stops. Therefore, the lock determination output signal LD is fixed at the final value (lock). As a result, since the control unit determines that the locked state has been established and performs processing in spite of the unlocked state, a malfunction of the device may be caused.
[0017]
In order to prevent the lock state from being fixed by stopping the external reference signal, for example, in “Semiconductor Integrated Circuit Device and PLL Frequency Synthesizer” described in Japanese Patent Application Laid-Open No. 10-322199, a lock is performed based on a reference signal fr and a comparison signal fp. When the clock signal of the determination circuit is generated and the reference signal fr generated from the external reference signal stops, the lock determination circuit is operated by setting the comparison signal fp as a reference signal for lock detection. This prevents the circuit from being locked in the locked state.
[0018]
However, in the PLL frequency synthesizer having such a configuration, even if the reference signal fr is stopped, the lock determination circuit operates normally, and as a result, the lock determination circuit is unlocked. For this reason, the same problem as in the case of the reference signal input circuit (1) described above occurs.
[0019]
The present invention has been made in view of such a point, and a lock determination circuit and a lock determination circuit capable of reliably preventing a mismatch between an operation state when an external reference signal is stopped and a determination result of the lock determination circuit. An object of the present invention is to provide a frequency synthesizer including a circuit.
[0020]
[Means for Solving the Problems]
In the present invention, in order to solve the above problem, as shown in FIG. 2, a comparison signal obtained by dividing an output signal of a voltage controlled oscillator to a set frequency and a reference signal obtained by dividing an external reference signal having a predetermined frequency to a reference frequency In a lock determination circuit that determines whether the phase of the comparison signal has locked to the reference signal based on the phase error of the reference signal and the reference signal, the reference signal input to the lock determination circuit is monitored. A reference signal detection unit that generates a predetermined output signal according to whether or not the reference signal is stopped; and locks when the reference signal is stopped based on an output signal of the reference signal detection unit. And a lock detection circuit for setting the determination to unlock.
[0021]
The lock determination circuit having such a configuration provides a phase error signal LOCK between a comparison signal obtained by dividing the output signal of the voltage controlled oscillator to a set frequency and a reference signal obtained by dividing an external reference signal having a predetermined frequency by a reference frequency. Is input, and lock determination is performed using the reference signal DX as a clock signal. The reference signal detection unit, for example, the voltage adder 51 receives and monitors the reference signal DX input to the lock determination circuit, and determines a predetermined reference signal detection signal DXA according to whether the reference signal DX has stopped. Generate The voltage adder 51 serving as the reference signal detection unit outputs, for example, a voltage level “H” when the reference signal DX is normally input, and outputs a voltage level “L” when the reference signal DX is stopped. The output signal of the voltage adder 51 is used as a FF3 (66), an FF4 (67), and an FF5 (68) that constitute a lock detection unit that detects whether or not the in-phase state is a lock state that continues for a certain period of time. ) Clear terminal. The lock detection unit includes FF3 (66), FF4 (67), FF5 (68), and AND 63, and the reference signal detection signal DXA of the voltage adder 51, which is the reference signal detection unit, is “L” ( When the reference signal DX stops), the FF circuit is cleared, and 0 is output from the output terminal Q. As a result, the lock determination output signal LD becomes “L” (unlocked state).
[0022]
Further, a PLL frequency synthesizer including such a lock determination circuit includes a reference signal detection circuit, monitors the reference signal DX in the reference signal detection circuit, and determines whether or not the reference signal DX has stopped. The detection signal DXA is output to the lock determination circuit. The lock determination circuit forcibly outputs an unlock determination when the reference signal detection signal DXA of the reference signal detection circuit is “reference signal stopped”.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a PLL frequency synthesizer according to an embodiment of the present invention.
[0024]
A PLL frequency synthesizer according to the present invention receives an output signal of a voltage controlled oscillator (hereinafter, referred to as a VCO (Voltage Controlled Oscillator)) that generates a signal having a frequency (fin) corresponding to the voltage value of an input control voltage signal. Then, a prescaler 11 for dividing the frequency to a predetermined frequency, a comparison frequency divider 12 for further dividing the oscillation signal divided by the prescaler 11 to a set frequency to generate a comparison signal fp, and a crystal oscillator or the like are generated. A reference signal input circuit 21 for inputting an external reference signal OSCin of a predetermined frequency, and a reference frequency divider for dividing the external reference signal OSCin input to the reference signal input circuit 21 to a reference frequency to generate reference signals fr and DX 22 and a position for generating a phase error signal LOCK by comparing the phases of the comparison signal fp and the reference signal fr. The comparator 30, a charge pump (hereinafter, referred to as C / P) 40 that outputs an output current Do corresponding to the phase error signal detected by the phase comparator 30, and a reference signal DX generated by the reference frequency divider 22. A reference signal detection circuit 50 for generating a reference signal detection signal DXA by monitoring whether or not the reference signal has stopped and a phase error signal LOCK, a reference signal DX and a reference signal detection signal DXA, and a comparison signal fp. And a lock determination circuit 60 which detects whether the phase of the reference signal fr is locked to the phase of the reference signal fr and generates a lock determination output signal LD.
[0025]
The VCO generates an oscillation signal having a frequency fin according to the voltage value of the control voltage signal, and outputs the oscillation signal to the prescaler 11. The high-frequency oscillation signal generated by the VCO is frequency-divided by the prescaler 11 to a predetermined frequency and output to the comparison frequency divider 12. The comparison frequency divider 12 further divides the frequency of the oscillation signal divided by the prescaler 11 to a preset frequency to generate a comparison signal fp. The comparison signal fp is generated from the oscillation signal (frequency fin) generated by the VCO in this manner, and is output to the phase comparator 30.
[0026]
The reference signal input circuit 21 receives an external reference signal OSCin having a natural frequency generated by a crystal oscillator or the like, and outputs the signal to the reference frequency divider 22.
The reference frequency divider 22 divides the external reference signal OSCin input from the reference signal input circuit 21 to a reference frequency to generate a reference signal fr, and outputs the reference signal fr to the phase comparator 30. Further, it generates a similar reference signal DX and outputs it to the lock determination circuit 60 as a clock signal for lock detection.
[0027]
The phase comparator 30 compares the phases of the comparison signal fp and the reference signal fr, and outputs first and second phase error signals based on the comparison result to the C / P 40. Further, it generates a phase error signal LOCK, which is a pulse signal corresponding to the phase difference between the rise of the reference signal fr and the rise of the comparison signal fp, and outputs it to the lock determination circuit 60.
[0028]
The C / P 40 inputs the first and second phase error signals detected by the phase comparator 30, and outputs an output current Do for a time corresponding to these phase error signals. Further, a control voltage signal of the VCO is generated according to the output current Do of the C / P 40, and the output frequency of the VCO is controlled according to the control voltage signal.
[0029]
The reference signal detection circuit 50 receives the reference signal DX generated by the reference frequency divider 22, monitors the reference signal DX, and generates a reference signal detection signal DXA depending on whether or not the reference signal DX has stopped. Output to the lock determination circuit 60. For example, the reference signal detection circuit 50 maintains a predetermined potential as the reference signal detection signal DXA while the reference signal DX is operating (the oscillation signal of the reference frequency is input). The signal detection signal DXA is configured with a circuit that cannot maintain the potential. Such a circuit can be constituted by a voltage adding circuit, a boosting circuit, an integrating circuit, or the like.
[0030]
The lock determination circuit 60 receives the phase error signal LOCK generated by the phase comparator 30, the reference signal DX generated by the reference frequency divider 22, and the reference signal detection signal DXA generated by the reference signal detection circuit 50, and receives the comparison signal fp. Is determined whether or not the phase has locked to the reference signal fr. In the lock determination circuit 60, the reference signal detection signal DXA is monitored. If the reference signal detection signal DXA indicates the input of the reference signal DX, the comparison signal fp is determined based on the reference signal DX and the phase error signal LOCK. It is determined whether or not the phase is locked to the reference signal fr, and a “locked” or “unlocked” lock determination output signal LD is output. When the reference signal detection signal DXA indicates that the reference signal DX has stopped, the lock determination output signal LD is forcibly set to “unlock”.
[0031]
The operation of the PLL frequency synthesizer having such a configuration will be described.
The oscillation signal of the frequency fin generated by the VCO is input to the prescaler 11, is divided into a predetermined frequency, and is further divided by the comparison divider 12 to the set frequency. Thereby, the comparison signal fp of the set frequency is generated from the input signal of the frequency fin, and is output to the phase comparator 30. Further, an external reference signal OSCin based on an oscillation signal of a constant frequency generated by a crystal oscillator or the like is input from a reference signal input circuit 21 and is divided by a reference frequency divider 22 to a reference frequency to generate reference signals fr and DX. You. The reference signal fr of the reference frequency is output to the phase comparator 30, and the reference signal DX is output to the reference signal detection circuit 50 and the lock determination circuit 60.
[0032]
The phase comparator 30 compares the phase of the comparison signal fp based on the output signal of the VCO with the phase of the reference signal fr based on the external reference signal OSCin, and outputs a phase difference detected as a result of the comparison to the C / P 40. Further, it outputs a phase error signal LOCK between the comparison signal fp and the reference signal fr to the lock determination circuit 60.
[0033]
The C / P 40 receives the phase difference and outputs a time output current Do corresponding to the phase difference. Further, a control voltage signal of the VCO is generated according to the output current Do, and the output frequency of the VCO is controlled according to the control voltage signal. As described above, the oscillation signal (frequency fin) generated by the VCO is a closed-loop PLL composed of the phase comparator 30, the C / P 40, the VCO, the prescaler 11, and the comparison frequency divider 12, based on the comparison signal fp and the reference signal fr. Feedback control is performed by the circuit.
[0034]
Further, the reference signal detection circuit 50 monitors the reference signal DX, generates a reference signal detection signal DXA indicating whether or not the reference signal DX is input, and outputs the signal to the lock determination circuit 60. The lock determination circuit 60 monitors the reference signal detection signal DXA, and forcibly sets the lock determination output signal LD to “unlock” when the reference signal detection signal DXA indicates that the reference signal DX has stopped. On the other hand, when the reference signal detection signal DXA indicates the input of the reference signal DX, it is determined whether or not the phase of the comparison signal fp is locked to the reference signal fr based on the reference signal DX and the phase error signal LOCK. And outputs a lock determination output signal LD corresponding to the determination result. The lock determination output signal LD generated in this manner is sent to a control unit such as a microprocessor that controls the system, and is used for determination at the time of operation control such as start and end of processing.
[0035]
In the PLL frequency synthesizer having such a configuration, the reference signal detection circuit 50 for monitoring whether or not the reference signal DX is being input is provided, and the reference signal detection signal DXA is detected by the lock determination circuit 60 in accordance with the detection of the reference signal DX. Output to When the stop of the reference signal DX is detected based on the reference signal detection signal DXA, the lock determination circuit 60 forcibly sets the lock detection output signal to “unlock”. As described above, when the PLL is unlocked due to the stop of the reference signal, it is possible to reliably match the output results of the lock determination circuit 60. As a result, a malfunction or the like of the control unit that refers to the lock determination output signal LD can be reliably prevented.
[0036]
In the above description, the reference signal detection circuit 50 is provided outside the lock determination circuit 60, but may be provided inside the lock determination circuit 60.
Next, the circuit configuration of the lock determination circuit 60 including the reference signal detection circuit 50 will be described. FIG. 2 is a configuration diagram of a lock determination circuit according to an embodiment of the present invention.
[0037]
The lock determination circuit according to the present invention includes a voltage adder 51 that receives a reference signal DX and a phase error signal LOCK as input signals, and changes an output value of a reference signal detection signal DXA according to the presence or absence of the reference signal DX. An inverter 61 that inverts the output of LOCK, an FF1 (64) that latches the output of the inverter 61, an AND 62 that calculates the logical product of the output of the inverter 61 and the FF1 (64), an FF2 (65) that latches the output of the AND 62, and an output of the FF2 FF3 (66) that latches and clears the output according to the reference signal detection signal DXA, FF4 (67) that latches the output of the FF3 and clears the output according to the reference signal detection signal DXA, latches the FF4 output and sets the reference FF5 (68) and FF3 (66) for clearing the output in response to the signal detection signal DXA, F 4 (67) and calculates the logical product of the output signal of FF5 (68), consists of and 63 to generate a lock determination output signal LD.
[0038]
The inverter 61 has an input terminal connected to the phase error signal LOCK output terminal of the phase comparator 30 and an output terminal connected to the input terminals of the FF1 (64) and the AND 62, and generates an inverted signal of the phase error signal LOCK. That is, the period during which the phase error signal LOCK is "H" output is a period during which a phase error occurs.
[0039]
In the FF 1 (64), the data input terminal D is connected to the output terminal of the inverter 61, the clock terminal CLK is connected to the output terminal of the reference signal DX, and the output terminal Q is connected to the input terminal of the AND 62. The FF1 (64) outputs the output value of the inverter 61 latched at the rise of the reference signal DX to the AND 62 and holds the output value for one clock.
[0040]
The AND terminal has an input terminal connected to the output of the inverter 61 and the output of the FF1 (64), and an output terminal connected to the data input terminal D of the FF2 (65). The logical product of the output value of the inverter 61 and the output value of the FF1 (64) is output as an output signal to the FF2 (65).
[0041]
In the FF2 (65), the data input terminal D is connected to the output terminal of the AND 62, the clock terminal CLK is connected to the output terminal of the reference signal DX, and the output terminal XQ is connected to the data input terminal D of the FF3 (66). The FF2 (65) inverts the output value of the inverter 61 latched at the rise of the reference signal DX, outputs the inverted value to the FF3 (66) as an inverted signal (A), and holds the same for one clock.
[0042]
In the FF3 (66), the data input terminal D is connected to the output terminal of the FF2 (65), the clock terminal CLK is connected to the output terminal of the inverter 61, the clear terminal CLR is connected to the output terminal of the reference signal detection signal DXA, and the output terminal Q Is connected to the data input terminal D of the FF 4 (67) and the input terminal of the AND 63. The FF3 (66) outputs the output signal (A) of the FF2 (65) latched at the rising edge of the inverted signal of the phase error signal LOCK to the FF4 (67) and holds the output signal for one clock. When the input signal to the clear terminal CLR becomes 0, the output signal is cleared to 0.
[0043]
In the FF4 (67), the data input terminal D is connected to the output terminal of the FF3 (66), the clock terminal CLK is connected to the output terminal of the inverter 61, the clear terminal CLR is connected to the output terminal of the reference signal detection signal DXA, and the output terminal Q Are connected to the data input terminal D of the FF5 (68) and the input terminal of the AND 63. The FF 4 (67) outputs the output signal of the FF 3 (66) latched at the rising edge of the inverted signal of the phase error signal LOCK to the FF 5 (68) and holds the output signal for one clock. The FF 4 (67) latches the output signal one clock before the FF 3 (66) (clock generated by the output signal of the inverter 61). When the input signal to the clear terminal CLR becomes 0, the output signal is cleared to 0.
[0044]
In the FF5 (68), the data input terminal D is connected to the output terminal Q of the FF4 (67), the clock terminal CLK is connected to the output terminal of the inverter 61, and the clear terminal CLR is connected to the output terminal of the reference signal detection signal DXA. Q is connected to the input terminal of AND63. The FF5 (68) outputs the output signal of the FF4 (67) latched at the rising edge of the inverted signal of the phase error signal LOCK to the AND 63 and holds it for one clock. The FF4 (67) latches the output signal two clocks before the FF3 (66). When the input signal to the clear terminal CLR becomes 0, the output signal is cleared to 0.
[0045]
The AND 63 receives the output signals of the FF3 (66), FF4 (67), and FF5 (68), and outputs the logical product as a lock determination output signal LD. When the output signals of FF3 (66), FF4 (67), and FF5 (68) all become 1, that is, the state where the pulse width of the phase error signal LOCK is twice or less the width of the reference signal DX three times. When the above is continuously maintained, the lock determination output signal LD becomes “locked” and LD = "1". When this state is not maintained, and when the output signals of FF3 (66), FF4 (67) and FF5 (68) are cleared by stopping the reference signal, the lock determination output signal LD becomes LD = "0". ".
[0046]
The operation of the lock determination circuit having such a configuration will be described.
The phase error signal LOCK input to the lock determination circuit is a pulse width signal corresponding to the rising phase error between the reference signal fr and the comparison signal fp generated by the phase comparator 30. On the other hand, the reference signal DX is the same clock signal as the reference signal fr generated by the reference frequency divider 22, and is the reference signal detection signal DXA generated by the reference signal detection circuit 50.
[0047]
The inverter 61 is an inverted output of the phase error signal LOCK, and indicates that the larger the pulse width, the larger the phase error between the comparison signal fp and the reference signal fr. The FF 1 (64) latches the inverted signal of the phase error signal LOCK, which is the output signal of the inverter 61, at the rising edge of the reference signal DX, and outputs the level of the latched signal to the AND 62. In the AND 62, the logical product of the output signal of the inverter 61 and the output signal of the FF1 (64) is obtained and output to the FF2 (65). The FF2 (65) latches the output signal of the AND 62 at the rising edge of the reference signal DX, and outputs an inverted signal of the latched signal to the FF3 (66) as the output signal (A). The output signal (A) indicates whether the pulse width of the phase error signal LOCK is less than twice the width of the reference signal DX, and in the case where the pulse width of the phase error signal LOCK is less than twice the reference signal DX. Is "1", otherwise "0" is output.
[0048]
The FF3 (66) latches the output signal (A) of the FF2 (65) in synchronization with the rising edge of the inverter 61, that is, the falling edge of the phase error signal LOCK, and changes the level of the latched signal to FF4 (67) and AND. 63. As a result, if the period during which the phase error occurs is two or more rising edges of the reference signal DX, “0” is output, and if not, “1” is output. If the reference signal detection signal DXA input from the clear terminal CLR is “0”, the output signal is cleared. Similarly, the FF 4 (67) latches the output signal of the FF 3 (66) in synchronization with the rising edge of the inverter 61, and outputs the level of the latched signal to the FF 5 (68) and the AND 63. As a result, if the period during which the phase error occurs in the previous clock is at least two rising edges of the reference signal DX, “0” is output, and if not, “1” is output. If the reference signal detection signal DXA input from the clear terminal CLR is “0”, the output signal is cleared. Similarly, the FF 5 (68) latches the output signal of the FF 4 (67) in synchronization with the rising edge of the inverter 61 and outputs the latched signal to the AND 63. As a result, when a period during which a phase error occurs in the clock of the last two cycles is two or more rising edges of the reference signal DX, “0” is output, and when not, “1” is output. If the reference signal detection signal DXA input from the clear terminal CLR is “0”, the output signal is cleared.
[0049]
The AND 63 receives the output signals of the FF3 (66), FF4 (67), and FF5 (68), and outputs the logical product of them as a lock determination output signal LD. As a result, if the reference signal detection signal DXA is “0” (reference signal is stopped), it is determined to be “unlocked” and LD = “L” is output. If the reference signal detection signal DXA is "1" (reference signal is normal) and the state in which the pulse width of the phase error signal LOCK is not more than twice as large as the reference signal DX is continuously maintained at least three times, it is determined as "lock". When LD = “H” and the width of the phase error signal LOCK is equal to or larger than the signal pulse width of DX, it is determined to be “unlocked” and LD = “L” is output.
[0050]
This operation will be described with reference to a time chart. FIG. 3 is a time chart of the lock determination circuit according to one embodiment of the present invention.
When the output signal (OUT) of the reference signal input circuit is normal, the reference signal DX is normally generated based on this signal, and the output (DXA) of the voltage adder 51 also has a predetermined potential indicating normal "1". Will be maintained. Accordingly, the lock determination circuit 60 determines whether or not the phase of the comparison signal fp and the phase of the reference signal fr match, and outputs a lock determination output signal LD. When the output signal (OUT) of the reference signal input circuit stops for some reason, the reference signal DX also stops. In the voltage adder 51, since the reference signal DX stops, the potential of the reference signal detection signal DXA cannot be maintained, and the output value changes to “0” indicating the stop of the reference signal. In the lock determination circuit 60, the output of the FF3 (66), the FF4 (67) and the FF5 (68) becomes “0” because the reference signal detection signal DXA falls to “0”, and the output signal of the AND 63 Is also "0".
[0051]
As described above, according to the lock determination circuit of the present invention, when the reference signal stops, the lock determination can be immediately unlocked.
Next, a circuit configuration using a voltage adder, which is an embodiment of the reference signal detection circuit, will be described.
[0052]
First, the case where the circuit is configured most simply will be described. FIG. 4 is a circuit diagram of a passive voltage adder in a PLL frequency synthesizer according to an embodiment of the present invention.
[0053]
The passive type voltage adder is a voltage adder including only passive elements, and includes a resistor R1 connected to an input terminal for inputting a reference signal DX, an output terminal for outputting a reference signal detection signal, and a resistor R1. A capacitor C1 is connected between the output terminal and the ground, and a resistor R2 is connected between the resistor R1 and the output terminal and the ground like the capacitor C1. The voltage adder having such a configuration operates as a filter. If the capacitance of the capacitor C1 and the resistance values of the resistors R1 and R2 are appropriately selected with respect to the frequency of the reference signal DX, the reference signal DX is input. During this time, the voltage level of the reference signal detection signal DXA can be maintained at a predetermined potential or higher.
[0054]
Second, a description will be given of a circuit configuration in which the output value of the reference signal detection signal DXA, which is an output signal, is set to a predetermined level. FIG. 5 is a circuit diagram of an active voltage adder in a PLL frequency synthesizer according to an embodiment of the present invention.
[0055]
The active type voltage adder is a voltage adder including active elements. An operational amplifier (OP-amp) is provided between an input terminal for inputting a reference signal DX and an output terminal for outputting a reference signal detection signal. Is provided. The input terminal of the reference signal DX is connected to the inverting input terminal of OP-amp via the resistor R1, and the power supply is connected to the non-inverting input terminal. Further, a capacitor C1 and a resistor R2 are provided in parallel with the OP-amp. The voltage adder having such a configuration operates as an integrating circuit, and the transfer characteristics of the circuit have characteristics similar to those of the above-mentioned passive type voltage adder. That is, while the reference signal DX is being input, the voltage level of the reference signal detection signal DXA can be maintained at a predetermined potential or higher. However, the passive type voltage adder cannot amplify, but the active type voltage adder can amplify.
[0056]
As described above, the reference signal detection circuit can be realized by a relatively simple circuit configuration as described above. By using the presence / absence of the reference signal detected by the reference signal detection circuit for the lock determination, “unlock” can be quickly and reliably transmitted to the control unit. As a result, it is possible to reliably prevent a malfunction caused by a mismatch between the lock determination and the actual state.
[0057]
【The invention's effect】
As described above, the lock determination circuit and the PLL frequency synthesizer of the present invention monitor whether or not the reference signal generated from the external reference signal has stopped, and immediately determine the lock when the stop of the reference signal is detected. Unlock the output signal. Thus, when the PLL is unlocked due to the stop of the reference signal, it is possible to reliably match the output results of the lock determination circuit. As a result, even if the lock determination output signal is used as the system control signal, no inconvenience such as malfunction occurs.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a PLL frequency synthesizer according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a lock determination circuit according to an embodiment of the present invention.
FIG. 3 is a time chart of a lock determination circuit according to an embodiment of the present invention.
FIG. 4 is a circuit diagram of a passive voltage adder in the PLL frequency synthesizer according to one embodiment of the present invention;
FIG. 5 is a circuit diagram of an active voltage adder in the PLL frequency synthesizer according to one embodiment of the present invention.
FIG. 6 is a configuration diagram of a conventional lock determination circuit.
FIG. 7 is a time chart of a conventional lock determination circuit.
FIG. 8 is a configuration diagram of a conventional reference signal input circuit.
FIG. 9 shows an operation waveform when the external reference signal OSCin is stopped.
[Explanation of symbols]
11 Prescaler
12 Comparison divider
21 Reference signal input circuit
22 Reference frequency divider
30 phase comparator
40 charge pump (C / P)
50 Reference signal detection circuit
60 Lock judgment circuit

Claims (5)

A phase error between a comparison signal obtained by dividing the output signal of the voltage controlled oscillator to a set frequency and a reference signal obtained by dividing an external reference signal having a predetermined frequency by a reference frequency, and a phase of the comparison signal based on the reference signal In a lock determination circuit that determines whether or not is locked to the reference signal,
A reference signal detection unit that monitors the reference signal input to the lock determination circuit and generates a predetermined output signal depending on whether or not the reference signal has stopped;
A lock detection unit that sets a lock determination to unlock when detecting that the reference signal has stopped based on an output signal of the reference signal detection unit,
A lock determination circuit comprising: 2. The reference signal detection unit, comprising: a voltage adder that receives the reference signal and holds a predetermined voltage level as the output signal while the reference signal is being input. 3. The lock determination circuit described in the above. 3. The lock determination circuit according to claim 2, wherein the reference signal detection unit is configured by a passive voltage adder using only passive elements. 3. The lock determination circuit according to claim 2, wherein the reference signal detection unit is configured by an active type voltage adder using an active element. A comparison signal obtained by dividing the output signal of the voltage controlled oscillator that outputs a frequency signal according to the voltage value of the input control voltage signal to a set frequency, and a reference signal obtained by dividing an external reference signal having a predetermined frequency by a reference frequency. A lock determination circuit that determines whether or not the phase of the comparison signal is locked to the reference signal based on the phase error of the control voltage signal according to a result of the lock determination circuit. In a PLL frequency synthesizer that controls
A reference signal detection circuit that monitors the reference signal generated by a reference frequency divider that divides the external reference signal to a reference frequency, and generates a predetermined output signal depending on whether the reference signal has stopped. ,
The reference signal is input as a clock signal to determine whether the phase of the comparison signal is locked to the reference signal and to detect that the reference signal has stopped based on the output signal of the reference signal detection circuit. A lock determination circuit that forcibly sets the lock determination to unlock when the
A PLL frequency synthesizer comprising:

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