TWI523433B - Input signal voltage detection module and method, and related data transmission system - Google Patents

Description

Input signal voltage detection module and method and related data transmission system

The present invention relates to an input signal voltage detecting module and method and related data transmission system, and particularly to an input signal voltage detecting module and method and related data transmission system capable of detecting whether an abnormality of a data signal is abnormal .

The phase-locked loop (PLL) circuit has functions such as phase synchronization and frequency lock, and has been widely used in data transmission systems and wireless communication and other related fields. Please refer to FIG. 1 , which is a schematic diagram of a conventional phase locked loop circuit 10 . The phase locked loop circuit 10 includes a phase frequency detector 110, a charge pump 120, a voltage-controlled oscillator 130, and a frequency divider 140. The phase frequency detector 110 compares the frequency and phase of the data signal F _IN and the feedback signal F _B to produce a comparison result. The charge pump 120 is configured to convert the comparison result generated by the phase frequency detector 110 into an input signal voltage V _IN . The voltage controlled oscillator 130 is configured to convert the input signal voltage V _IN into a frequency output signal F _OUT having a corresponding oscillation frequency. The frequency divider 140 reduces the frequency of the frequency output signal F _OUT to generate a feedback signal F _B . Further, between the charge pump 120 and a voltage controlled oscillator circuit 130 can further include a filter (not shown) for the high frequency component of the input signal voltage V _IN is removed, the input signal voltage V _IN a smoother . However, the phase-locked loop circuit 10 may not be able to lock the frequency output signal F _OUT to the correct frequency due to external factors, resulting in a system abnormality. If the system abnormality cannot be detected immediately, the system performance will be seriously affected. influences.

The object of the present invention is to provide a detection mechanism for instantly detecting an input signal voltage to determine whether a frequency output signal is locked at a correct frequency. If the frequency output signal is not locked at the correct frequency, the system is judged to be abnormal, and the corresponding processing can be performed immediately, thereby improving the system performance.

According to the above object of the present invention, an input signal voltage detecting module is proposed. The input signal voltage detecting module is suitable for detecting an input signal voltage, and includes a comparison voltage generating unit, a comparing unit and a control unit. The comparison voltage generating unit is configured to generate an output signal voltage, a first comparison voltage, and a second comparison voltage according to the input signal voltage. The comparing unit is configured to generate a first comparison result and a second comparison result according to the output signal voltage, the first comparison voltage, the second comparison voltage, and the first clock signal. The control unit is configured to generate a control signal according to the first comparison result and the second comparison result.

According to an embodiment of the invention, the comparison voltage generating unit includes an operational amplifier, a transistor, a first resistor, and a second resistor. The operational amplifier has a positive phase input, a negative phase input, and an output. The positive phase input of the operational amplifier receives the output signal voltage, and the negative phase input of the operational amplifier receives the input voltage signal. The transistor has a source, a gate and a drain. The source of the transistor is electrically connected to the voltage source, and the gate of the transistor is electrically connected Out. The first resistor has a first end and a second end. The first end of the first resistor is electrically connected to the source of the transistor and is used to provide a first comparison voltage, and the second end of the first resistor is used to provide an output signal voltage. The second end of the first resistor. The second resistor has a first end and a second end. The first end of the second resistor is electrically connected to the second end of the first resistor and is configured to provide an output signal voltage, and the second end of the second resistor is configured to provide a second comparison voltage.

According to still another embodiment of the present invention, the comparison unit includes a high voltage comparison unit and a low voltage comparison unit. The high voltage comparison unit is configured to generate a first comparison result according to the output signal voltage, the first comparison voltage, and the first clock signal. The high voltage comparison unit includes a first switch, a first capacitor, and a first comparator. The first switch is electrically connected to the first end of the first resistor for switching to an on or off state according to the first clock signal. The first capacitor is electrically connected between the first switch and the ground. The first comparator has a positive phase input terminal, a negative phase input terminal, and an output terminal. The non-inverting input end of the first comparator is electrically connected to the second end of the first resistor, the negative phase input end of the first comparator is electrically connected to the first capacitor, and the output end of the first comparator is used to output the first comparison result. The low voltage comparison unit is configured to generate a second comparison result according to the output signal voltage, the second comparison voltage, and the first clock signal. The low voltage comparison unit includes a second switch, a second capacitor, and a second comparator. The second switch is electrically connected to the second end of the second resistor for switching to an on or off state according to the first clock signal. The second capacitor is electrically connected between the second switch and the ground. The second comparator has a positive phase input terminal, a negative phase input terminal, and an output terminal. The non-inverting input end of the second comparator is electrically connected to the first end of the second resistor, the negative phase input end of the second comparator is electrically connected to the second capacitor, and the output end of the second comparator is used To output a second comparison result.

According to still another embodiment of the present invention, the comparison unit includes a high voltage comparison unit and a low voltage comparison unit. The high voltage comparison unit is configured to generate a first comparison result according to the output signal voltage, the first comparison voltage, the common input voltage, the first clock signal, and the second clock signal. The high voltage comparison unit includes a first switch, a second switch, a first capacitor, a third switch, and a first comparator. The first switch is electrically connected to the first end of the first resistor. The first switch is configured to switch to an on or off state according to the first clock signal. The second switch is electrically connected to the second end of the first resistor and the first switch. The second switch is configured to switch to an on or off state according to the second clock signal. The first capacitor is electrically connected to the first switch and the second switch. The third switch is electrically connected to the first capacitor and the common input voltage. The third switch is configured to switch to an on or off state according to the first clock signal. The first comparator has a positive phase input terminal, a negative phase input terminal, and an output terminal. The non-inverting input terminal of the first comparator is electrically connected to the common input voltage, the negative phase input end of the first comparator is electrically connected to the first capacitor and the third switch, and the output end of the first comparator is used to output the first comparison result. The low voltage comparison unit is configured to generate a second comparison result according to the output signal voltage, the second comparison voltage, the common input voltage, the first clock signal, and the second clock signal. The low voltage comparison unit includes a fourth switch, a fifth switch, a second capacitor, a sixth switch, and a second comparator. The fourth switch is electrically connected to the second end of the second resistor. The fourth switch is configured to switch to an on or off state according to the first clock signal. The fifth switch is electrically connected to the first end of the second resistor and the fourth switch. The fifth switch is configured to switch to an on or off state according to the second clock signal. The second capacitor is electrically connected to the fourth switch and the fifth switch. The sixth switch is electrically connected The second capacitor and the common input voltage. The sixth switch is configured to switch to an on or off state according to the first clock signal. The second comparator has a positive phase input terminal, a negative phase input terminal, and an output terminal. The non-inverting input terminal of the second comparator is electrically connected to the common input voltage, the negative phase input end of the second comparator is electrically connected to the second capacitor and the sixth switch, and the output end of the second comparator is used to output the second comparison result.

According to still another embodiment of the present invention, the first clock signal and the second clock signal are mutually inverted.

According to still another embodiment of the present invention, the comparison voltage generating unit further includes a variable resistance unit electrically connected between the second end of the second resistor and the ground.

According to the above object of the present invention, a data transmission system is further proposed. This data transmission system consists of a transmitter and a receiver. The mode of operation of the transmitter includes a training mode and a normal mode. When the operating mode of the transmitter is in the normal mode, the transmitter transmits the data signal. The receiver is configured to receive the data signal and includes an input signal voltage detecting module. The input signal voltage detection module includes a comparison voltage generation unit, a comparison unit, and a control unit. The comparison voltage generating unit is configured to generate an output signal voltage, a first comparison voltage, and a second comparison voltage according to the input signal voltage. The comparing unit is configured to generate a first comparison result and a second comparison result according to the output signal voltage, the first comparison voltage, the second comparison voltage, and the first clock signal. The control unit is configured to generate a control signal according to the first comparison result and the second comparison result, where the control signal is used to switch the operation mode of the transmitter.

According to an embodiment of the invention, if the output signal voltage is higher than the first When the comparison voltage or the output signal voltage is lower than the second comparison voltage, the control signal instructs the transmitter to switch to the training mode and transmit a clock recovery pattern signal.

According to the above object of the present invention, an input signal voltage detecting method is further proposed. This input signal voltage detection method is suitable for data transmission systems. This data transmission system consists of a transmitter and a receiver. The operating mode of the transmitter includes a training mode and a normal mode. When the operating mode of the transmitter is in the normal mode, the transmitter transmits the data signal. The receiver is used to receive data signals. The input signal voltage detecting method includes input signal voltage of the sampled data signal to generate an output signal voltage, a first comparison voltage, and a second comparison voltage; and comparing the output signal voltage with the first comparison voltage according to the clock signal to generate the first a comparison result; comparing the output signal voltage with the second comparison voltage according to the clock signal to generate a second comparison result; and generating a control signal according to the first comparison result and the second comparison result, the control signal is used to switch the transmitter Operating mode.

According to an embodiment of the invention, if the output signal voltage is higher than the first comparison voltage or the output signal voltage is lower than the second comparison voltage, the control signal indicates that the transmitter switches to the training mode and transmits the clock recovery type signal.

10, 222‧‧‧ phase-locked loop circuit

110‧‧‧ phase frequency detector

120‧‧‧Charge pump

130‧‧‧Voltage Controlled Oscillator

140‧‧‧Delephone

200‧‧‧Data Transmission System

210‧‧‧transmitter

220‧‧‧ Receiver

224, 300, 400, 500‧‧‧ input signal voltage detection module

310, 410, 510‧‧‧Comparative voltage generating unit

320, 420, 520‧‧‧ comparison unit

330, 430, 530‧‧‧ control unit

421, 521‧‧‧ high voltage comparison unit

422, 522‧‧‧ low voltage comparison unit

700‧‧‧ method

702, 704, 706, 708‧ ‧ steps

C, C1, C2‧‧‧ capacitor

CKS, ‧‧‧clock signal

CP1, CP2‧‧‧ comparator

CR1, CR2‧‧‧ comparison results

CTRL‧‧‧ control signal

F _B ‧‧‧ feedback signal

F _IN ‧‧‧ frequency input signal

F _OUT ‧‧‧ frequency output signal

GND‧‧‧ ground terminal

OP‧‧‧Power Amplifier

R1, R2, R3‧‧‧ resistance

RV‧‧‧Variable Resistor Unit

SW1, SW2, SW3, SW4, SW5, SW6‧‧‧ switch

V _C1 , V _C2 ‧‧‧ comparison voltage

V _CMI ‧‧‧ Common input voltage

V _IN ‧‧‧ input signal voltage

V _OUT ‧‧‧Output signal voltage

V _X1 , V _X2 ‧‧‧ voltage

VDD‧‧‧voltage source

T‧‧‧O crystal

W‧‧‧Scope

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2 is a schematic diagram showing a data transmission system according to an embodiment of the present invention; 3 is a schematic diagram of an input signal voltage detecting module according to an embodiment of the present invention; FIG. 4 is a schematic diagram of an input signal voltage detecting module according to an embodiment of the present invention; FIG. 5 is a diagram showing an embodiment of the present invention; FIG. 6A is a schematic diagram showing changes in output signal voltage according to an embodiment of the present invention; FIG. 6B is a schematic diagram showing changes in output signal voltage according to an embodiment of the present invention; and FIG. A schematic diagram of a method for detecting an input signal voltage according to an embodiment of the present invention is shown.

Embodiments of the invention are discussed in detail below. However, it will be appreciated that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific content. The specific embodiments discussed are illustrative only and are not intended to limit the scope of the invention.

Please refer to FIG. 2, which is a schematic diagram of a data transmission system 200 according to an embodiment of the present invention. The data transmission system 200 includes a transmitter 210 and a receiver 220. The operation mode of the transmitter 210 includes a training mode and a normal mode. When the operating mode of the transmitter 210 is the training mode, the transmitter 210 transmits a clock recovery pattern signal for the receiver 220 to perform frequency locking. When the frequency lock is completed, the operation mode of the transmitter 210 is switched to the normal mode to transmit the data signal to the receiver 220. The receiver 220 includes a phase-locked loop (PLL) circuit 222 and an input signal voltage detection module 224. The phase-locked loop circuit 222 processes the frequency input signal F _IN corresponding to the data signal to generate the input signal voltage V _IN , and adjusts the frequency of the frequency output signal F _OUT according to the input signal voltage V _IN to lock the frequency output signal F _OUT to the correct one. frequency. The input signal voltage detecting module 224 is configured to detect the input signal voltage V _IN . If the change of the input signal voltage V _IN is detected to be too large, the representative frequency output signal F _{OUT is} not locked at the correct frequency. At this time, the control signal CTRL generated by the input signal voltage detecting module 224 instructs the transmitter 210 to switch to the training mode, and causes the transmitter 210 to transmit the clock return pattern signal to the receiver 220 to re-transmit the frequency output signal F _{OUT .} The frequency is locked.

Please refer to FIG. 3 , which is a schematic diagram of an input signal voltage detecting module 300 according to an embodiment of the present invention. The input signal voltage detecting module 300 is an embodiment of the input signal voltage detecting module 224 in FIG. The input signal voltage detecting module 300 includes a comparison voltage generating unit 310, a comparing unit 320, and a control unit 330. The comparison voltage generating unit 310 receives the input signal voltage V _IN and generates an output signal voltage V _OUT and comparison voltages V _C1 , V _C2 according to the input signal voltage V _IN . The comparing unit 320 is configured to lock the comparison voltages V _C1 and V _C2 according to the clock signal CKS, and compare the output signal voltage V _OUT with the comparison voltages V _C1 and V _C2 to generate comparison results CR1 and CR2 , respectively. The control unit 330 generates a control signal CTRL based on the comparison results CR1, CR2.

Please refer to FIG. 4 , which is a schematic diagram of an input signal voltage detecting module 400 according to an embodiment of the present invention. The input signal voltage detecting module 400 is An embodiment of the input signal voltage detection module 300. The input signal voltage detecting module 400 includes a comparison voltage generating unit 410, a comparing unit 420, and a control unit 430. The comparison voltage generating unit 410, the comparing unit 420, and the control unit 430 correspond to the comparison voltage generating unit 310, the comparing unit 320, and the control unit 330 in FIG. 3, respectively.

The comparison voltage generating unit 410 includes an operational amplifier OP, a transistor T, a capacitor C, resistors R1, R2, R3, and a variable resistance unit RV. The non-inverting input terminal of the operational amplifier OP receives the output signal voltage V _OUT , and the negative phase input terminal of the operational amplifier OP receives the input voltage signal V _IN . The source of the transistor T is electrically connected to the voltage source VDD, and its gate is electrically connected to the output terminal of the operational amplifier OP. The capacitor C and the resistor R1 are connected in series, and are electrically connected to the gate and the source of the transistor T, respectively. One end of the resistor R2 is electrically connected to the source of the transistor T, and is used to provide a comparison voltage V _C1 . The other end of the resistor R2 is used to provide an output signal voltage V _OUT . One end of the resistor R3 is electrically connected to the other end of the resistor R2, and the other end of the resistor R3 is used to provide a comparison voltage V _C2 . The variable resistance unit RV is electrically connected between the resistor R3 and the ground GND for adjusting the comparison voltages V _C1 , V _C2 and the width therebetween.

The comparison unit 420 includes a high voltage comparison unit 421 and a low voltage comparison unit 422. The high voltage comparison unit 421 is configured to generate a comparison result CR1 according to the output signal voltage V _OUT , the comparison voltage V _{C1 and the} timely pulse signal CKS. The high voltage comparison unit 421 includes a switch SW1, a capacitor C1, and a comparator CP1. The switch SW1 is electrically connected to one end of the resistor R2, and its state is switched to an on or off state according to the clock signal CKS. The capacitor C1 is electrically connected between the switch SW1 and the ground GND. When the clock signal CKS is at the high level, the switch SW1 is in the off state, and the potential difference across the capacitor C1 is updated to the comparison voltage V _C1 . The non-inverting input terminal of the comparator CP1 is electrically connected to the other end of the resistor R2. The negative phase input terminal of the comparator CP1 is electrically connected to the capacitor C1, and the output terminal of the comparator CP1 is used to output the comparison result CR1. When the output signal voltage V _{OUT is} smaller than the comparison voltage V _C1 , the potential of the comparison result CR1 is at a low level. Conversely, when the output signal voltage V _{OUT is} greater than the comparison voltage V _C1 , the potential of the comparison result CR1 is at a high level.

The low voltage comparison unit 422 is configured to generate a comparison result CR1 according to the output signal voltage V _OUT , the comparison voltage V _{C1 and the} timely pulse signal CKS. Similar to the high voltage comparison unit 421, the low voltage comparison unit 422 includes a switch SW2, a capacitor C2, and a comparator CP2. The switch SW2 is electrically connected to one end of the resistor R3, and its state is switched to an on or off state according to the clock signal CKS. The capacitor C2 is electrically connected between the switch SW2 and the ground GND. When the clock signal CKS is at the high level, the switch SW2 is in the off state, and the potential difference across the capacitor C2 is updated to the comparison voltage V _C2 . The non-inverting input terminal of the comparator CP2 is electrically connected to the other end of the resistor R3, the negative phase input terminal of the comparator CP2 is electrically connected to the capacitor C2, and the output terminal of the comparator CP2 is used to output the comparison result CR2. When the output signal voltage V _{OUT is} smaller than the comparison voltage V _C2 , the potential of the comparison result CR2 is at a low level. Conversely, when the output signal voltage V _{OUT is} greater than the comparison voltage V _C2 , the potential of the comparison result CR2 is at a high level.

The control unit 430 receives the comparison results CR1, CR2 and generates a control signal CTRL based on the comparison results CR1, CR2. If the comparison result CR1 is at a low level and the comparison result CR2 is at a high level, indicating that the output signal voltage V _OUT is between the comparison voltages V _C1 and V _C2 , the control signal CTRL indicates that the transmitter 210 remains in the normal mode. If the comparison results CR1 and CR2 are both high level or low level, indicating that the output signal voltage V _OUT is above the comparison voltage V _C1 or below the comparison voltage V _C2 , the control signal CTRL indicates that the transmitter 210 switches. To the training mode, the transmitter 210 transmits a clock recovery pattern signal to the receiver 220 for frequency locking of the frequency output signal F _OUT .

Please refer to FIG. 5, which is a schematic diagram of an input signal voltage detecting module 500 according to an embodiment of the present invention. The input signal voltage detecting module 500 is another embodiment of the input signal voltage detecting module 300. The input signal voltage detecting module 500 includes a comparison voltage generating unit 510, a comparing unit 520, and a control unit 530. The comparison voltage generating unit 510, the comparing unit 520, and the control unit 530 correspond to the comparison voltage generating unit 310, the comparing unit 320, and the control unit 330 in FIG. 3, respectively. The structure and implementation of the comparison voltage generating unit 510 are the same as those of the comparison voltage generating unit 410, and thus will not be described herein.

The comparison unit 520 includes a high voltage comparison unit 521 and a low voltage comparison unit 522. The high voltage comparison unit 521 is configured to use the output signal voltage V _OUT , the comparison voltage V _{C1 , the} time pulse signal CKS, A comparison result CR1 is generated. In this embodiment, the clock signal CKS, They are mutually inverted signals. The high voltage comparison unit 521 includes switches SW1, SW2, SW3, a capacitor C1, and a comparator CP1. The switch SW1 is electrically connected to one end of the resistor R2, and its state is switched to an on or off state according to the clock signal CKS. The switch SW2 is electrically connected to the other end of the resistor R2 and the switch SW1, and the state is based on the clock signal Switch to the on or off state. The capacitor C1 is electrically connected to the switches SW1 and SW2. The switch SW3 is electrically connected to the capacitor C1 and the common input voltage V _CMI , and its state is switched to an on or off state according to the clock signal CKS. The non-inverting input terminal of the comparator CP1 is electrically connected to the common input voltage V _CMI , the negative phase input terminal of the comparator CP1 is electrically connected to the capacitor C1 and the switch SW3, and the output terminal of the comparator is used for outputting the comparison result CR1.

When the clock signal CKS is at the high level, the switches SW1 and SW3 are in the off state, and the switch SW2 is in the on state. At this time, the amount of charge stored in the capacitor C1 is C _Q1 ×(V _C1 -V _CMI ), where C _Q1 represents Capacitance of capacitor C1. Then, the switching clock signal CKS is switched to the low level, the switches SW1 and SW3 are switched to the on state, and the switch SW2 is switched to the off state. At this time, the amount of charge stored in the capacitor C1 is C _Q1 ×(V _OUT -V _X1 ), where V _X1 is the voltage between the capacitor C1 and the comparator CP1. Capacitor C1 stores the amount of charge before and after the clock signal CKS is switched to the low level, that is, C _Q1 × (V _C1 - V _CMI ) = C _Q1 × (V _OUT - V _X1 ). Since the capacitance C _{Q1 of the} capacitor C1 is not equal to 0, the above equation can be simplified to obtain V _X1 =V _CMI +(V _OUT -V _C1 ). Therefore, when the voltage V _{X1 is} less than the common input voltage V _CMI , the potential of the comparison result CR1 is a high level, which represents that the output signal voltage V _{OUT is} smaller than the comparison voltage V _C1 . Conversely, when the voltage V _{X1 is} greater than the common input voltage V _CMI , the potential of the comparison result CR1 is a low level, which represents that the output signal voltage V _{OUT is} greater than the comparison voltage V _C1 .

The low voltage comparison unit 522 is configured to detect the signal voltage V _OUT , the comparison voltage V _{C2 , and the} pulse signal CKS according to the output voltage. A comparison result CR2 is generated. The low voltage comparison unit 522 includes switches SW4, SW5, SW6, a capacitor C2, and a comparator CP2. The switch SW4 is electrically connected to one end of the resistor R3, and its state is switched to an on or off state according to the clock signal CKS. The switch SW5 is electrically connected to the other end of the resistor R3 and the switch SW2, and the state is based on the clock signal Switch to the on or off state. The capacitor C2 is electrically connected to the switches SW4 and SW5. The switch SW6 is electrically connected to the capacitor C2 and the common input voltage V _CMI , and its state is switched to an on or off state according to the clock signal CKS. The non-inverting input terminal of the comparator CP2 is electrically connected to the common input voltage V _CMI , the negative phase input terminal of the comparator CP2 is electrically connected to the capacitor C2 and the switch SW6, and the output end of the comparator is used to output the comparison result CR2.

When the clock signal CKS is at the high level, the switches SW4 and SW6 are in the off state, and the switch SW5 is in the on state. At this time, the amount of charge stored in the capacitor C2 is C _Q2 × (V _C2 - V _CMI ), where C _Q2 represents Capacitance of capacitor C2. Then, the switching clock signal CKS is switched to the low level, the switches SW4 and SW6 are switched to the on state, and the switch SW5 is switched to the off state. At this time, the amount of charge stored in the capacitor C2 is C _Q2 × (V _OUT - V _X2 ), where V _X2 is the voltage between the capacitor C2 and the comparator CP2. The amount of charge stored in the capacitor C2 before and after the clock signal CKS is switched to the low level is equal, that is, C _Q2 × (V _C2 - V _CMI ) = C _Q2 × (V _OUT - V _X2 ). Since the capacitance C _{Q2 of the} capacitor C2 is not equal to 0, the above equation can be simplified to obtain V _X2 = V _CMI + (V _OUT - V _C2 ). Therefore, when the voltage V _{X2 is} less than the common input voltage V _CMI , the potential of the comparison result CR2 is a high level, which represents that the output signal voltage V _{OUT is} smaller than the comparison voltage V _C2 . Conversely, when the voltage V _{X2 is} greater than the common input voltage V _CMI , the potential of the comparison result CR2 is a low level, which represents that the output signal voltage V _{OUT is} greater than the comparison voltage V _C2 .

The control unit 530 receives the comparison results CR1, CR2 and generates a control signal CTRL based on the comparison results CR1, CR2. If the comparison result CR1 is at a high level and the comparison result CR2 is at a low level, indicating that the output signal voltage V _OUT is between the comparison voltages V _C1 and V _C2 , the control signal CTRL indicates that the transmitter 210 remains in the normal mode. If the comparison results CR1 and CR2 are both high level or low level, indicating that the output signal voltage V _OUT is above the comparison voltage V _C1 or below the comparison voltage V _C2 , the control signal CTRL indicates that the transmitter 210 switches. To the training mode, the transmitter 210 transmits a clock recovery pattern signal to the receiver 220 for frequency locking of the frequency output signal F _OUT .

Please refer to FIG. 6A and FIG. 6B, which are respectively schematic diagrams showing changes in output signal voltage according to an embodiment of the present invention. A range W is formed between the comparison voltages V _C1 and V _C2 . The width or position of the range W can be adjusted according to the input signal voltage V _IN or the resistance value of the variable resistance unit RV. In FIG. 6A, the output signal voltage V _{OUT is} not higher than the comparison voltage V _C1 or lower than the comparison voltage V _C2 , that is, the range W is not exceeded. At this time, the control signal CTRL generated by the control unit indicates that the transmitter 210 remains in the normal mode. The transmitter 210 is caused to continue transmitting the data signal to the receiver 220. In FIG. 6B, the output signal voltage V _{OUT is} initially located in the range W, and then decreases below the comparison voltage V _C2 , indicating that the output signal voltage V _OUT changes too much. At this time, the control signal CTRL generated by the control unit indicates the transmitter 210. Switching to the training mode causes the transmitter 210 to transmit a clock recovery pattern signal to the receiver 220 for frequency locking of the frequency output signal F _OUT .

Please refer to FIG. 7 , which is a schematic diagram of an input signal voltage detecting method 700 according to an embodiment of the present invention. The input signal voltage detecting method 700 is applicable to the input signal voltage detecting modules 224, 300, 400, and 500 illustrated in FIGS. 2 to 5. First, in step 702, the input signal voltage V _{IN is} sampled to generate an output signal voltage V _OUT and a comparison voltage V _C1 , V _C2 , wherein the comparison voltage V _{C1 is} higher than the comparison voltage V _C2 . Next, in step 704, the output signal voltage V _OUT and the comparison voltage V _C1 are compared according to the clock signal CKS to generate a comparison result CR1. When step 704 is performed, step 706 is simultaneously performed, and the output signal voltage V _OUT and the comparison voltage V _C2 are compared according to the clock signal CKS to generate a comparison result CR2. Finally, step 708 is performed to generate a control signal CTRL according to the comparison results CR1, CR2 for switching the operation mode of the transmitter 210. If the output signal voltage V _{OUT is} higher than the comparison voltage V _C1 or lower than the comparison voltage V _C2 , the control signal CTRL instructs the transmitter 210 to switch to the training mode, so that the transmitter 210 transmits the clock recovery pattern signal to the receiver 220 for performing. The frequency output signal F _OUT is frequency locked.

In summary, the input signal voltage detecting module and method of the present invention and the related data transmission system can determine whether the frequency output signal is locked at the correct frequency by detecting the input signal voltage in real time. If the frequency output signal is not locked at the correct frequency, the system is judged to be abnormal, and the corresponding processing can be performed immediately, so that the data transmission system re-locks the frequency output signal to lock the frequency output signal at the correct frequency, thereby improving the system. efficacy.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art may, without departing from the spirit of the invention. And the scope of the invention is defined by the scope of the appended claims.

300‧‧‧Input signal voltage detection module

310‧‧‧Comparative voltage generating unit

320‧‧‧Comparative unit

330‧‧‧Control unit

CKS‧‧‧ clock signal

CR1, CR2‧‧‧ comparison results

CTRL‧‧‧ control signal

V _C1 , V _C2 ‧‧‧ comparison voltage

The input signal voltage V _IN ‧‧‧

V _OUT ‧‧‧Output signal voltage

Claims (10)

An input signal voltage detecting module is configured to detect an input signal voltage. The voltage detecting module includes: a comparison voltage generating unit configured to generate an output signal voltage and a first comparison voltage according to the input signal voltage And a second comparison voltage; a comparison unit configured to generate a first comparison result and a second comparison result according to the output signal voltage, the first comparison voltage, the second comparison voltage, and a first clock signal; And a control unit, configured to generate a control signal according to the first comparison result and the second comparison result. The input signal voltage detecting module of claim 1, wherein the comparison voltage generating unit comprises: an operational amplifier having a positive phase input terminal, a negative phase input terminal and an output terminal, the positive phase of the operational amplifier The input terminal receives the output signal voltage, and the negative phase input terminal of the operational amplifier receives the input voltage signal; a transistor having a source, a gate and a drain, the source of the transistor is electrically connected a voltage source, and the gate of the transistor is electrically connected to the output end; a first resistor has a first end and a second end, and the first end of the first resistor is electrically connected to the transistor a source for providing the first comparison voltage, and a second end of the first resistor for providing the output signal voltage; a second resistor having a first end and a second end, the first end of the second resistor being electrically connected to the second end of the first resistor and configured to provide the output signal voltage, and the second resistor The second end is configured to provide the second comparison voltage. The input signal voltage detecting module of claim 2, wherein the comparing unit comprises: a high voltage comparing unit, configured to generate the first according to the output signal voltage, the first comparison voltage, and the first clock signal a comparison result, the high voltage comparison unit includes: a first switch electrically connected to the first end of the first resistor, the first switch configured to switch to an on or off state according to the first clock signal; a first capacitor electrically connected between the first switch and a ground; and a first comparator having a positive phase input terminal, a negative phase input terminal and an output terminal, the first comparator being positive The phase input terminal is electrically connected to the second end of the first resistor, the negative phase input end of the first comparator is electrically connected to the first capacitor, and the output end of the first comparator is used to output the first a comparison result; and a low voltage comparison unit configured to generate the second comparison result according to the output signal voltage, the second comparison voltage, and the first clock signal, the low voltage comparison unit comprising: a second switch, Sexually connected to the second The second end of the resistor, The second switch is configured to switch to an on or off state according to the first clock signal; a second capacitor electrically connected between the second switch and the ground; and a second comparator having a positive a phase input terminal, a negative phase input terminal and an output terminal, wherein the non-inverting input terminal of the second comparator is electrically connected to the first end of the second resistor, and the negative phase input terminal of the second comparator is electrically connected And the output of the second comparator is used to output the second comparison result. The input signal voltage detecting module of claim 2, wherein the comparing unit comprises: a high voltage comparing unit, configured to: according to the output signal voltage, the first comparison voltage, a common input voltage, the first time The first signal is generated by the pulse signal and the second clock signal. The high voltage comparison unit includes: a first switch electrically connected to the first end of the first resistor, the first switch being used according to the first The first switch is electrically connected to the second end of the first resistor and the first switch, and the second switch is configured to be turned on according to the second clock signal. Or a closed state; a first capacitor electrically connected to the first switch and the second switch; a third switch electrically connected to the first capacitor and the common input a third switch for switching to an on or off state according to the first clock signal; and a first comparator having a positive phase input terminal, a negative phase input terminal and an output terminal, the first The positive phase input terminal of the comparator is electrically connected to the common input voltage, the negative phase input end of the first comparator is electrically connected to the first capacitor and the third switch, and the output end of the first comparator is used And outputting the first comparison result; and a low voltage comparison unit, configured to generate the first according to the output signal voltage, the second comparison voltage, the common input voltage, the first clock signal, and the second clock signal As a result of the comparison, the low voltage comparison unit includes: a fourth switch electrically connected to the second end of the second resistor, wherein the fourth switch is configured to switch to an on or off state according to the first clock signal; The fifth switch is electrically connected to the first end of the second resistor and the fourth switch, and the fifth switch is configured to switch to an on or off state according to the second clock signal; a second capacitor is electrically connected In the fourth switch and the a sixth switch electrically connected to the second capacitor and the common input voltage, the sixth switch for switching to an on or off state according to the first clock signal; and a second comparator having a positive phase input terminal, a negative phase input terminal and an output terminal, wherein the non-inverting input terminal of the second comparator is electrically connected to the common input voltage, and the negative phase input terminal of the second comparator is electrically The second capacitor is connected to the sixth switch, and the output of the second comparator is used to output the second comparison result. The input signal voltage detecting module of claim 4, wherein the first clock signal and the second clock signal are mutually inverted. The input signal voltage detecting module of claim 2, wherein the comparison voltage generating unit further comprises a variable resistance unit electrically connected between the second end of the second resistor and a ground. A data transmission system includes a transmitter and a receiver. The operation mode of the transmitter includes a training mode and a normal mode. When the operation mode of the transmitter is the normal mode, the transmitter Transmitting a data signal, the receiver is configured to receive the data signal, and the receiver includes an input signal voltage detecting module, the input signal voltage detecting module includes: a comparison voltage generating unit configured to respond to the corresponding data The input signal voltage of the signal generates an output signal voltage, a first comparison voltage, and a second comparison voltage, wherein the first comparison voltage is higher than the second comparison voltage; and a comparison unit is configured to perform, according to the output signal voltage, The first comparison voltage, the second comparison voltage, and a first clock signal generate a first comparison result and a second comparison result; and a control unit configured to use the first comparison result and the second comparison result Generating a control signal for switching the operation of the transmitter Mode. The data transmission system of claim 7, wherein if the output signal voltage is higher than the first comparison voltage or the output signal voltage is lower than the second comparison voltage, the control signal indicates that the transmitter switches to the training mode and Transmit a clock recovery pattern signal. An input signal voltage detecting method is applicable to a data transmission system, the data transmission system includes a transmitter and a receiver, and the operation mode of the transmitter includes a training mode and a normal mode. When the operation mode of the transmitter is the normal mode, the transmitter transmits a data signal, and the receiver is configured to receive the data signal. The input signal voltage detection method includes: sampling one of the data signals to input a signal voltage to generate An output signal voltage, a first comparison voltage, and a second comparison voltage, wherein the first comparison voltage is higher than the second comparison voltage; comparing the output signal voltage with the first comparison voltage according to a clock signal to generate a first comparison result; comparing the output signal voltage and the second comparison voltage according to the clock signal to generate a second comparison result; and generating a control signal according to the first comparison result and the second comparison result, The control signal is used to switch the operating mode of the transmitter. The input signal voltage detecting method according to claim 9, wherein If the output signal voltage is higher than the first comparison voltage or the output signal voltage is lower than the second comparison voltage, the control signal indicates that the transmitter switches to the training mode and transmits a clock recovery pattern signal. .