CN103399808A - Method for achieving crystal oscillator dual redundancy in flight control computer - Google Patents
Method for achieving crystal oscillator dual redundancy in flight control computer Download PDFInfo
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- CN103399808A CN103399808A CN2013102240058A CN201310224005A CN103399808A CN 103399808 A CN103399808 A CN 103399808A CN 2013102240058 A CN2013102240058 A CN 2013102240058A CN 201310224005 A CN201310224005 A CN 201310224005A CN 103399808 A CN103399808 A CN 103399808A
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Abstract
The invention provides a method for achieving crystal oscillator dual redundancy in a flight control computer. The flight control computer comprises two crystal oscillators, an FPGA and a DSP. The method includes the steps that a dual-crystal-oscillator clock is sent to the FPGA, and the frequency of the dual-crystal-oscillator clock is detected through an FPGA crystal oscillator clock mutual-detection module, the two crystal oscillators supply clock signals for the DSP and the FPGA respectively if both the two crystal oscillators normally work, when oscillation stop occurs to either one of the crystal oscillators, a clock switching module is started, the other crystal oscillator simultaneously supplies clock signals for the DSP and the FPGA, and meanwhile a reset module is started to supply reset signals for the DSP and the FPGA. The mutual detection conducted for finding out whether oscillation stop occurs to the dual-crystal-oscillator clock or not is achieved. When oscillation stop occurs to either one of the crystal oscillators, the other single crystal oscillator simultaneously supplies the reliable clock signals for the DSP and the FPGA through the clock switching module, and reliability of using the clock of the flight control computer can be effectively improved through the whole crystal oscillator dual redundancy design method.
Description
Technical field
The present invention relates to a kind of method that realizes the two redundancies of crystal oscillator in flight control computer, be applicable to the flight control computer clock High Reliability Design field based on DSP and FPGA framework.
Background technology
Along with the development of the national defence information processing technology, a large amount of flight control computers has all adopted the embedded architecture of DSP+FPGA at present, and DSP and FPGA need to introduce crystal oscillator clock.Crystal oscillator is one of the large Primary Component of three on flight control computer (DSP, FPGA and crystal oscillator), is also " heartbeat " generator of each integrated circuit board.Present crystal oscillator (specially referring to active crystal oscillator) using method mainly contains two kinds: the one,, with two crystal oscillators, send into respectively DSP and FPGA.The 2nd,, with a crystal oscillator, after being driven by clock driver, then send into respectively DSP and FPGA.
Above-mentioned two kinds of crystal oscillator cut-in methods, a common critical defect is arranged: if during any road crystal oscillator failure of oscillation, DSP or FPGA will quit work, and then by the flight control computer that the DSP+FPGA framework forms, can't be used, and the crystal oscillator failure of oscillation topmost failure mode (the inefficacy ratio is up to 80%) that is crystal oscillator, therefore above-mentioned two kinds of crystal oscillator cut-in methods, greatly reduce the reliability that the flight control computer clock uses.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of method that realizes the two redundancies of crystal oscillator in flight control computer is provided, while having realized any road crystal oscillator failure of oscillation, another road crystal oscillator provides reliable and stable clock signal for DSP and FPGA simultaneously, guarantees the high reliability that the flight control computer clock uses.
Technical solution of the present invention is:
A kind ofly realize that in flight control computer the method for the two redundancies of crystal oscillator comprises that step is as follows:
(1) twin crystal is shaken clock signal access FPGA, FPGA comprises the mutual detection module of crystal oscillator clock, clock handover module and reseting module, utilizes the mutual detection module of FPGA crystal oscillator clock to realize that the frequency of twin crystal between shaking detects mutually;
(2) all working properly if twin crystal shakes, FPGA incites somebody to action a wherein road crystal oscillator access DSP and provides clock signal for DSP, and another road crystal oscillator access FPGA provide clock signal for FPGA; If the unexpected failure of oscillation of crystal oscillator of access DSP enters step (3); If the unexpected failure of oscillation of crystal oscillator of access FPGA enters step (4);
(3) the mutual detection module output alarm signal of FPGA crystal oscillator clock carries out the switching of clock signal to FPGA clock handover module, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access FPGA is to supply with DSP with the clock signal of failure of oscillation crystal oscillator same frequency to use, and by reset all the other operational modules of DSP and FPGA of reseting module, the clock signal that accesses simultaneously FPGA continues as FPGA provides clock;
(4) the mutual detection module output alarm signal of FPGA crystal oscillator clock carries out the switching of clock signal to FPGA clock handover module, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access DSP is to supply with FPGA with the clock signal of failure of oscillation crystal oscillator same frequency to use, and by reset all the other operational modules of DSP and FPGA of reseting module, the clock signal that accesses simultaneously DSP continues as DSP provides clock.
The mutual detection module of described FPGA crystal oscillator clock comprises frequency division module, two frequency discrimination modules, warning discrimination module, frequency division module is low-frequency clock and high frequency clock signal with the twin crystal clock signal frequency division that shakes, and by make timing signal with low-frequency clock, high frequency clock is counted to realize the mutual detection of twin crystal between shaking in the frequency discrimination module.The warning discrimination module, according to frequency discrimination module result, is exported the alerting signal of corresponding crystal oscillator failure of oscillation when a certain crystal oscillator failure of oscillation.
Described reseting module reset under powering-off state not DSP and all the other operational modules of FPGA, coordinate the clock after switching that flight control computer is resumed work again, at twin crystal, shakes while all working, and reseting module is inoperative.
The present invention's beneficial effect compared with prior art is:
(1) the present invention does not introduce third party's clock, has realized the twin crystal whether mutual detection of failure of oscillation of clock of shaking, and has improved high efficiency and the convenience of system;
(2) during any road crystal oscillator failure of oscillation, system is automatically completed clock and is switched in real time, by another crystal oscillator, provides clock signal for DSP and FPGA simultaneously, has improved the reliability that the flight control computer clock uses.
(3) the two redundancy design method highly versatiles of this crystal oscillator, do not increase device, and hardware cost is low, and reliability is high, is beneficial to and applies.
Description of drawings
Fig. 1 is the two redundancy design method block diagrams of crystal oscillator that the present invention realizes;
Fig. 2 is the mutual detection module block diagram of crystal oscillator clock that the present invention realizes;
Fig. 3 is clock handover module and the reseting module block diagram that the present invention realizes.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described in detail.
The invention provides a kind of method that realizes the two redundancies of crystal oscillator in flight control computer, while having realized any road crystal oscillator failure of oscillation, another road crystal oscillator provides reliable and stable clock signal for DSP and FPGA simultaneously, guarantees the high reliability that the flight control computer clock uses.As shown in Figure 1, the present invention is mainly by with lower module, forming: twin crystal shakes, FPGA, DSP, and wherein FPGA comprises again the mutual detection module of crystal oscillator clock, clock handover module, reseting module.twin crystal shakes clock signal is sent into FPGA, utilizing the mutual detection module of FPGA crystal oscillator clock to carry out the frequency that twin crystal shakes detects mutually, if twin crystal shakes all working properly, FPGA offers respectively FPGA and DSP with the two-way crystal oscillator clock signal, when in the crystal oscillator of access FPGA and DSP during any road failure of oscillation, the mutual detection module of FPGA crystal oscillator clock arrives the clock handover module with output alarm signal, the crystal oscillator that the clock handover module utilizes failure of oscillation not provides clock signal for FPGA and DSP simultaneously, all the other operational modules of FPGA are (except the mutual detection module of crystal oscillator simultaneously, the clock handover module, all the other operational modules outside reseting module) and DSP complete and reset.
As shown in Figure 2, the mutual detection module of FPGA crystal oscillator clock comprises frequency division module, two frequency discrimination modules and warning discrimination module; Twin crystal shakes and clock signal is sent into frequency division module carries out clock division, be divided into low frequency and high-frequency signal (high-frequency signal and low frequency signal relation meet the nyquist frequency sampling condition), then make regularly the numerical value that high frequency clock is counted to get and theoretical value (numerical value that the high-frequency signal value obtains divided by the low frequency signal value) relatively by low-frequency clock in the frequency discrimination module, realization is to the whether judgement of failure of oscillation of crystal oscillator under high frequency clock in comparer; Simultaneously after powering on to the low-frequency clock counting, the numerical value that will count to get in real time and theoretical value (numerical value that the high-frequency signal value obtains divided by the low frequency signal value) comparison, the whether judgement of failure of oscillation of crystal oscillator under comparer draws low-frequency clock.In order to ensure the accuracy that the crystal oscillator failure of oscillation is differentiated, the differentiation result of two frequency discrimination module outputs is sent into the warning discrimination module, only have the crystal oscillator failure of oscillation to differentiate in situation about coming to the same thing, could export the alerting signal of corresponding crystal oscillator failure of oscillation.
, for the more precisely bright two redundancies of crystal oscillator that how to realize in flight control computer, take crystal oscillator 1 and crystal oscillator 2 (establish the clock signal of crystal oscillator 1 output as CLKA, the clock signal of crystal oscillator 2 outputs is CLKB), for example, be elaborated:
Twin crystal shakes and clock signal clk A, CLKB are sent into the mutual detection module of crystal oscillator clock carries out clock division, the CLKA frequency division is CLKA1 and CLKA2, the CLKB frequency division is CLKB1 and CLKB2, wherein the frequency of CLKA1 is the integral multiple more than 2 times of CLKB1, the frequency of CLKB2 is the integral multiple more than 2 times (meeting the nyquist frequency sampling condition) of CLKA2, make timing signal by low-frequency clock high frequency clock is counted to realize the mutual detection of twin crystal between shaking, the mutual testing process of crystal oscillator clock is as follows:
For the clock CLKA1 after frequency division, CLKB1, send into frequency discrimination module 1, utilizes 1 pair of CLKA1 counting of counter, and count value is m1; CLKB1 sends into trigger 1 latching accumulator 1 currency n1, the numerical value that n1 and pre-register p1(p1 value are obtained divided by CLKB1 for CLKA1) send into comparer 2:n1=p1, illustrate that the CLKA clock is normal, the numerical value m1 that remove counter 1 this moment counts again, n1＜p1, illustrate that the CLKA1 clock disappears, i.e. crystal oscillator 1 failure of oscillation; At comparer 1, m1 value and p1 value are compared in real time, work as m1 p1, counter 1 numerical value is in time removed, and illustrates that the CLKB1 clock disappears, and this hour counter 1 stops counting, i.e. crystal oscillator 2 failure of oscillations.
In like manner, clock CLKA2, CLKB2 for after frequency division, send into frequency discrimination module 2, utilize 2 pairs of CLKB2 countings of counter, count value is m2, and CLKA2 sends into trigger 2 latching accumulator 2 currency n2, the numerical value that n2 and pre-register p2(p2 value are obtained divided by CLK A2 for CLK B2) send into comparer 4, n2=p2, illustrate that the CLKB2 clock is normal, the numerical value m2 that remove counter 2 this moment counts again, n2＜p2, illustrate that the CLKB2 clock disappears, i.e. crystal oscillator 2 failure of oscillations; At comparer 3, m2 value and p2 value are compared in real time, work as m2 p2, counter 2 numerical value are in time removed, and illustrate that the CLKA2 clock disappears, and this hour counter 2 stops counting, i.e. crystal oscillator 1 failure of oscillation.
When twin crystal shook normal operation, crystal oscillator 1 was sent clock signal to DSP is provided through FPGA, and crystal oscillator 2 provides clock signal to FPGA, at this moment, and the output of the mutual detection module alarm free of crystal oscillator clock signal.
When frequency discrimination module 1 and frequency discrimination module 2 are measured crystal oscillator 1 failure of oscillation simultaneously, by with door 2, warning discrimination module output alarm signal ALARM_S1 is 1, shows crystal oscillator 1 failure of oscillation that accesses DSP.When frequency discrimination module 1 and frequency discrimination module 2 are measured crystal oscillator 2 failure of oscillation simultaneously, by with door 1, warning discrimination module output alarm signal ALARM_S2 is 1, shows crystal oscillator 2 failure of oscillations that access FPGA.
As shown in Figure 3, the alerting signal of the mutual detection module output of crystal oscillator clock offers the clock handover module, and FPGA clock handover module switches clock signal according to the alerting signal that detects, and clock switching detailed process is as follows:
Design clock handover module 1 and clock handover module 2, when ALARM_S1=1, show crystal oscillator 1 failure of oscillation that accesses DSP, 1 work of clock handover module, the clock signal clk B of crystal oscillator 2 outputs of access FPGA is converted to CLKA ' (frequency numerical value is equal to the frequency numerical value of clock signal clk A) through phaselocked loop (PLL), CLKA ' is accessed DSP clock end for it through FPGA, to replace the CLKA clock.The running status of DSP is unknown due to this moment, and the DSP that therefore need to reset, allow DSP again from FLASH, move program to RAM, and the DSP program starts to carry out, and FPGA all the other operational modules simultaneously reset.When ALARM_S2=1, show crystal oscillator 2 failure of oscillations that access FPGA, 2 work of clock handover module, the clock signal clk A of crystal oscillator 1 output of access DSP is converted to CLKB ' (frequency numerical value is equal to the frequency numerical value of CLKB) through phaselocked loop (PLL), CLKB ' is supplied with FPGA internal clocking is provided, to replace the CLKB clock.Because the running status in this moment FPGA is unknown, all the other operational modules of FPGA that need to reset, DSP simultaneously resets.
As shown in Figure 3, the present invention has introduced reseting module, and CLKOUT1 provides clock signal for reseting module, ALARM_S1 and ALARM_S2 process or door access reseting module, and when the alarm free signal produced, reseting module was set to high level.When having alerting signal to produce, the low level signal of reseting module output certain width, not resetting simultaneously under powering-off state at flight control computer, (any road goes wrong as long as twin crystal shakes for DSP and all the other operational modules of FPGA, all with all the other operational modules of DSP and FPGA that reset simultaneously), again recover flight control computer work; Shake while all working at twin crystal, reseting module is inoperative.
The present invention has utilized the built-in phaselocked loop of FPGA, therefore requires built-in at least 2 phaselocked loops of fpga chip (PLL) of selecting.Main flow FPGA all is built-in with 2 and above PLL at present.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (3)
1. method that realizes the two redundancies of crystal oscillator in flight control computer is characterized in that comprising that step is as follows:
(1) the clock signal access FPGA that twin crystal is shaken export, FPGA comprises the mutual detection module of crystal oscillator clock, clock handover module and reseting module, utilizes the mutual detection module of FPGA crystal oscillator clock to realize that the frequency that twin crystal shakes detects mutually;
(2) all working properly if twin crystal shakes, FPGA incites somebody to action a wherein road crystal oscillator access DSP and provides clock signal for DSP, and another road crystal oscillator access FPGA provide clock signal for FPGA; If the unexpected failure of oscillation of crystal oscillator of access DSP enters step (3); If the unexpected failure of oscillation of crystal oscillator of access FPGA enters step (4);
(3) the mutual detection module output alarm signal of FPGA crystal oscillator clock carries out the switching of clock signal to FPGA clock handover module, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access FPGA is to supply with DSP with the clock signal of failure of oscillation crystal oscillator same frequency to use, and by reseting module reset DSP and all the other operational modules of FPGA, the clock signal that accesses simultaneously FPGA continues as FPGA provides clock;
(4) the mutual detection module output alarm signal of FPGA crystal oscillator clock carries out the switching of clock signal to FPGA clock handover module, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access DSP is to supply with FPGA with the clock signal of failure of oscillation crystal oscillator same frequency to use, and by reseting module reset DSP and all the other operational modules of FPGA, the clock signal that accesses simultaneously DSP continues as DSP provides clock.
2. a kind of method that realizes the two redundancies of crystal oscillator in flight control computer according to claim 1, it is characterized in that: the mutual detection module of FPGA crystal oscillator clock in described step (1) comprises frequency division module, two frequency discrimination modules and warning discrimination module, frequency division module is low-frequency clock and high frequency clock signal with the twin crystal clock signal frequency division that shakes, by make timing signal with low-frequency clock, high frequency clock is counted to realize the mutual detection of twin crystal between shaking in the frequency discrimination module, the warning discrimination module is according to frequency discrimination module result, export the alerting signal of corresponding crystal oscillator failure of oscillation when a certain crystal oscillator failure of oscillation.
3. a kind of method that realizes the two redundancies of crystal oscillator in flight control computer according to claim 1, it is characterized in that: the reseting module in described step (3) and (4) reset under powering-off state not DSP and all the other operational modules of FPGA, coordinate the clock after switching that flight control computer is resumed work again, shake while all working at twin crystal, reseting module is inoperative.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105138070A (en) * | 2015-09-25 | 2015-12-09 | 烽火通信科技股份有限公司 | Clock circuit for FPGA verification platform |
| CN107431479A (en) * | 2015-04-08 | 2017-12-01 | 美高森美半导体无限责任公司 | Digital phase-locked loop arrangement with master clock redundancy |
| CN109687866A (en) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | A kind of compensation device ensureing PLL output clock |
| CN110221650A (en) * | 2019-06-18 | 2019-09-10 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
| CN111614319A (en) * | 2020-04-29 | 2020-09-01 | 杭州拓深科技有限公司 | Combined crystal oscillator switching method suitable for humid environment |
| CN114860028A (en) * | 2022-03-29 | 2022-08-05 | 上海航天电子有限公司 | Programmable crystal oscillator real-time configuration and monitoring method for FPGA |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1713527A (en) * | 2004-06-24 | 2005-12-28 | 华为技术有限公司 | Crystal oscillation duplicaltion and its duplicating circuit |
| WO2009127848A2 (en) * | 2008-04-18 | 2009-10-22 | Elonics Limited | Clock distribution buffer |
| CN102411147A (en) * | 2011-12-22 | 2012-04-11 | 成都金本华科技有限公司 | Unidirectional time-service discipline system and method for Beidou-I satellite system |
| CN102946529A (en) * | 2012-10-19 | 2013-02-27 | 华中科技大学 | Image transmission and processing system based on FPGA (Field Programmable Gate Array) and multi-core DSP (Digital Signal Processor) |
-
2013
- 2013-06-06 CN CN201310224005.8A patent/CN103399808B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1713527A (en) * | 2004-06-24 | 2005-12-28 | 华为技术有限公司 | Crystal oscillation duplicaltion and its duplicating circuit |
| WO2009127848A2 (en) * | 2008-04-18 | 2009-10-22 | Elonics Limited | Clock distribution buffer |
| CN102411147A (en) * | 2011-12-22 | 2012-04-11 | 成都金本华科技有限公司 | Unidirectional time-service discipline system and method for Beidou-I satellite system |
| CN102946529A (en) * | 2012-10-19 | 2013-02-27 | 华中科技大学 | Image transmission and processing system based on FPGA (Field Programmable Gate Array) and multi-core DSP (Digital Signal Processor) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107431479A (en) * | 2015-04-08 | 2017-12-01 | 美高森美半导体无限责任公司 | Digital phase-locked loop arrangement with master clock redundancy |
| CN107431479B (en) * | 2015-04-08 | 2018-11-13 | 美高森美半导体无限责任公司 | Digital phase-locked loop arrangement with master clock redundancy |
| CN105138070A (en) * | 2015-09-25 | 2015-12-09 | 烽火通信科技股份有限公司 | Clock circuit for FPGA verification platform |
| CN105138070B (en) * | 2015-09-25 | 2017-12-08 | 烽火通信科技股份有限公司 | Clock circuit for FPGA verification platforms |
| CN109687866A (en) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | A kind of compensation device ensureing PLL output clock |
| CN110221650A (en) * | 2019-06-18 | 2019-09-10 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
| CN111614319A (en) * | 2020-04-29 | 2020-09-01 | 杭州拓深科技有限公司 | Combined crystal oscillator switching method suitable for humid environment |
| CN114860028A (en) * | 2022-03-29 | 2022-08-05 | 上海航天电子有限公司 | Programmable crystal oscillator real-time configuration and monitoring method for FPGA |
| CN114860028B (en) * | 2022-03-29 | 2024-06-11 | 上海航天电子有限公司 | Programmable crystal compaction time configuration and monitoring method for FPGA |
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