CN103399808B - A kind of method that realizes the two redundancies of crystal oscillator in flight control computer - Google Patents
A kind of method that realizes the two redundancies of crystal oscillator in flight control computer Download PDFInfo
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- CN103399808B CN103399808B CN201310224005.8A CN201310224005A CN103399808B CN 103399808 B CN103399808 B CN 103399808B CN 201310224005 A CN201310224005 A CN 201310224005A CN 103399808 B CN103399808 B CN 103399808B
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Abstract
A method that realizes the two redundancies of crystal oscillator in flight control computer, comprising: twin crystal shakes, FPGA, DSP; Two crystal oscillator clocks are sent into FPGA, and the mutual detection module of FPGA crystal oscillator clock completes the shake detection of clock frequency of twin crystal. All normal work if twin crystal shakes, two crystal oscillators provide clock signal to respectively DSP, FPGA. If when arbitrary crystal oscillator failure of oscillation, start clock handover module, another crystal oscillator provides clock to DSP and FPGA simultaneously, starts reseting module simultaneously, for DSP and FPGA provide reset signal. The present invention has realized the whether mutual detection of failure of oscillation of two crystal oscillator clocks. In the time of arbitrary crystal oscillator failure of oscillation, by clock handover module by single crystal oscillator simultaneously for DSP and FPGA provide reliable clock signal, the two redundancy design methods of whole crystal oscillator can effectively improve the reliability that flight control computer clock uses.
Description
Technical field
The present invention relates to a kind of method that realizes the two redundancies of crystal oscillator in flight control computer, be applicable to based onThe flight control computer clock High Reliability Design field of DSP and FPGA framework.
Background technology
Along with the development of the national defence information processing technology, a large amount of flight control computers has all adopted at presentThe embedded architecture of DSP+FPGA, and DSP and FPGA need to introduce crystal oscillator clock. Crystal oscillator isOne of the large Primary Component of on flight control computer three (DSP, FPGA and crystal oscillator) is also " the heart of each boardJump " generator. Current crystal oscillator (specially referring to active crystal oscillator) using method mainly contains two kinds: the one, and with twoIndividual crystal oscillator, sends into respectively DSP and FPGA. The 2nd, with a crystal oscillator, after being driven by clock driver,Send into respectively again DSP and FPGA.
Above-mentioned two kinds of crystal oscillator cut-in methods, have a common critical defect: if any road crystal oscillatorWhen failure of oscillation, DSP or FPGA will quit work, so formed by DSP+FPGA framework fly controlComputer cannot use, and the crystal oscillator failure of oscillation topmost failure mode that is crystal oscillator (inefficacy ratio up to80%), therefore above-mentioned two kinds of crystal oscillator cut-in methods, greatly reduce reliable that flight control computer clock usesProperty.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of and flown control meterIn calculation machine, realize the method for the two redundancies of crystal oscillator, while having realized any road crystal oscillator failure of oscillation, another road crystal oscillator withTime provide reliable and stable clock signal for DSP and FPGA, ensure what flight control computer clock usedHigh reliability.
Technical solution of the present invention is:
A kind of method that realizes the two redundancies of crystal oscillator in flight control computer comprises that step is as follows:
(1) by two crystal oscillator clock signal access FPGA, FPGA comprise the mutual detection module of crystal oscillator clock,Clock handover module and reseting module, utilize the mutual detection module of FPGA crystal oscillator clock to realize between twin crystal shakesFrequency detect mutually;
(2) all working properly if twin crystal shakes, FPGA will be wherein a road crystal oscillator access DSP beDSP provides clock signal, and another road crystal oscillator access FPGA provides clock signal for FPGA; IfThe unexpected failure of oscillation of crystal oscillator of access DSP enters step (3); If the unexpected failure of oscillation of crystal oscillator of access FPGAEnter step (4);
(3) the mutual detection module output alarm signal of FPGA crystal oscillator clock is to FPGA clock handover moduleCarry out the switching of clock signal, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access FPGAUse for supplying with DSP with the clock signal of failure of oscillation crystal oscillator same frequency, and by reseting module reset DSPWith all the other operational modules of FPGA, the clock signal that simultaneously accesses FPGA continues as FPGA to be providedClock;
(4) the mutual detection module output alarm signal of FPGA crystal oscillator clock is to FPGA clock handover moduleCarry out the switching of clock signal, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access DSP isSupply with FPGA with the clock signal of failure of oscillation crystal oscillator same frequency and use, and by reseting module reset DSPWith all the other operational modules of FPGA, the clock signal that simultaneously accesses DSP continues as DSP provides clock.
The described mutual detection module of FPGA crystal oscillator clock comprise frequency division module, two frequency discrimination modules,Warning discrimination module, frequency division module is low-frequency clock and high frequency clock signal by two crystal oscillator clock signal frequency divisions,In frequency discrimination module, high frequency clock is counted to realize two by make timing signal with low-frequency clockMutual detection between crystal oscillator. Warning discrimination module is according to frequency discrimination module result, at a certain crystal oscillator failure of oscillationTime export the alarm signal of corresponding crystal oscillator failure of oscillation.
Described reseting module under powering-off state not, reset DSP and all the other operational modules of FPGA, cooperation is cutClock after changing is resumed work flight control computer again, shakes while all normally working at twin crystal, and reseting module is notWork.
The present invention's beneficial effect is compared with prior art:
(1) the present invention does not introduce third party's clock, has realized the whether mutual detection of failure of oscillation of two crystal oscillator clocks,High efficiency and the convenience of system are improved;
(2), when any road crystal oscillator failure of oscillation, system completes clock automatically to be switched in real time, by another crystal oscillatorFor DSP and FPGA provide clock signal, improved the reliability that flight control computer clock uses simultaneously.
(3) the two redundancy design method highly versatiles of this crystal oscillator, do not increase device, and hardware cost is low, canLean on property high, be beneficial to and apply.
Brief description of the drawings
Fig. 1 is the two redundancy design method block diagrams of crystal oscillator that the present invention realizes;
Fig. 2 is the mutual detection module block diagram of crystal oscillator clock that the present invention realizes;
Fig. 3 is clock handover module and the reseting module block diagram that the present invention realizes.
Detailed description of the invention
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described in detail.
The invention provides a kind of method that realizes the two redundancies of crystal oscillator in flight control computer, realized arbitrarilyWhen one road crystal oscillator failure of oscillation, another road crystal oscillator is simultaneously for DSP and FPGA provide reliable and stable clock letterNumber, ensure the high reliability that flight control computer clock uses. As shown in Figure 1, the present invention mainly by belowModule composition: twin crystal shakes, FPGA, DSP, wherein FPGA comprise again the mutual detection module of crystal oscillator clock,Clock handover module, reseting module. Twin crystal shakes clock signal is sent into FPGA, utilizes FPGA crystal oscillatorThe mutual detection module of clock carries out the frequency that twin crystal shakes and detects mutually, all working properly if twin crystal shakes, FPGATwo-way crystal oscillator clock signal is offered respectively to FPGA and DSP, when the crystalline substance of access FPGA and DSPWhen any road failure of oscillation of center of percussion, the mutual detection module of FPGA crystal oscillator clock is cut output alarm signal to clockDie change piece, the crystal oscillator that clock handover module utilizes failure of oscillation is not simultaneously for FPGA and DSP provide clock letterNumber, all the other operational modules of FPGA are (except the mutual detection module of crystal oscillator, clock handover module, reset mould simultaneouslyAll the other operational modules outside piece) and DSP complete reset.
As shown in Figure 2, the mutual detection module of FPGA crystal oscillator clock comprises frequency division module, two frequencies differentiationsModule and warning discrimination module; Twin crystal shakes and clock signal is sent into frequency division module carries out clock division, is divided intoLow frequency and high-frequency signal (high-frequency signal and low frequency signal relation meet nyquist frequency sampling condition), soAfter in frequency discrimination module by low-frequency clock do timing numerical value that high frequency clock is counted to get withRelatively, it is right in comparator, to realize for theoretical value (numerical value that high-frequency signal value obtains divided by low frequency signal value)The whether judgement of failure of oscillation of crystal oscillator under high frequency clock; After powering on, low-frequency clock is counted simultaneously, in real time willThe numerical value counting to get and theoretical value (numerical value that high-frequency signal value obtains divided by low frequency signal value) compare,The whether judgement of failure of oscillation of crystal oscillator under comparator draws low-frequency clock. Differentiate in order to ensure crystal oscillator failure of oscillationAccuracy, sends the differentiation result of two frequency discrimination module outputs into warning discrimination module, only has crystal oscillatorFailure of oscillation is differentiated in situation about coming to the same thing, and could export the alarm signal of corresponding crystal oscillator failure of oscillation.
For the more precisely bright two redundancies of crystal oscillator that how to realize in flight control computer, with crystal oscillator 1 and crystalline substanceShake 2 (establishing the clock signal that crystal oscillator 1 exports is CLKA, and the clock signal that crystal oscillator 2 is exported is CLKB)For example is elaborated:
Twin crystal shakes and clock signal clk A, CLKB are sent into the mutual detection module of crystal oscillator clock carries out clock and divideFrequently, CLKA frequency division is CLKA1 and CLKA2, and CLKB frequency division is CLKB1 and CLKB2, itsThe frequency of middle CLKA1 is 2 times of above integral multiples of CLKB1, and the frequency of CLKB2 is CLKA22 times of above integral multiples (meeting nyquist frequency sampling condition), does timing by low-frequency clock and believesNumber high frequency clock is counted to realize the mutual detection of twin crystal between shaking, the mutual testing process of crystal oscillator clock asUnder:
For the clock CLKA1 after frequency division, CLKB1, sends into frequency discrimination module 1, utilizes counter 1To CLKA1 counting, count value is m1; CLKB1 sends into trigger 1 latching accumulator 1 currencyN1, the numerical value that n1 and pre-register p1(p1 value are obtained divided by CLKB1 for CLKA1) send intoComparator 2:n1=p1, illustrates that CLKA clock is normal, and the numerical value m1 that now removes counter 1 is heavyNew count, n1 < p1, illustrates that CLKA1 clock disappears, i.e. crystal oscillator 1 failure of oscillation; At comparator 1 by m1Value compares in real time with p1 value, works as m1 > p1, counter 1 numerical value is not removed in time, and CLKB1 is describedClock disappears, and this hour counter 1 stops counting, i.e. crystal oscillator 2 failure of oscillations.
In like manner, for clock CLKA2, CLKB2 after frequency division, send into frequency discrimination module 2, utilizeCounter 2 is to CLKB2 counting, and count value is m2, and CLKA2 sends into trigger 2 latching accumulators2 currency n2, obtain for CLKB2 n2 and pre-register p2(p2 value divided by CLKA2Numerical value) send into comparator 4, n2=p2, illustrate that CLKB2 clock is normal, now removes counter 2Numerical value m2 counts again, and n2 < p2 illustrates that CLKB2 clock disappears, i.e. crystal oscillator 2 failure of oscillations; ComparingDevice 3 compares m2 value and p2 value in real time, works as m2 > p2, counter 2 numerical value are not removed in time, sayBright CLKA2 clock disappears, and this hour counter 2 stops counting, i.e. crystal oscillator 1 failure of oscillation.
In the time that twin crystal shakes normal work, crystal oscillator 1 is sent clock signal to DSP is provided through FPGA, crystalline substanceShaking 2 provides clock signal to FPGA, now, and the output of the mutual detection module alarm free of crystal oscillator clock signal.
When frequency discrimination module 1 and frequency discrimination module 2 are measured crystal oscillator 1 failure of oscillation simultaneously, by with door 2,Warning discrimination module output alarm signal ALARM_S1 is 1, shows to access crystal oscillator 1 failure of oscillation of DSP.In the time that frequency discrimination module 1 and frequency discrimination module 2 are measured crystal oscillator 2 failure of oscillation simultaneously, by with door 1,Warning discrimination module output alarm signal ALARM_S2 is 1, shows that the crystal oscillator 2 that accesses FPGA stopsShake.
As shown in Figure 3, the alarm signal of the mutual detection module output of crystal oscillator clock offers clock handover module,FPGA clock handover module switches clock signal according to the alarm signal detecting, and clock switches toolBody process is as follows:
Design clock handover module 1 and clock handover module 2, in the time of ALARM_S1=1, show to connectCrystal oscillator 1 failure of oscillation that enters DSP, clock handover module 1 is worked, and the crystal oscillator 2 of access FPGA is exportedClock signal clk B be converted to CLKA ' through phaselocked loop (PLL) (frequency numerical value be equal to clock letterThe frequency numerical value of number CLKA), by CLKA ' through FPGA access DSP clock end for it,To replace CLKA clock. Due to now running status the unknown of DSP, therefore need the DSP that resets,Allow DSP again move program to RAM from FLASH, DSP program starts to carry out, and resets simultaneouslyAll the other operational modules of FPGA. In the time of ALARM_S2=1, show to access crystal oscillator 2 failure of oscillations of FPGA,Clock handover module 2 is worked, and the clock signal clk A that the crystal oscillator 1 of access DSP is exported is through phase-lockedRing (PLL) is converted to CLKB ' (frequency numerical value is equal to the frequency numerical value of CLKB), by CLKB 'Supply with FPGA internal clocking is provided, to replace CLKB clock. Due to the operation shape in FPGA nowState the unknown, all the other operational modules of FPGA that need to reset, DSP resets simultaneously.
As shown in Figure 3, the present invention has introduced reseting module, and CLKOUT1 provides clock for reseting moduleSignal, ALARM_S1 and ALARM_S2 process or door access reseting module, in the time that alarm free signal produces, reseting module is set to high level. In the time having alarm signal to produce, reseting module output certain widthLow level signal, in flight control computer do not reset under powering-off state DSP and all the other works of FPGA simultaneouslyDo module (as long as twin crystal any road that shakes goes wrong, all will reset simultaneously DSP and FPGA all the otherOperational module), again recover flight control computer work; Shake while all normally working at twin crystal, reseting moduleInoperative.
The present invention has utilized the built-in phaselocked loop of FPGA, therefore require the fpga chip selected at least inPut 2 phaselocked loops (PLL). Main flow FPGA is all built-in with 2 and above PLL at present.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (2)
1. a method that realizes the two redundancies of crystal oscillator in flight control computer, is characterized in that comprising stepAs follows:
(1) twin crystal the is shaken clock signal access FPGA of output, FPGA comprises that crystal oscillator clock examines mutuallySurvey module, clock handover module and reseting module, utilize the mutual detection module of FPGA crystal oscillator clock to realize twoThe frequency of crystal oscillator detects mutually;
(2) all working properly if twin crystal shakes, FPGA will be wherein a road crystal oscillator access DSP beDSP provides clock signal, and another road crystal oscillator access FPGA provides clock signal for FPGA; IfThe unexpected failure of oscillation of crystal oscillator of access DSP enters step (3); If the crystal oscillator of access FPGA stops suddenlyShake and enter step (4);
(3) the mutual detection module output alarm signal of FPGA crystal oscillator clock is to FPGA clock handover moduleCarry out the switching of clock signal, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access FPGAUse for supplying with DSP with the clock signal of failure of oscillation crystal oscillator same frequency, and reset by reseting moduleAll the other operational modules of DSP and FPGA, the clock signal that simultaneously accesses FPGA continues as FPGA and carriesFor clock;
(4) the mutual detection module output alarm signal of FPGA crystal oscillator clock is to FPGA clock handover moduleCarry out the switching of clock signal, clock signal phaselocked loop (PLL) frequency conversion in FPGA of access DSP isSupply with FPGA with the clock signal of failure of oscillation crystal oscillator same frequency and use, and by reseting module reset DSPWith all the other operational modules of FPGA, the clock signal that simultaneously accesses DSP continues as DSP provides clock;
The mutual detection module of FPGA crystal oscillator clock in step (1) comprises that frequency division module, two frequencies sentenceOther module and warning discrimination module, frequency division module is low-frequency clock and high frequency by two crystal oscillator clock signal frequency divisionsClock signal is counted high frequency clock by making timing signal with low-frequency clock in frequency discrimination moduleNumber is realized the mutual detection of twin crystal between shaking, and warning discrimination module is according to frequency discrimination module result, at certainWhen one crystal oscillator failure of oscillation, export the alarm signal of corresponding crystal oscillator failure of oscillation.
2. a kind of method that realizes the two redundancies of crystal oscillator in flight control computer according to claim 1,It is characterized in that: the DSP that resets under powering-off state not of the reseting module in described step (3) and (4)With all the other operational modules of FPGA, coordinate the clock after switching that flight control computer is resumed work again,Twin crystal shakes while all normally work, and reseting module is inoperative.
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| WO2016161504A1 (en) * | 2015-04-08 | 2016-10-13 | Microsemi Semiconductor Ulc | Digital phase locked loop arrangement with master clock redundancy |
| CN105138070B (en) * | 2015-09-25 | 2017-12-08 | 烽火通信科技股份有限公司 | Clock circuit for FPGA verification platforms |
| CN109687866A (en) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | A kind of compensation device ensureing PLL output clock |
| CN110221650B (en) * | 2019-06-18 | 2021-04-09 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
| CN111614319A (en) * | 2020-04-29 | 2020-09-01 | 杭州拓深科技有限公司 | Combined crystal oscillator switching method suitable for humid environment |
| CN114860028A (en) * | 2022-03-29 | 2022-08-05 | 上海航天电子有限公司 | Programmable crystal oscillator real-time configuration and monitoring method for FPGA |
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