CN109947226A - A kind of UART wake-up circuit of MCU chip - Google Patents
A kind of UART wake-up circuit of MCU chip Download PDFInfo
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- 230000001360 synchronised effect Effects 0.000 claims abstract description 16
- 238000001914 filtration Methods 0.000 claims description 9
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- 230000003111 delayed effect Effects 0.000 description 3
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Abstract
The invention discloses a kind of UART wake-up circuits of MCU chip, including clock opening module, signal filter module and wake up detection module, PAD is received outside the clock opening module connection UART, it includes register one, latch AND gate circuit, clock opening module is when receiving effective hopping edge, internal clocking and UART module clock are opened, to receive the information of PAD outside UART；Signal filter module is connect with clock opening module, it plays filter action to external PAD, signal filter module is when input signal is not useful signal, control signal is issued to clock opening module and it is allowed to close clock, there is synchronous circuit, delay circuit, filter circuit and interference indicator generation circuit inside signal filter module.The phenomenon that present invention can be realized fast wake-up under unclocked deep sleep mode, and will not lose any communication data, can customize wake-up matched data, and can prevent false wake-up.
Description
Technical field
The present invention relates to electronic circuit field, the UART wake-up circuit of specially a kind of MCU chip.
Background technique
UART communication module is the module on MCU chip basis.As MCU is in handheld device, internet of things equipment and wearable
Equipment using more and more extensive, be also more strong to low-power consumption demand.The low-power consumption mode of MCU chip is generally divided into sleep
Mode and deep sleep mode, sleep pattern simply turn off core clock, and peripheral clock can be opened, it is easy to realize that UART connects
It receives data to wake up, but does not close peripheral clock, power consumption is difficult to meet long-term sleep pattern, is much higher than deep sleep mould
Formula；Deep sleep mode ordinary circumstance can close all clocks other than low-speed clock, and power consumption is lower, using upper also urgent
A kind of wake-up mode is needed, specific data is sent to MCU to wake up the MCU in deep sleep mode by UART interface.By
Under deep sleep mode, clock can not be provided to UART module, it is therefore desirable to a kind of reliable UART wake-up circuit.
Summary of the invention
The purpose of the present invention is to provide a kind of UART wake-up circuits of MCU chip, to solve to mention in above-mentioned background technique
Out the problem of.
To achieve the above object, the invention provides the following technical scheme: a kind of UART wake-up circuit of MCU chip, including
Clock opening module, signal filter module and wake-up detection module, the outside clock opening module connection UART receive PAD,
It includes register one, latch AND gate circuit, clock opening module when receiving effective hopping edge, open internal clocking and
UART module clock, to receive the information of PAD outside UART, external PAD is sent directly into the clock end of register by gate circuit,
It realizes when external PAD becomes 0 from 1, forms a triggering and the output of register is allowed to become 1, reach the condition in not clock
Lower clock control enables to become 1 purpose, and another aspect exports clearing logic in register and realized in reset terminal, when next
Burr interferes, is obstructed out-of-date into deep sleep and wake-up correlation data, causes the reset of register, resets register, so that
Clock control is enabled to become 0；The latch of inside modules, clock is closed generation burr and is specifically added into order to prevent, at that time
When clock signal is low level, clock control signal could change；Signal filter module is connect with clock opening module, to outside
PAD plays filter action, and signal filter module issues control signal to clock and open mould when input signal is not useful signal
Block simultaneously allows it to close clock, inside signal filter module there is synchronous circuit, delay circuit, filter circuit and interference indicator to produce
Raw circuit, external PAD first pass around the synchronized sampling of two registers, and solving input PAD variation causes register metastable
Problem, the pad signal after synchronizing are sent into filter circuit, and filter circuit is first to carry out 1 bat time delayed signal with register and prolong
When before signal, it be all 0 output is just 0 that the two, which is all 1 just for 1, is believed then only 11 or 10 input can be filtered out
Number.After clock starting module opens clock control signal, delay a period of time removes signal of the detection after filtering, if
Or it is high level, then external PAD is interference signal；If it is low level, then being normal signal.Delay in the present invention
Since circuit realize a kind of delay opening clock control signal, directly adopt clock control signal as delay circuit
Reset terminal resets release trigger after clock control signal is opened.It is delayed after the specified clock cycle, judges filtered
Pad signal checks whether as interference signal.Interference indicator generation circuit is realized using a register, in specified delay
Between, when filtered signal, there is interference, register, which can lock, generates an interference indicator signal.
Preferably, it wakes up detection module to connect with signal filter module, wake-up detection module includes destination register and connect
Receive data register, wake up detection module and receive the external received information of PAD, and it is expected with inner setting wake up data into
Row comparison, receiving register sample in signal of the specific moment point to PAD external after filtering, obtain receiving number
According to and destination register carry out after comparing one by one, if compared by generating interrupt signal, otherwise generate it fails to match signal.
Preferably, it wakes up detection module and issues interruption to kernel when comparison passes through, while waking up clock and kernel, wake up
Detection module compare it is obstructed it is out-of-date will not wake up kernel, close clock and go successively to deep sleep mode.
Preferably, signal filter module is only greater than in significant level external pad signal after synchronous circuit synchronizes
The signal of 1 clock could pass through, and in addition after the specific delay of delay circuit, check the effective of filter circuit output level
Property.
Preferably, the clock end that detection module is directly connected to register one using external PAD input is waken up, register one
Output end is using opening internal clocking after latch.
Compared with prior art, the beneficial effects of the present invention are:
The present invention can be realized fast wake-up under unclocked deep sleep mode, and will not lose any communication data；It can
The phenomenon that waking up matched data with customization, and false wake-up can be prevented.
Detailed description of the invention
Fig. 1 is integrated circuit block diagram of the invention；
Fig. 2 is the circuit diagram of clock opening module of the present invention；
Fig. 3 is that signal filter module of the present invention implements figure；
Fig. 4 is that the present invention wakes up detection module implementation figure.
In figure: 1, clock opening module；101, register one；102, latch；2, signal filter module；201, electricity is synchronized
Road；202, delay circuit；203, alternative selector one；204, alternative selector two；205, register two；206, register
Three；207, register four；208, register five；3, detection module is waken up；301, destination register；302, data register is received
Device；303, alternative selector three.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 1-4 is please referred to, a kind of technical solution provided by the invention: a kind of UART wake-up circuit of MCU chip, including when
Clock opening module 1, signal filter module 2 and wake-up detection module 3, the clock opening module 1 are connected and are received outside UART
PAD comprising register 1,102 AND gate circuit of latch, clock opening module 1 are opened when receiving effective hopping edge
Internal clocking and UART module clock are opened, to receive the information of PAD outside UART；The signal filter module 2 is opened with clock
Module 1 connects, and plays filter action to external PAD, and signal filter module 2 is issued when input signal is not useful signal
Control signal is to clock opening module 1 and it is allowed to close clock, has synchronous circuit 201, delay electricity inside signal filter module 2
Road 202, filter circuit and interference indicator generation circuit.
It wakes up detection module 3 to connect with signal filter module 2, wakes up detection module 3 and include destination register 301 and receive
Data register 302 wakes up detection module 3 and receives the received information of external PAD, and it is expected to wake up data with inner setting
It compares.
It wakes up detection module 3 and issues interruption to kernel when comparison passes through, while waking up clock and kernel, wake up detection mould
Block 3 compare it is obstructed it is out-of-date will not wake up kernel, close clock and go successively to deep sleep mode.
Signal filter module 2 further includes alternative selector 1, alternative selector 2 204, register 2 205, posts
External pad signal is passed through synchronous circuit 201 by storage 3 206, register 4 207 and register 5 208, signal filter module 2
After synchronizing, it could only pass through in the signal that significant level is greater than 1 clock, in addition after the specific delay of delay circuit 202,
Check the validity of filter circuit output level.
Waking up detection module 3 further includes alternative selector 3 303, and it is direct using external PAD input to wake up detection module
Connect the clock end of register 1, the output end of register 1 is using opening internal clocking after latch.
Before entering deep sleep, need to open the enabled of UART deep sleep wake-up, configuration wakes up matched target
Data；Then, enabled into clock control after deep sleep mode, is closed, reach simulation clock module source and closes, so that
MCU internal clocking is all closed；Then, start to detect PAD outside UART, when the failing edge for receiving PAD outside UART, open
Clock control is enabled, to open internal clocking and UART module clock；Signal is received to external PAD and carries out low level detection,
Be still after filtering it is low level, be expressed as significant level, enter in next step, if filtering after be high level, be expressed as doing
Signal is disturbed, to be re-closing off internal clocking.
The data that detection module 3 receives external PAD are waken up, after the data receiver for waiting a whole frame, and ratio is waken up and matches
Target data compare, if match to kernel issue interrupt, wake up MCU；If mismatched, it is enabled to be re-closing off clock
With enter deep sleep mode.
Working principle: inside clock opening module 1, by one 101, latch 102 of a register and several doors
Circuit composition.External PAD by phase inverter be sent into register 1 clock end, realize when external PAD from 1 become 0 after formed
The D end data of register 1 is sent to output end Q by one clock, when the low-power consumption of UART wakes up enabled open, is posted
The D end signal of storage 1 is 1, and when PAD becomes 0 from 1, output end Q becomes 1；By enabling mutually or being sent into clock software
The end D of latch 102, when being enabled due to output clock control as low level, Clk signal 0, so clock system makes when output
When can be low level, the enabled EN of latch 102 be open, as long as or door output is high level, clock control is enabled
For high level.It fails to match, and signal, low-power consumption pulse signal and interference indicator signal pass through or behind the door, are directly connected to register one
101 reset terminal, reaching three has any one signal effective, and the output of register 1 can be made to become 0, when or door
After output is 0, the enabled EN of latch 102 negates for Clk, and only when Clk is 0, output signal clock control enables just meeting
Become 0, it is therefore prevented that clock generates burr when closing.
Inside signal filter module 2, generated by synchronous circuit 201, delay circuit 202, filter circuit and interference indicator
Circuit composition.External PAD first passes around the synchronized sampling of two registers in synchronous circuit 201, is sent into filter circuit, filtering
Circuit be first with register 2 205 carry out 1 bat time delayed signal and synchronous circuit 201 output signal, the two phase or and phase with；It posts
The output feedback of storage 3 206 arrives the selection end of alternative selector 1, when 3 206 output valve of register is 0, alternative
Selector 1 selection mutually with input, that is to say, that only when register 2 205 and 201 output signal of synchronous circuit are all 1
When, the output of register 3 206 can just be changed to 1, otherwise still remain 0；When 3 206 output valve of register is 1, alternative
Selector 1 selection mutually or input, that is to say, that only when register 2 205 and 201 output signal of synchronous circuit are all 0
When, register 3 206 can just be changed to 0, and otherwise register 3 206 or output are 1.Namely register 2 205 with it is synchronous
When both 201 output signals of circuit are different, the output of register 3 206 will not change, and achieve the effect that filtering with this.Delay electricity
Register in road 202 directlys adopt clock control signal as reset terminal, and when clock control signal is 0, register is located always
In reset, when clock control signal is 1, reset discharges.This embodiment delay of 4 bat clock cycle, discharges resetting
The delay of 4 bat clock cycle is needed afterwards, and it is 1 that delay circuit 202, which could export, and the output of delay circuit 202 is on the one hand by taking
Instead, another party plays a bat by register 4 207, and the two is sent into and door, and output one becomes 1 from clock control signal from 0
After moment point, delay 4 clap after pulse signal, the pulse duration be 1 clock cycle.It is that delay pulse is believed with door output
Number, and pad signal Xiang Yuhou after filtering, access the selection end of alternative selector 2 204；It indicates only to work as delay pulse
Pad signal after filtering is checked later, if pad signal is 1, the selection end of alternative selector 2 204 becomes 1, selects 1 ' b1
Input terminal, after clock has come, the output of register 5 208 becomes 1, after register 5 208 becomes 1, when next
Even if the end that selects of clock alternative selector 2 204 is 0, the end the D selection output end Q of register 5 208, so register five
208 value can be always maintained at 1, generate interference indicator signal.
It is waking up inside matching module 3, is being made of destination register 301 and reception data register 302, receiving data and post
Storage 302 be UART Bit0 receiving register, use bit counter BitCnt be equal to 0 and baud rate calculator BRCnt for
0.5BR carries out Xiang Yuhou, is sent into the selection end of alternative selector 3 303, only when being both 1, opens alternative choosing
It selects device and selects filtered pad signal, the pad signal after receiving 302 sampling filter of data register.That is, receiving number
According to register 302 in bit counter BitCnt it is 0 and in the middle position of a UART ETU, filtered PAD is believed
Number just sample, obtain 0 data of received bit, and destination register 301 houses desired 0 data of position, the two be sent into XOR gate into
Row compare in place 0 as a result, similarly in place 1, position 2 etc. is as a result, each result progress phase or, if none of
Difference, output wake-up signal are 1, and it fails to match, and signal is 0.If there is 1 signal difference, exporting wake-up signal is 0, and matching is lost
Lose signal be 1, reach only with destination register all it is identical just generate interrupt signal.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (5)
1. a kind of UART wake-up circuit of MCU chip, which is characterized in that including clock opening module, signal filter module and call out
Awake detection module, the outside clock opening module connection UART receive PAD comprising register one, latch AND gate circuit,
Clock opening module opens internal clocking and UART module clock when receiving effective hopping edge, to receive PAD outside UART
Information；The signal filter module is connect with clock opening module, plays filter action to external PAD, signal filters mould
Block issues control signal to clock opening module and it is allowed to close clock, signal filtering when input signal is not useful signal
Inside modules have synchronous circuit, delay circuit, filter circuit and interference indicator generation circuit.
2. a kind of UART wake-up circuit of MCU chip according to claim 1, it is characterised in that: the wake-up detects mould
Block is connect with signal filter module, is waken up detection module and is included destination register and receive data register, wakes up detection module
The received information of external PAD is received, and it is expected that waking up data compares with inner setting.
3. a kind of UART wake-up circuit of MCU chip according to claim 1, it is characterised in that: the wake-up detects mould
Block is issued to kernel when comparison passes through and is interrupted, while waking up clock and kernel, wake up detection module compare it is obstructed it is out-of-date not
Kernel can be waken up, clock is closed and goes successively to deep sleep mode.
4. a kind of UART wake-up circuit of MCU chip according to claim 1, it is characterised in that: the signal filters mould
Block after synchronous circuit synchronizes, only could pass through external pad signal in the signal that significant level is greater than 1 clock, separately
After the specific delay of external delay circuit, the validity of filter circuit output level is checked.
5. a kind of UART wake-up circuit of MCU chip according to claim 1, it is characterised in that: the wake-up detects mould
Block is directly connected to the clock end of register one using external PAD input, and the output end of register one after latch using opening
Internal clocking.
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| CN201910266833.5A CN109947226A (en) | 2019-04-03 | 2019-04-03 | A kind of UART wake-up circuit of MCU chip |
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| CN201910266833.5A CN109947226A (en) | 2019-04-03 | 2019-04-03 | A kind of UART wake-up circuit of MCU chip |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111198776A (en) * | 2019-12-25 | 2020-05-26 | 上海亮牛半导体科技有限公司 | Method for preventing UART (universal asynchronous receiver/transmitter) from receiving lost data during deep sleep of MCU (microprogrammed control unit) |
| CN112306214A (en) * | 2019-07-31 | 2021-02-02 | 上海贝岭股份有限公司 | Chip wake-up circuit, control method thereof and chip |
| CN114328351A (en) * | 2021-12-23 | 2022-04-12 | 西安芯海微电子科技有限公司 | MCU wake-up circuit, method and electronic equipment |
| CN114448403A (en) * | 2020-11-05 | 2022-05-06 | 中移物联网有限公司 | Asynchronous wake-up circuit |
| CN115686635A (en) * | 2023-01-03 | 2023-02-03 | 杭州米芯微电子有限公司 | MCU structure without clock circuit and corresponding electronic equipment |
| CN111198776B (en) * | 2019-12-25 | 2024-06-07 | 上海亮牛半导体科技有限公司 | Method for preventing UART (universal asynchronous receiver/transmitter) from receiving lost data during deep sleep period of MCU (micro controller Unit) |
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Application publication date: 20190628 |