CN103226169B

CN103226169B - Square wave detector for wireless wake-up circuit

Info

Publication number: CN103226169B
Application number: CN201210191098.4A
Authority: CN
Inventors: 何文涛; 葛亮; 甘业兵; 钱敏; 马成炎
Original assignee: Individual
Current assignee: HANGZHOU ZHONGKE MICROELECTRONICS CO Ltd
Priority date: 2012-06-12
Filing date: 2012-06-12
Publication date: 2015-07-08
Anticipated expiration: 2032-06-12
Also published as: CN103226169A

Abstract

The invention provides a square wave detector for a wireless wake-up circuit. The frequency of the square wave detector can be configured within the range of 10-200 kHz. The square wave detector comprises a signal acquisition circuit and a square wave detection circuit, wherein the square wave detection circuit comprises a jitter detection module path, a frequency detection module path, a relevant detection module path and an AND circuit which are used for respectively detecting the duty factor, the frequency and the relevance of an input sampling signal; and when outputs of the three detection module paths are high levels respectively, the output of the AND circuit is also high level and the square wave detection circuit outputs a wake-up signal. By detecting the jitter, the frequency and the relevance of the input sampling signal, the accurate judgment and clutter reduction are realized, the mistaken wake-up probability is effectively reduced, the wake-up probability is increased and the wake-up time is remarkably shortened, thereby increasing the work efficiency of a wake-up receiver and reducing the power consumption of the system. The square wave detector provided by the invention is suitable for wake-up receiving circuits of an RFID (Radio Frequency Identification) system and an ETC (Electronic Toll Collection) system.

Description

A kind of square wave detector for wireless awakening circuit

Technical field

The invention belongs to radio frequency electric technical field, what relate to radio frequency discrimination RFID system wakes receiving circuit up, particularly relate to a kind of square wave detector for wireless awakening circuit, be applicable to active RFID system and electric non-stop toll ETC system, effectively improve the work efficiency waking receiver up.

Background technology

In recent years, radio-frequency (RF) identification (RFID) technical development is swift and violent, and rfid system is primarily of radio-frequency identification reader (reader) and radio-frequency (RF) tag (tag) composition.Whether rfid system has built-in power according to radio-frequency (RF) tag, is divided into active RFID system and passive RFID system two class.The label of active RFID system, with built-in power, has the advantage such as high reliability, telecommunication, therefore, gains great popularity in recent years.But because radio-frequency (RF) tag relies on powered battery, power consumption decides the mission life of radio-frequency (RF) tag.So, low-power consumption and the energy-conservation major issue being active RFID system and paying close attention to the most.

Video tab adds and wakes receiving circuit up, effectively can reduce power consumption.Waking ultimate principle up is: wake the high-frequency signal of receiver up after ovennodulation, send into RF envelope detecting device (RFED) in sheet and carry out rectification, obtain modulation signal envelope, signal envelope amplifies through operational amplifier, the signal be exaggerated is sent into comparer and is compared, and is driven into logic level, obtains the square-wave signal of demodulation, adjudicated by the logical square-wave signal of frequency discriminator to demodulation of band again, determine whether effective wake-up signal.If the square-wave signal frequency of this demodulation is positioned within the frequency range of setting, be judged to be effective wake-up signal, send into the interrupt waking receiver MCU up and interrupt.

But the signal that receiver receives if wake up is not effective radiofrequency signal, but mixed and disorderly waveform, late-class circuit also may have signal and produce, and this time will produce false wake-up.Square wave detector is then be added in wake receiver rear end up, mainly by the problem solving false wake-up.Input signal, through the laggard row detection of over-sampling, judges that whether NkHz (such as 14kHz) square wave is correct, if so, then exports high level, drive late-class circuit work, if input has problem, then do not wake up.Thus realization condition wakes the object energy-conservation with low-power consumption up.

The patent No. 200820141876.8 of prior art, name is called the patent of " detection device for dimension variable accidental resonance square wave ", build peripheral circuit by modulus (AD) conversion chip and digital signal processing (DSP) chip to complete square wave and detect, this prior art exists and utilizes peripheral circuit to add the defect of the poor reliability of circuit cost and circuit.

The patent No. 200810151278.3 of prior art, name is called " system for detecting cascade programmed control frequency accidental resonance square wave ", and this invention is the design based on printed circuit board (PCB) (PCB), there is peripheral circuit complex structure and the high defect of false wake-up probability.

The patent No. 01144557.2 of prior art, name is called " synchronization signal detection circuit device and this device thereof detect the detection method of synchronizing signal ", and it is too single that this invention exists detection method structure, the defect that false wake-up probability is high.

Summary of the invention

The object of the invention is to overcome the problems such as the design cost of printed circuit board (PCB) level that prior art exists is high, peripheral circuit complex structure, false wake-up probability are high, NkHz(such as 14K to waking receiver in RFID up and exporting) square wave distinguishes process, that improves correct signal wakes probability up, reduce the probability that rub-out signal produces false wake-up, and reduce wakeup time.

The object of the invention is to be achieved through the following technical solutions:

For a square wave detector for wireless awakening circuit, it is, square wave detector comprises:

A signal sample circuit, sample frequency is M times of input signal NkHz, and the span of N is 10 ~ 200, is determined by the system at wireless awakening circuit place; By sample frequency be MNkHz square wave to input NkHz intermediate-freuqncy signal sample, the span of M is 4,8,16;

N value sets according to the IF signal frequency of Upper system, and usual electric non-stop toll ETC system N value is 14, and active RFID system N value is 156.Realize the configuration of square wave detector to detection signal frequency N kHz, the configuration scope detecting frequency N kHz is 10 ~ 200KHz, and completing detection signal frequency is best configuration, and the wakeup time of wake-up circuit is reduced.Sample frequency is by completing configuration to digital oscillator local oscillation signal M frequency multiplication, and the span of M is 4,8,16, is 8 as preferably getting M value.Such as N is 14, M is 8, input intermediate-freuqncy signal 14kHz, samples by the 14kHz intermediate-freuqncy signal of square wave to input of 112kHz.

A square wave testing circuit has shaking detection module path, frequency detection module path and correlation detection module path, the output terminal of the input end of three detection module paths of square wave testing circuit all connection signal sample circuit, for the correction judgement of the dutycycle to input sample signal, frequency and correlativity; Square wave testing circuit also has AND circuit, and the output signal of AND circuit to three detection module paths judges, for exporting wake-up signal when being judged as correct;

Signal sample circuit is a kind of sampling hold circuit, the intermediate-freuqncy signal output terminal of its outer wireless awakening circuit of input end brace, the output terminal of signal sample circuit connects the input end of square wave testing circuit, the wake-up signal end of the outer wireless awakening circuit of output terminal brace of square wave testing circuit.

Described square wave detector, it is that the shaking detection of described square wave testing circuit, frequency detecting and correlation detection three module paths and AND circuit are integrated in same chip, consists of:

A shaking detection module path comprises a shaking detection module, for detecting the dutycycle of input signal;

A frequency detection module path comprises a frequency detection module, for detecting the frequency of input signal;

A correlation detection module path comprises a correlation detection module, for detecting the phase correlation of input signal;

The AND circuit of one three input, for exporting wake-up signal;

The signal output part of the input end difference connection signal sample circuit of shaking detection module, frequency detection module and correlation detection module, shaking detection module, frequency detection module and the output terminal of correlation detection module are connected an input end of the AND circuit of one three input respectively, for realizing high level phase and and exporting the correct wake-up signal of high level.

Described square wave detector, it is that described correlation detection module path comprises sampling hold circuit, digital oscillator, a pair digital mixer, a pair anomalous integral summation circuit, envelope detected circuit and the first comparator circuit; A pair digital mixer and a pair anomalous integral summation circuit form computing cross-correlation device circuit; The output terminal of sampling hold circuit is connected with the input end of a pair digital mixer respectively, the signal end of a pair digital mixer is connected with digital oscillator output terminal respectively, the signal end of a pair digital mixer is connected with digital oscillator output terminal respectively, and the output terminal of a pair digital mixer is connected with the input end of corresponding first integrator with second integral device respectively; The output terminal of first integrator connects the input end of the first totalizer, and the output terminal of second integral connects the input end of the second totalizer; The output terminal of the first totalizer and the output terminal of the second totalizer are corresponding to be respectively connected with an input end of envelope detected circuit, for the mean value of comprehensive detection input signal dutycycle and frequency; The output terminal of envelope detected circuit is connected with the input end of the first comparator circuit, and the output terminal of the first comparer connects an input end of AND circuit.

Correlation detection module be based on sampled signal and the local oscillation signal of pair of orthogonal do phase place relevant after, envelope detected circuit is sent to make envelope detected again, for the root mean square process of two-way accumulator output signal, detect the mean value of input signal dutycycle and frequency, thus realize the correlation detection of comprehensive input sample signal.

Described square wave detector, it is that described frequency detection module path comprises sampling hold circuit, and the frequency detection module be made up of an edge sense circuit and the second comparator circuit; Frequency detection module is the structure adopting Digital Analog Hybrid Circuits, the input end of edge sense circuit connects sampling hold circuit, the output terminal of edge sense circuit connects an input end of the second comparator circuit, another input end of second comparator circuit accesses the second amplitude threshold settings, and the output terminal of the second comparator circuit connects an input end of AND circuit; Frequency detection module adopts Digital Analog Hybrid Circuits structure, frequency detection module with a register, for arranging the amplitude threshold of the second comparer; Wherein:

Described edge sense circuit comprises the peak detection circuit, third integral device and the 3rd totalizer that connect successively; Related peak detecting circuit is a kind of amplitude detection circuit, its input end connects the output terminal of the sampling hold circuit of square wave detector, the output terminal of peak detection circuit is connected with the input end of third integral device, third integral device band integration holding circuit, third integral device output terminal is connected with the input end of the 3rd totalizer, the output terminal of the 3rd totalizer connects an input end of the second comparator circuit, for detecting the frequency of input sample signal; The reference signal termination of the second comparator circuit enters the second amplitude threshold settings; The reset terminal of reset signal access third integral device, the 3rd totalizer and the second comparator circuit or clear terminal; Frequency detection module, for detecting the frequency of input signal, by detecting the number of the hopping edge of sampled signal, realizes the frequency detecting to input sample signal.

The detection window number of the peak detection circuit of frequency detection module is configurable, and Systematical control SPI interface is connected to window number and arranges end, and detection window number is configured by settings k; The settings k of detection window number is arranged by Systematical control SPI interface; Hopping edge number >=2k-permissible variation value that frequency detection module detects by judging k detection window, judges the correct of the frequency dutycycle of input signal, realizes the detection to frequency input signal.

Described square wave detector, it is that described shaking detection module and frequency detection module merge and forms shake and frequency detection module; Shake and frequency detection module comprise the shaking detection circuit be made up of dither signal detection circuit and reset signal generating circuit, the edge sense circuit be made up of the related peak detecting circuit connected successively, third integral device and the 3rd totalizer, and the second comparator circuit; Wherein:

Described dither signal detection circuit is made up of the related peak detecting circuit connected successively, the 4th integrator and the 4th totalizer; The output terminal of sampling hold circuit is connected with dither signal detection circuit input end, dither signal detection circuit is connected with reset signal generating circuit input end by output terminal, an input end of the second comparator circuit that the output terminal rate of connections detection module of reset signal generating circuit leads to; Connect reset terminal or clear terminal that reset signal that reset signal generating circuit exports accesses the anomalous integral summation circuit in the reset terminal of the envelope detected circuit in correlation detection module and frequency detection module respectively;

Described related peak detecting circuit is a kind of amplitude detection circuit, its input end connects the output terminal of the sampling hold circuit of square wave detector, the output terminal of related peak detecting circuit is connected with the input end of third integral device, third integral device band integration holding circuit, integration holding circuit output terminal is connected with the input end of the 3rd totalizer, the output terminal of the 3rd totalizer connects an input end of the second comparator circuit, for detecting the frequency of input sample signal; The reference signal termination of the second comparator circuit enters the second amplitude threshold settings; The reset terminal of reset signal access third integral device, the 3rd totalizer and the second comparator circuit or clear terminal; Frequency detection module, for detecting the frequency of input signal, by detecting the number of the hopping edge of sampled signal, realizes the frequency detecting to input sample signal.

Shake and frequency detection module are for detecting sampled signal dutycycle, whether respectively M/2 sampled point is contained by detection sampled signal high level and low level, thus whether the dutycycle judging input signal is 50%, realize the detection to the dutycycle of input sample signal, judge that whether the frequency dutycycle of input signal is correct.

Described square wave detector, it is that described correlation detection module, frequency detection module and shaking detection module also comprise a register separately: be the first register, the second register and the 3rd register respectively; The data input pin correspondence of three registers connects three fields of the register control word of Upper system: wherein:

The data input pin of described first register connects the first field of the register control word of Upper system, for the initial value of configure amplitude threshold T H_MAG, the data output end of the first register connects the first comparator circuit reference signal end, provides the first amplitude threshold settings;

The data input pin of described second register connects the second field of the register control word of Upper system, for the initial value of configuration frequency comparison threshold value TH_FREQ, the data output end of the second register connects the second comparator circuit reference signal end, provides the second amplitude threshold settings;

The data input pin of described 3rd register connects the 3rd field of the register control word of Upper system, for configuring the initial value of shake comparison threshold value TH_ JITTER, the data output end of the 3rd register connects the 3rd comparator circuit reference signal end, provides shake comparison threshold settings.

Described square wave detector, it is that described shaking detection module path comprises sampling hold circuit and shaking detection module;

Shaking detection module comprises dither signal detection circuit and reset signal generating circuit; Dither signal detection circuit is made up of, for detecting the dutycycle of input sample signal the related peak detecting circuit connected successively, the 4th integrator and the 4th totalizer; The output terminal of sampling hold circuit is connected with dither signal detection circuit input end, dither signal detection circuit is connected with reset signal generating circuit input end by output terminal, and the output terminal of the reset signal generating circuit of shaking detection module directly connects an input end of the AND circuit of square wave detector; The reset signal that reset signal generating circuit exports accesses reset terminal or the clear terminal of the anomalous integral summation circuit in the reset terminal of the envelope detected circuit in correlation detection module and frequency detection module respectively.

Described square wave detector, it is that described shake and frequency detection module also comprise the second register and the 3rd register, wherein:

Shown by the test result of the emulation experiment of the square wave detector to 14kHz IF input signals, the wakeup time of square wave detector is 640us ~ 850us, is better than the wakeup time of existing wake-up circuit.

Described square wave detector, it is the wake-up signal end of the wireless transceiver circuit of the output terminal connecting band wireless awakening circuit of described square wave detector; For in frequency detection module, the output terminal of shaking detection module and correlation detection module is all high level, when the AND circuit output terminal of square wave detector is high level, exports the wake-up signal of high level, realizes waking up wireless transceiver circuit.

Described square wave detector, it is also the signal sample circuit of described square wave detector, and the correlation detection module of square wave testing circuit, shaking detection module and frequency detection module, or above-mentioned shaking detection module and frequency detection module merge the shake and frequency detection module that form, and AND circuit, adopt CMOS technology to be integrated in a chip, chip-scale circuit is based on Digital Analog Hybrid Circuits structure; Adopt Digital Analog Hybrid Circuits structure high for the reliability improving square wave detector, thus meet the high reliability request of wireless awakening circuit;

The first totalizer in described chip, the second totalizer form identical with the circuit of the 3rd totalizer, all comprise three delay circuits and a totalizer, a totalizer is time diversity totalizer, time diversity number of times is 3, range signal diversity for being completed the testing result of three sense cycle by two-stage delay circuit is added up, and the output wake-up signal of a sense cycle and clearing or reset, significantly improve and wake probability up, reduce false wake-up probability.

Local oscillator square-wave cycle is respective settings with input IF signal frequency, detection window number k is directly related with the delay time of the delay circuit of totalizer again, time diversity number of times is 3, arrange detection window number k value be 6,9,12,15(k is the multiple of 3), one detection period is k/3 local oscillator square-wave cycle.If arranging k value is 9, one detection period is 3 local oscillator square-wave cycle; If k is 12, then one detection period is 4 local square-wave cycle; The delay circuit of totalizer is configurable delay circuit, and the delay time of digital delay circuit is synchronized with the setting of local oscillator square-wave cycle, and corresponding adjustment delay time is one detection period;

Shaking detection circuit detects the distortion of input intermediate-freuqncy signal fast in one detection period, when there is larger distortion in input signal, the deviate of the high level number of transitions that shaking detection circuit detects in one detection period is greater than permissible value, output jitter reset signal immediately, totalizer intermission diversity is added up, re-execute and newly once wake detection up, be beneficial to effectively shorten wakeup time.

For N=14, the sampled output signal that input signal 14kHz samples through 112kHz local oscillator and keeps, enters three detection module paths respectively:

Shaking detection module, for detecting the dutycycle of input signal, for the sampled signal of 112kHz, in input signal a kind of cycle, high level and low level respectively should have four sampled points, if deviation is excessive, then think that signal is not correct input signal, produce shake (Jitter) and reset;

Frequency detection module, for detecting the frequency of input signal, whether the hopping edge signal detected according to 9 detection windows is 18 judge that whether the frequency of input signal is correct;

Correlation detection module, for the correlativity of comprehensive detection signal, actual is amplitude detection to input signal dutycycle, and it is different from shaking detection, and amplitude detection is the amplitude average value for whole detection window;

Only have each detection module testing result to meet the demands, this circuit just can export high level, drives late-class circuit work.

The present invention can reduce the false wake-up probability waking receiver up effectively, improves and wakes probability up, reduces wakeup time, thus raising wakes efficiency up, reduces the useless power consumption of false wake-up, reduces system power dissipation.

Substantial effect of the present invention:

1, the present invention uses correlation detection to come comprehensive detection dutycycle and frequency, improves the false wake-up probability of detection.

2, frequency detecting being combined by processing with door with shaking detection, correlation detection, improve the accuracy of detection, reduce the probability of false wake-up.

3 adopt correlativity, shake and frequency three detection module paths to realize the process of sampled signal comprehensive detection, and treatment effect is optimized, and saves the processing time, improves and wake efficiency up, shorten wakeup time.

4, the module of square wave detector of the present invention and circuit are integrated in same chip, without peripheral circuit, based on Digital Analog Hybrid Circuits on chip, meet the high reliability of wireless awakening circuit and the requirement of low-power consumption.

Accompanying drawing explanation

Fig. 1 is the schematic block circuit diagram waking receiver in the system of the electronic charging system without parking ETC of 5.8GHz up;

In Fig. 1: 11-wake receiver up, 12-square wave detector.

Fig. 2 is the circuit principle of compositionality block diagram of square wave detector in RFID wireless awakening circuit;

In Fig. 2: 21-sample circuit, 22-square wave testing circuit, 221-shaking detection module, 222-frequency detection module, 223-correlation detection module, 224-AND circuit.

Fig. 3 a is the structured flowchart of the first embodiment of the invention 14kHz square wave testing circuit be applied in ETC system;

In Fig. 3 a: 3a-square wave testing circuit, 31-sample circuit, 32-in pass property detection module, 321-correlation detection circuit, 322-envelope detected circuit, 323-the first comparator circuit, 33-shaking detection module, 34-AND circuit, 35-frequency detection module, 351-edge sense circuit, 352-the second comparator circuit, the intermediate-freuqncy signal of 301-input, the clock signal of 302-input, the power-on reset signal of 303-input, the reset signal of 304-input, 305-register control word, first amplitude threshold settings of 306-input, second amplitude threshold settings of 307-input, the wake-up signal of 308-output.

Fig. 3 b is the structured flowchart of the second embodiment of the invention 14kHz square wave testing circuit be applied in ETC system;

In Fig. 3 b: 36-shake and frequency detection module.

Fig. 4 is that correlation detection modular circuit forms block diagram;

In Fig. 4: 41-correlation calculating circuit, 411,412-related operation frequency mixer, 413-numerically-controlled oscillator, 42,43-anomalous integral summation circuit, 421-first integrator, 431-second integral device, the 422-the first totalizer, the 432-the second totalizer, 322-envelope detected circuit, 323-the first comparator circuit, 34-AND circuit.

Fig. 5 is that frequency detection module circuit of the present invention forms block diagram;

In Fig. 5: 362-edge sense circuit, 51-related peak detecting circuit, 52-third integral device, the 53-the three totalizer.

Fig. 6 a is that a kind of shaking detection modular circuit of first embodiment of the invention square wave testing circuit forms block diagram;

Fig. 6 b is the formation block diagram of a kind of shaking detection circuit in the shake of second embodiment of the invention square wave testing circuit and frequency detection module;

In Fig. 6 a and Fig. 6 b: 61-dither signal detection circuit, 611-related peak detecting circuit, 612-anomalous integral totalizer, 613-shake comparer, 62-reset signal generating circuit.

Fig. 7 is that embodiment of the present invention square wave detector on-chip circuit forms block diagram;

In Fig. 7: 71-sample circuit, 72-correlation detection module, 720-digital oscillator, 721,722-related operation frequency mixer, 723-first integrator, 724-second integral device, 725-the first totalizer, 726-the second totalizer, 727-envelope detected circuit, the 728-the first comparator circuit, 73-shake and frequency detection module, 731-shaking detection circuit, 732-peak detection circuit, 733-third integral device, 734-the three totalizer, 735-the second comparator circuit, 74-AND circuit, 741-holding circuit.

Embodiment

Fig. 1 provides the schematic block circuit diagram waking receiver in the ETC electronic charging system without parking of 5.8GHz up, and the wake-up signal waking receiver 11 up is provided by a square wave detector 12.The output terminal of square wave detector as the output terminal of the enable signal waken up connect wake receiver up wake input end up, when the vehicle with ETC electronics message accounting do not stop normally sail into time, square wave detector exports a wake-up signal to ETC chip, realization wakes ETC(electronic charging system without parking up) chip operation object, from vehicle ETC chip, withhold expense for charge station ETC electronics message accounting.But the defects such as the square wave detector of prior art exists peripheral circuit complex structure and measuring ability is single, cause the false wake-up probability that detects higher, wakeup time is longer, wakes efficiency up lower, and direct impact efficiently wakes the realization of the energy-conservation object with low-power consumption up.

Below in conjunction with drawings and Examples, technical scheme of the present invention is described further.

Fig. 2 is the three module paths formation block diagrams of the present invention for a kind of embodiment of the square wave detector of RFID wireless awakening circuit, and as shown in Figure 2, the circuit of square wave testing circuit forms block diagram and comprises the sample circuit 21 and square wave testing circuit 22 that are connected in series.Square wave testing circuit 22 comprises shaking detection module 221, frequency detection module 222 and correlation detection module 223 and AND circuit 224, and the input end of shaking detection module 221, frequency detection module 222 and correlation detection module 223 is connected in parallel the output terminal of sample circuit 21.Shaking detection module 221, frequency detection module 222 and the output terminal of correlation detection module 223 are connected an input end of AND circuit 224 respectively.Shaking detection module 221, frequency detection module 222 and correlation detection module 223 form shaking detection module path, frequency detection module path and correlation detection module path respectively with sample circuit 21.The input end access intermediate-freuqncy signal of sample circuit 21, the output terminal of gate circuit 224 exports wake-up signal.

First embodiment

Fig. 3 a provides the structured flowchart that the first embodiment of the invention N be applied in ETC system is the 14kHz square wave detector of 14, as shown in Figure 3 a: square wave detector 3a comprises sample circuit 31, correlation detection mould 32, shaking detection module 33, frequency detection module 35 and AND circuit 34.Correlation detection module 32 comprises the correlation detection circuit 321 be sequentially connected in series, envelope detected circuit 322 and the first comparator circuit 323.Frequency detection module 35 comprises edge sense circuit 351, and the second comparator circuit 352.Shaking detection module 33 output terminal is connected an input end of AND circuit respectively with the output terminal of the second comparator circuit 352 of frequency detection module 35, the output terminal of the first comparator circuit 323 of correlation detection module 32 also connects an input end of AND circuit 34, and what the output terminal of AND circuit 34 transferred out that wake-up signal 307 delivers to radio-frequency (RF) identification (RFID) system wakes receiving circuit up.The shake reset signal that shaking detection module 33 exports is connected to the reset terminal of the envelope detected circuit 322 of correlation detection module 32 and the reset terminal of edge sense circuit 332 simultaneously.The intermediate-freuqncy signal 301 of input accesses the input end of sample circuit 31, the output terminal of sample circuit 31 connects the input end of the correlation detection circuit 321 shaking detection module 33 of square wave testing circuit and the edge sense circuit 351 of frequency detection module 35, and the clock signal 302 of input is as the reference clock signal of square wave detector 3a.Power-on reset signal 303 RSTN of system input, controls the reset of sample circuit 31, correlation detection mould 32, shaking detection module 33 and frequency detection module 35, for square wave detector provides the start-up time after reset.When the reset signal CLEAR 304 of system input is added to square wave detector, then the register of Systematical control square wave detector resets.Simultaneity factor input register control word SETTING, the register control word 305 " SETTING " of 18 bit wides arranges initial value to three registers in correlation detection module 32, frequency detection module 35 and shaking detection module.First amplitude threshold settings TH_MAG 306 of the first register accesses the reference value input end of the first comparator circuit 323 of correlation detection mould 32, the output terminal of envelope detected circuit 322 connects the signal value input end of the first comparator circuit 323, the comparative result that the first comparator circuit 323 exports.Second amplitude threshold settings 307 of the second register access the reference value input end of the second comparator circuit 333 of frequency detection module 36; The shake thresholding settings TH_JITTER that 3rd register exports accesses the shaking detection comparator reference end of shaking detection module 33, for after determine whether to control reset signal generating circuit whether output jitter reset signal.The output terminal of edge sense circuit 351 and the output terminal of shaking detection module 33, connect a signal input part of the second comparator circuit 352 respectively, the second comparator circuit 352 exports comparative result.Intermediate-freuqncy signal IFDATA 301 accesses the input end of sampling hold circuit 31, and the output terminal Jing San Road of sampling hold circuit 31 is connected with the input end of correlation detection module 32 path, shaking detection module 33 path, frequency detection module 35 path respectively.The comparative result that first comparator circuit 323 exports and the comparative result that the second comparator circuit 352 exports are added to an input end of AND circuit 34 respectively.When the comparative result that comparative result and second comparator circuit 352 of the first comparator circuit 323 output export and the shake reset signal that shaking detection module 33 exports are all high level, AND circuit 34 exports the wake-up signal " WAKEUP " 308 of a high level.Otherwise AND circuit 34 exports as low level, does not export wake-up signal.

Second embodiment

The structured flowchart of Fig. 3 b to be the second embodiment of the invention N be applied in ETC system be 14kHz square wave detector of 14.As shown in Figure 3 b: square wave detector comprises sample circuit 31, correlation detection mould 32, the shake of being combined by shaking detection circuit and frequency detection circuit and frequency detection module 36, and AND circuit 34.Correlation detection module 32 comprises the correlation detection circuit 321 be sequentially connected in series, envelope detected circuit 322 and the first comparator circuit 323.Shaking detection module and frequency detection module are combined as a shake and frequency detection module 36, and it comprises shaking detection circuit 361, edge sense circuit 362, and the second comparator circuit 363.Shaking detection circuit 361 and the output terminal of edge sense circuit 362 are connected an input end of the second comparator circuit 363 separately, and the shake reset signal that shaking detection circuit 361 exports is connected to the reset terminal of the envelope detected circuit 362 of correlation detection module 32 and the reset terminal of edge sense circuit 362 simultaneously.Output terminal and the shake of the first comparator circuit 323 of correlation detection module 32 are connected an input end of AND circuit 34 separately with the output terminal of the second comparator circuit 363 of frequency detection module 36, and the output terminal of AND circuit 34 transfers out wake-up signal 308.The intermediate-freuqncy signal 301 of input accesses the input end of sample circuit 31, the output terminal of sample circuit 31 accesses the correlation detection circuit 321 of square wave testing circuit and the input end of shaking detection circuit 361 and edge sense circuit 362 simultaneously, the clock signal 302 inputted is as the reference clock signal of square wave detector 3b, the power-on reset signal 303 of input controls sample circuit 31, correlation detection mould 32 and shake and frequency detection module 33 reset, the start-up time after reset is provided.Reset signal when input " CLEAR " 304 be added to square wave detector, then the register initial value CLEAR of Systematical control square wave detector resets.When system passes through register control word " SETTING " 305 assignment to related register, register control word " SETTING " 305 arranges initial value to the register in correlation detection module 32 in square wave detector and shake and frequency detection module 36, first amplitude threshold settings TH_MAG 306 of the first register accesses the reference value input end of the first comparator circuit 323 of correlation detection mould 32, the output terminal of envelope detected circuit 322 connects the signal value input end of the first comparator circuit 323, the comparative result that the first comparator circuit 323 exports.Second amplitude threshold settings 307 of the second register access the reference value input end of the second comparator circuit 363 of shake and frequency detection module 36, the output terminal of edge sense circuit 362 connects the signal value input end of the second comparator circuit 363, and the second comparator circuit 363 exports comparative result.The shake thresholding settings TH_JITTER that 3rd register exports accesses shake and frequency detection module 36 shaking detection circuit comparator reference edge, relatively, determines whether control reset signal generating circuit whether output jitter reset signal.The comparative result that first comparator circuit 323 exports and the comparative result that the second comparator circuit 363 exports are added to an input end of AND circuit 34 respectively.When the comparative result that the first amplitude threshold settings and second comparator circuit 363 of comparative result and input that the first comparator circuit 323 exports export all is high level with the second amplitude threshold settings inputted, AND circuit 34 exports the wake-up signal 307 of a high level.Otherwise AND circuit 34 exports as low level, does not export wake-up signal.

3rd embodiment

The circuit principle of compositionality block diagram of correlation detection module as shown in Figure 4.Correlation detection module is by computing cross-correlation frequency mixer 411,412, and digital oscillator 413, the anomalous integral summation circuit 42,43 of two-way cross-correlation, envelope detected circuit 322 and the first comparator circuit 323 are formed.Anomalous integral summation circuit 42 comprises the first integrator circuit 421 and the first accumulator circuit 422 that are connected in series; Anomalous integral summation circuit 43 comprises the second integral device circuit 431 and the second accumulator circuit 432 that are connected in series; The output terminal of second integral device circuit 431 is added to the input end of first integrator circuit 421.The circuit of correlation detection module path connects as follows: the output terminal of digital oscillator 413 and No. two frequency mixer 411 of computing cross-correlation with 412 local oscillation signal input end be connected, No. two frequency mixer 411 of computing cross-correlation are connected with the input end of the input end of the integrator circuit 421 of anomalous integral summation circuit 42 and the integrator circuit 431 of anomalous integral summation circuit 43 separately with the output terminal of 412, the output terminal of the integrator circuit 421 of anomalous integral summation circuit 42 and being connected of the first accumulator circuit 422, the output terminal of the integrator circuit 431 of anomalous integral summation circuit 43 and being connected of the first accumulator circuit 432, first totalizer 422 is connected with an input end of envelope detected circuit 322 separately with the output terminal of the second totalizer 432, the output terminal of envelope detected circuit 322 is connected with the input end of the first comparer 323, AND circuit 34 1 input ends of square wave detector are delivered in the output of the first comparer 323.

The course of work of correlation detection module: under reset signal effect, envelope detected circuit 322 resets, and the start time that correlation detection module is determined according to clock signal starts working.The sampled signal that sampling hold circuit exports arrives the signal input part of No. two frequency mixer 411 and 412 of computing cross-correlation simultaneously, the local oscillation signal that sampled signal and digital oscillator export makes computing cross-correlation in No. two frequency mixer 411 and 412, the output signal of No. one frequency mixer 412 send the second totalizer 432 to make accumulation process after second integral device 431 integration, the integrated signal that the output signal of another road frequency mixer 411 and second integral device 431 export, through first integrator 421 integration, send the first totalizer 422 to make accumulation process.The cumulative signal that first totalizer 422 exports and the cumulative signal that the second totalizer 432 exports are delivered to after envelope detected circuit 322 carries out envelope detected respectively, the output signal of envelope detected circuit 322 delivers to an input end of the first comparator circuit 323, with the value of the first register determined by register control word, this value is added in the reference signal end of the first comparator circuit as the first amplitude threshold settings, make comparisons through the first comparator circuit, if the output signal of envelope detected circuit 322 is within the first amplitude threshold settings, comparative result exports as high level, otherwise, comparative result exports as low level.

4th embodiment

The embodiment of the present invention provides frequency detection module circuit and forms block diagram, as shown in Figure 5.Frequency detection module is made up of edge sense circuit 332 and the second comparator circuit 303, and edge sense circuit 332 comprises the related peak detecting circuit 51 be sequentially connected in series, third integral device 52 and the 3rd totalizer 53.The sampled signal that sample circuit 31 exports delivers to the input end of related peak detecting circuit 51, the output terminal of the 3rd totalizer 53 delivers to an input end of the second comparator circuit 303, the RESET input of reset signal access third integral device 52 and the 3rd totalizer 53, reset signal also accesses another input end of the second comparator circuit 303.Described reset signal comprises from the power-on reset signal outside sheet and the reset signal from shaking detection circuit output in sheet.Frequency detection module is made up of the edge sense circuit 362 and the second comparator circuit 303 comprising related peak detecting circuit 51, third integral device 52 and the 3rd totalizer 53 of connecting successively.The circuit of frequency detection module path connects as follows, the output terminal of sampling hold circuit is connected with the input end of the related peak detecting circuit 51 of edge sense circuit 362, the output terminal of edge sense circuit 362 third integral device circuit 53 is connected with the input end of the second comparer 303, and an input end of the output terminal AND circuit of the second comparer 303 is connected.Output terminal and the wake-up signal of AND circuit produce circuit and are connected, and the output terminal that wake-up signal produces circuit is connected with wireless transceiver circuit to be waken up.

Under reset signal effect, frequency detection module enters testing: the input end that the sampled signal that sampling hold circuit 31 exports enters the related peak detecting circuit 51 of edge sense circuit 362 carries out sampled point detection, sampled point detection signal is outputted to third integral device circuit 52 integration, after Integral Processing, third integral device circuit 52 integral result send the 3rd totalizer 53 to complete the sampling number accumulation process of first time sense cycle; Enter second time sense cycle, equally by the sampling number accumulation process in second time sense cycle; The 3rd totalizer 53 pairs of sampling numbers are sent to continue by the integral result of third integral device circuit 52 cumulative, until enter third time sense cycle, equally by the sampling number accumulation process in third time sense cycle, complete the cumulative of the sampling number that three sense cycle time diversities detect; Again through the process of a sense cycle time, by the 3rd accumulator circuit 52, diversity is detected cumulative sampling number result and send into the second comparator circuit 303, judgement is compared with the second amplitude threshold settings being added in the second comparator circuit 303 reference signal end, improve judgement precision, judge that signal exports the input end being sent to AND circuit.

A kind of shaking detection modular circuit of the square wave testing circuit of first embodiment of the invention forms block diagram as shown in Figure 6 a, the another kind of shaking detection modular circuit of the square wave testing circuit of second embodiment of the invention forms block diagram as shown in Figure 6 b, and it is 8 that embodiment arranges M.

Shaking detection module 33 is made up of dither signal detection circuit 61 and reset signal generating circuit 62.Dither signal detection circuit 61 comprises the related peak detecting circuit 611, anomalous integral totalizer 612 and the shake comparer 613 that are connected in series, and the reference signal termination of shake comparer 613 enters to shake the initial value of comparison threshold.The output terminal of sampling hold circuit is connected with the input end of dither signal detection circuit 61, the output terminal of dither signal detection circuit 61 is connected with the input end of reset signal generating circuit 62, the output terminal of reset signal generating circuit 62 respectively with the input end delivering to integrator circuit in the reset terminal of correlation detection module Zhong Second Road integrator circuit and frequency detection module.

Under reset signal effect, shaking detection module enters testing, the sampled signal that sampling hold circuit exports enters the input end of related peak detecting circuit 611, sampled signal dutycycle carries out phase and computing with the local oscillation signal of the 8NkHz of 50%, the output signal of related peak detecting circuit 611 makes anomalous integral accumulation process through anomalous integral totalizer 612, in a sense cycle, the sampled point of sampled signal is added up, deliver to shake comparer 613 to the statistics of the sampled point of sampled signal in output sense cycle of anomalous integral totalizer 612 to compare with the settings of shake comparison threshold, if the deviate of sampled point statistical number is greater than shake comparison threshold value, then shake comparer 613 and export high level to reset signal generating circuit 62, the shake reset signal that reset signal generating circuit 62 exports, be added to AND circuit 34, AND circuit 34 is made to be in low level, shake reset signal simultaneously and deliver to correlation detection module and frequency detection module, make each module resets.

In the shake of square wave testing circuit and frequency detection module, a kind of formation block diagram of shaking detection circuit as shown in Figure 6 b.In Fig. 6 b, the formation of shaking detection circuit forms substantially identical with shaking detection circuit in Fig. 6 a, difference is that the output terminal of the former reset signal generating circuit directly connects AND circuit 34, and the output terminal of the reset signal generating circuit of the latter connects an input end of the second comparator circuit 303, after the second comparator circuit 303 compares process, deliver to gate circuit 34 again.

The dynamic duty process that the present invention is applied to the embodiment of the square wave detector of wireless awakening circuit is described in detail as follows:

For the embodiment chip of the square wave detector of wireless awakening circuit interface configuration as shown in Table 1, in table one: the register control word SETTING of 18 bit wides carries out initial value configuration to three registers, the bit wide that the first register, the second register and the 3rd register account for register control word SETTING is respectively 8,5 and 3.The register initial value configuration of square wave detector as shown in Table 2.

The basic conception of technical solution of the present invention is the Characteristics Detection utilizing the square wave of Digital Analog Hybrid Circuits to input intermediate-freuqncy signal to provide frequency, dutycycle; shaking detection, frequency detecting, correlation detection are integrated; improve the accuracy rate of input; thus provide wake that receiver wakes late-class circuit up up wake efficiency up, reduce false wake-up rate.All DLC (digital logic circuit), adopt CMOS technology to be integrated in a chip and realize.

Shaking detection module path, the circuit of this shaking detection module 33 is configured to related peak detecting circuit and a reset signal generating circuit of a numerical model analysis, and the output terminal of peak detection circuit is connected with the input end of reset generation circuit.Setting N be 14, M is that 8,14 kHz intermediate-freuqncy signals enter into a related peak detecting circuit after sampling hold circuit, in peak detection circuit 14 kHz and dutycycle be 112 kHz of 50% local oscillation signal phase and.In one-period, the high level of local oscillation signal and low level place can produce 4 sampled points respectively, have 8 sampled points altogether.

When signal is normal, input signal is the square wave of 14kHz, and dutycycle is 50%.When the frequency of sampling clock is 112kHz, the related peak detecting circuit of shaking detection module detects that the high level of square wave and low level all comprise 4 sampled points of time detecting, so related peak detecting circuit exports as low level, and reset generation circuit does not just export reset signal.If when signal is abnormal, related peak detecting circuit detects that the high level of square wave and the sampling number of low level time detection are less than the shake comparison threshold TH_JITTER initial value of the 3rd register setting, just export as high level, reset generation circuit can produce reset signal.This reset generation circuit is made up of automatically reset inner accumulator register and a Data-Link, and the output terminal of this reset circuit is connected with the input end of the input end of the integrator circuit in correlation detection module with the integrator circuit in frequency detection module respectively.By inner accumulator register and the data of automatically reseting, testing circuit can be made to export high level.

Shake (Jitter) detection threshold TH_JITTER can configure, if allow the error 2 of a sampled point, namely shaking detection thresholding default value (M-2) is 6.If M settings are 16, allow the error 2 of a sampled point, shaking detection thresholding default value (M-2) is 14, the value of amendment Jitter detection threshold TH_JITTER, can emulation experiment choose reasonable M settings be passed through, optimize square wave detection perform.

Frequency detection module path, this module 36 is the frequency detection circuit of a numerical model analysis.14 kHz intermediate-freuqncy signals 301 enter into an edge sense circuit 332 after sampling hold circuit 31, whether edge sense circuit 332 changes according to previous clock and current clock signal level judges whether input signal saltus step occurs, thus detects the edge of input signal.If generation saltus step, edge sense circuit exports a high level, thinks there is a sampled point.The output terminal of edge sense circuit is connected with the input end of third integral device, if the reset signal generating circuit in shaking detection path 731 does not produce reset signal, the high level of input third integral device counts one by one through third integral device 733 pairs of sampled points, at the end of the first sense cycle, be sent to totalizer 3 add up, through the time of a delay circuit 7 time delay sense cycle, at the end of the second sense cycle, third integral device is delivered to totalizer 3 sampled point count value again and is added up, equally, through the time of a delay circuit 8 time delay sense cycle, at the end of the 3rd sense cycle, third integral device is delivered to totalizer 3 sampled point count value again and is added up, after the cumulative of three sampled point numbers with maintenance, in the time of a delay circuit 8 time delay sense cycle, at the end of the 4th sense cycle, the sampled point number that three time diversities is cumulative is sent in the second comparator circuit 735, compared with the second amplitude threshold settings determining frequency detecting permissible variation.If comparative result is for meeting comparison condition, then can export high level, being sent to the AND circuit 74 of rear stage.Frequency detecting path is by the number of the transition edges of sampled signal within the certain hour cycle or claim sampling number to judge the correctness that frequency input signal detects, in theory, if detection window number is set to 9, so total transition edges number should be 18, if frequency comparison threshold is set to 18, the sampled point of 18 high level is detected at totalizer 3, compare with frequency comparison threshold settings at the second comparator circuit 735, be judged to be normal, the second comparator circuit 735 exports the AND circuit 74 of high level to rear stage.If the sampled point number detected by totalizer 3 and frequency comparison threshold settings compare, the output valve as totalizer 3 is less than 18, then think that frequency input signal is abnormal, and the second comparator circuit 735 output low level is to the AND circuit of rear stage.In fact input signal is faint and be easily disturbed, occur that the sampled point number accumulated value of the totalizer 3 of edge sense circuit is lower than frequency comparison threshold settings, usually empirically configuration allows deviation value, by the settings of comparison threshold of adjusting frequency, realize the optimization improving speed of waking up and reduce false wake-up probability two aspect.

Correlation detection path, correlation detection is also called amplitude detection, and reality is also the detection to input signal dutycycle, with shaking detection unlike, amplitude detection is the mean value to whole detection window.This path is made up of the Digital Analog Hybrid Circuits through comprehensively forming.IF input signals is sent in two-way correlation calculating circuit after sampling hold circuit sampling, correlation calculating circuit is digital mixer, the orthogonal signal (square wave) that input intermediate-freuqncy signal is identical with input intermediate-freuqncy signal with the cycle of two-way in two-way correlation calculating circuit make related operation, and two-way orthogonal signal are produced by the numerically controlled oscillator of built-in chip type.The output signal of two-way correlation calculating circuit enters the anomalous integral summation circuit be made up of an integrator circuit and an accumulator circuit respectively, first make Integral Processing by integrator, and then send into totalizer and make accumulation process, anomalous integral summation circuit output terminal connects the input end of an envelope detector, the output terminal of envelope detector connects the first comparator circuit input end, in the first comparer, with the first amplitude threshold settings, done comparing of correlation detection to the output signal of envelope detector, judge that whether signal is correct.First amplitude threshold of correlation detection can be configured by upper computer software.The default value of the first amplitude threshold is 40, relevant with the size of detection window.In the square wave detector of first embodiment of the invention: sample frequency FS is 112KHz, input IF signal frequency FIN is 14KHz, and the size of detection window is 9 cycle FIN.

Fig. 7 provides embodiment of the present invention square wave detector on-chip circuit and forms block diagram; Below in conjunction with the initial value allocation list shown in the chip interface table shown in Fig. 7 and table one and table two, square wave detector dynamic duty process is described in detail as follows:

1, be that it arranges the initial value of following each settings by square wave detector place system

1) window number settings k, the Systematical control PRD inputted outward by sheet realize configuration, and acquiescence k initial value is 9;

2) amplitude comparison threshold settings TH_MAG, the register control word inputted outward by sheet realizes configuration, and acquiescence TH_MAG initial value is 40, and relevant with the size of detection window, correlation detection right-on envelope detection output amplitude value is 50.Embodiment setting input IF signal frequency FIN is 14KHz, sample frequency FS is 112KHz, and the detection window time is 9 FIN frequency square wave cycles.

3) frequency comparison threshold settings TH_FREQ, the register control word inputted outward by sheet realizes configuration, and acquiescence TH_FREQ initial value is 3;

4) shake comparison threshold settings TH_JITTER, the real configuration of the register control word inputted by sheet outward, acquiescence TH_JITTER initial value is 2;

2, electrification reset: 14kHz intermediate-freuqncy signal IFDATA is from 701 interface input sampling circuits 71, and the sampling clock through 112k is sampled, then delivers to correlation detection module, shaking detection module and frequency detection module three tunnel module path respectively and detects.The frequency FIN of input intermediate-freuqncy signal is set to 14kHz, and the frequency FS of sampling clock is set to 112 kHz, and this locality that digital oscillator 720 exports also is FIN=14kHz with reference to square wave frequency.

1) the correlation detection module channels course of work:

It is 9 that window number arranges initial value k, and setting-up time diversity number of times of being correlated with is 3.Digital oscillator 720 exports local oscillator square wave, and the integral time of first integrator 723 and second integral device 724 is 9/3 FIN frequency local oscillator square-wave cycle, and the time of total detection window equals 3*9/3=9 FIN frequency local oscillator square-wave cycle.Be the local oscillator side of the intermediate-freuqncy signal of 14kHz corresponding to FIN be wave period 71us, so one detection period and an integral time are 213us, the time of total detection window equals 639us, and the quiescent interval after three times diversity detects is one detection period and 213us.When inputting 14k square-wave signal, detecting that the time interval of this signal is 639us, adding that the intermittent phase is 852us, so wakeup time is 639us ~ 852us.

The correlation detection of the correlation detection module dependant amplitude that is otherwise known as detects, and it is to the detection of if sampling input signal dutycycle, is the detection of the mean value to whole detection window.If sampling signal is through a pair orthogonal correlation calculating circuit process based on digital mixer 721 and 722 and digital oscillator 720, digital mixer 721 is delivered to reference to square wave cosine signal in this locality that digital mixer 721 exports, and digital mixer 722 is delivered to reference to the sinusoidal signal of square wave in this locality that digital mixer 721 exports.The cosine that digital mixer 721 and 722 exports and sinusoidal local oscillation signal, respective correspondence delivers to the input end of first integrator 723 and second integral device 724, simultaneously second integral device 724 output to first integrator 723, participate in the integration of first integrator 723, for completing cosine and sinusoidal local oscillation signal.The integral output signal of first integrator 723 and second integral device 724, the first totalizer 725 and the second totalizer 726 input end delivered to by delay circuit of respectively hanging oneself.First totalizer 725 and the second totalizer 726 are the totalizer that band time delay is deposited, for passing through time delay, the time diversity completing three integral time detects, improve correct detection probability, and using an integral time as reset and stand-by period, make correlation detection path and frequency detecting path that respective testing result is synchronously input to AND circuit input end, if one-time detection is unsuccessful, enters after reset and detect next time.The integral output signal correspondence of first integrator 723 and second integral device 724 delivers to the first totalizer 725 and accumulation process made by the second totalizer 726, first totalizer 725 is Cos phase accumulator, second totalizer 726 is Sin phase accumulator, first totalizer 725 of two-way quadrature channel and the output signal of the second totalizer 726, respective correspondence is through the time delay of an integral time of delay circuit 727-1 and delay circuit 717-2, again by an input end of two paths of signals correspondence input envelope detector 728, envelope detector 728 exports correlativity count value and sends into the first comparator circuit 729, compare with the initial value 40 that arranges of the first amplitude threshold 706, envelope detected range value >=40 of correlation detection module, the dutycycle of decision signal and the mean value of frequency are correct, first comparator circuit 729 exports as high level, otherwise envelope detected range value < 40, first comparator circuit 729 exports as low level.

2) the shaking detection module channels course of work: from the if sampling signal adopting circuit 71 to export, the input end of input jiffer testing circuit 731, export sampled point numerical value by shaking detection circuit 731 to compare with shake comparison reference, the default value of Jitter detection threshold TH_JITTER initial value configuration is 2, namely allows the metrical error of a sampled point.If a detection time within detection time clock period of setting detection window number k is sampled point metrical error number >=2 sampled point in 213us, judge that shake appears in sampled signal immediately, low level Jitter reset signal is produced by reset generation circuit, export Jitter reset signal, integrator 723,724 and 733 relevant in sheet and totalizer 725,726 and 734 are automatically reset, thus make the AND circuit 74 of square wave testing circuit cannot export the wake-up signal of high level, start new one-time detection simultaneously.

3) frequency detection module channels operation process:

In shake and frequency detection module, the detection window number of related peak detecting circuit of edge sense circuit 732 is configurable, and detection window number is configured by settings k, and the settings k of detection window number is arranged by Systematical control SPI interface.In addition, frequency comparison threshold value TH_FREQ i.e. the second amplitude threshold settings are also configurable.The frequency detection module path of shake and frequency detection module 73 is the frequency detection circuit 732 of a numerical model analysis.14 kHz intermediate-freuqncy signals 701 enter into an edge sense circuit 732 after sampling hold circuit 71, whether edge sense circuit 732 changes according to previous clock and current clock signal level judges whether input intermediate-freuqncy signal saltus step occurs, thus detects the edge of input intermediate-freuqncy signal.If generation saltus step, edge sense circuit 732 exports as high level.The input end that the output terminal of edge sense circuit 732 delivers to third integral device 733 carries out Integral Processing, if the reset signal generating circuit in shaking detection path does not produce reset signal, the high level one by one that third integral device 733 pairs of edge sense circuits 73 export, integration one by one.The integrated value that third integral device 733 exports, is sent in the 3rd totalizer 734 through time delay, the integral output signal of third integral device 733, delivers to the 3rd totalizer 734 input end through delay circuit.3rd totalizer 734 is also the totalizer that band time delay is deposited, and for by time delay, completes the time diversity detection of three integral time, improves correct detection probability.The output signal of the 3rd totalizer 734 is sent in the second comparer 736 after a time delay is deposited, compared with the second amplitude threshold settings determining frequency detecting permissible variation.If signal correctly, can high level be exported, be sent to the AND circuit 74 of rear stage.Frequency detecting path is the frequency being calculated input signal by counting input signal at the transition edges in certain hour mid-term.Under normal circumstances, be 9 for detection window number, total transition edges number should be 18,18 high level signals should be able to be detected at the input end of accumulator circuit.Now frequency comparison threshold is set to 18.In the second comparer 736, the count value of totalizer output terminal and the second amplitude threshold fiducial value are compared.Frequency comparison threshold initial value is 3, namely allow to occur detection error≤3, if the output valve > (18-3) of the 3rd totalizer 734, when namely differing larger with permission detection error value, then not think it is normal signal, the second comparer 736 output low level is to the AND circuit 74 of rear stage.This avoid false wake-up, but wake probability up and will reduce.In concrete enforcement, the detection saltus step high level number that there will be edge sense circuit 732 can send and depart from permissible value, make the output valve deviation theory value of third integral device 733 and the 3rd totalizer 734 thus, giving tacit consent to configurable permission detection error is 5, the settings that then frequency comparison threshold TH_FREQ is corresponding are 5, as long as the output valve of the 3rd totalizer 734 is greater than frequency comparison threshold value respective value (18-5), just judge that the frequency of input intermediate-freuqncy signal is normal, the second comparer 736 exports the AND circuit 74 of high level to rear stage.By the settings of comparison threshold of adjusting frequency, realize the optimization improving speed of waking up and reduce false wake-up probability two aspect, realize the square wave detector for wireless awakening circuit that low false wake-up, high recall rate are provided.

Finally, three module paths of the correlation detection of square wave detector, shaking detection and frequency detecting are through the detection of three sense cycle, if the result magcmp of correlation detection is high level, the result freqcmp of frequency detecting is high level, and shaking detection circuit does not produce low level reset signal in each sense cycle, AND circuit is the wake-up signal decision of output detections result and high level in a treatment cycle just, thus on the corresponding time exporting wake-up signal, drive its wireless awakening circuit by Upper system.

Table one

Table two

Title	Symbol	Bit wide	Explanation
				PRD	k	3	Detection window number, default value is 9
Amplitude threshold	TH_MAG	8	Amplitude comparison threshold, default value is 40
				Frequency threshold	TH_FREQ	5	Frequency comparison threshold, acquiescence deviate is 3
Shake threshold value	TH_JITTER	3	Shake comparison threshold, acquiescence deviate is 2

Protection scope of the present invention, is not limited to embodiments described herein.As long as various change is in claims restriction and the technical characteristic of the present invention determined and protection domain, these changes are apparent, and all examples utilizing the present invention to conceive are all at the row of protection.

Claims

1. for a square wave detector for wireless awakening circuit, it is characterized in that, square wave detector comprises:

A signal sample circuit, sample frequency is M times of input intermediate-freuqncy signal N kHz, and the span of N is 10 ~ 200; By sample frequency be MN kHz square wave to input N kHz intermediate-freuqncy signal sample, the span of M is 4,8,16;

2. square wave detector according to claim 1, is characterized in that: the shaking detection module path of described square wave testing circuit, frequency detection module path and correlation detection block path and AND circuit are integrated in same chip, consist of:

The AND circuit of one three input, for exporting wake-up signal;

3. square wave detector as claimed in claim 2, is characterized in that: described correlation detection module path comprises sampling hold circuit, digital oscillator, a pair digital mixer, a pair anomalous integral summation circuit, envelope detected circuit and the first comparator circuit; A pair digital mixer and a pair anomalous integral summation circuit form computing cross-correlation device circuit; The output terminal of sampling hold circuit is connected with the input end of a pair digital mixer respectively, the signal end of a pair digital mixer is connected with digital oscillator output terminal respectively, and the output terminal of a pair digital mixer is connected with the input end of corresponding first integrator with second integral device respectively; The output terminal of first integrator connects the input end of the first totalizer, and the output terminal of second integral connects the input end of the second totalizer; The output terminal of the first totalizer and the output terminal of the second totalizer are corresponding to be respectively connected with an input end of envelope detected circuit, for the mean value of comprehensive detection input signal dutycycle and frequency; The output terminal of envelope detected circuit is connected with the input end of the first comparator circuit, and the output terminal of the first comparer connects an input end of AND circuit.

4. square wave detector as claimed in claim 2, is characterized in that: described frequency detection module path comprises sampling hold circuit, and the frequency detection module be made up of an edge sense circuit and the second comparator circuit; Frequency detection module is the structure adopting Digital Analog Hybrid Circuits, the input end of edge sense circuit connects sampling hold circuit, the output terminal of edge sense circuit connects an input end of the second comparator circuit, another input end of second comparator circuit accesses the second amplitude threshold settings, and the output terminal of the second comparator circuit connects an input end of AND circuit; Frequency detection module adopts Digital Analog Hybrid Circuits structure; Wherein:

Described edge sense circuit comprises the peak detection circuit, third integral device and the 3rd totalizer that connect successively; Related peak detecting circuit is a kind of amplitude detection circuit, its input end connects the output terminal of the sampling hold circuit of square wave detector, the output terminal of peak detection circuit is connected with the input end of third integral device, third integral device band integration holding circuit, third integral device output terminal is connected with the input end of the 3rd totalizer, the output terminal of the 3rd totalizer connects an input end of the second comparator circuit, for detecting the frequency of input sample signal; The reference signal termination of the second comparator circuit enters the second amplitude threshold settings; The reset terminal of reset signal access third integral device, the 3rd totalizer and the second comparator circuit or clear terminal; Frequency detection module, for detecting the frequency of input signal, by detecting the number of the hopping edge of sampled signal, realizes the frequency detecting to input sample signal;

5. square wave detector as claimed in claim 2, is characterized in that: described shaking detection module path comprises sampling hold circuit, and the shaking detection module be made up of the dither signal detection circuit be connected in series and reset signal generating circuit;

Described dither signal detection circuit is made up of, for detecting the dutycycle of input sample signal the related peak detecting circuit connected successively, the 4th integrator and the 4th totalizer; The output terminal of sampling hold circuit is connected with dither signal detection circuit input end, and dither signal detection circuit is connected with reset signal generating circuit input end by output terminal;

The output terminal of described reset signal generating circuit directly connects an input end of the AND circuit of square wave detector; The reset signal that reset signal generating circuit exports accesses reset terminal or the clear terminal of the anomalous integral summation circuit in the reset terminal of the envelope detected circuit in correlation detection module and frequency detection module respectively.

6. square wave detector as claimed in claim 2, is further characterized in that: described shaking detection module and frequency detection module merge to form shakes and frequency detection module; Shake and frequency detection module comprise the shaking detection circuit be made up of dither signal detection circuit and reset signal generating circuit, the edge sense circuit be made up of the related peak detecting circuit connected successively, third integral device and the 3rd totalizer, and the second comparator circuit; Wherein

Described dither signal detection circuit is made up of the related peak detecting circuit connected successively, the 4th integrator and the 4th totalizer; The output terminal of sampling hold circuit is connected with dither signal detection circuit input end, dither signal detection circuit is connected with reset signal generating circuit input end by output terminal, an input end of the second comparator circuit of the output terminal rate of connections detection module of reset signal generating circuit; The reset signal that reset signal generating circuit exports accesses reset terminal or the clear terminal of the anomalous integral summation circuit in the reset terminal of the envelope detected circuit in correlation detection module and frequency detection module respectively;

7. the square wave detector as described in claim 3 or 4 or 5 or 6, is characterized in that: described correlation detection module, frequency detection module and shaking detection module also comprise a register separately: be the first register, the second register and the 3rd register respectively; The data input pin correspondence of three registers connects three fields of the register control word of Upper system: wherein:

The data input pin of described 3rd register connects the 3rd field of the register control word of Upper system, for configuring the initial value of shake comparison threshold value TH_ JITTER, the data output end of the 3rd register connects shake comparator circuit reference signal end, provides shake comparison threshold settings.

8. square wave detector as claimed in claim 6, is further characterized in that: described shake and frequency detection module also comprise the second register and the 3rd register, wherein:

9. square wave detector as claimed in claim 2, is characterized in that: the wake-up signal end of the wireless transceiver circuit of the output terminal connecting band wireless awakening circuit of described square wave detector; For when the AND circuit output terminal of square wave detector is high level, exports the wake-up signal WAKEUP of high level, realize waking up wireless transceiver circuit.

10. the square wave detector as described in one of claim 1-6 or 8, be further characterized in that: the signal sample circuit of described square wave detector, and the correlation detection module of square wave testing circuit, shaking detection module and frequency detection module, or above-mentioned shaking detection module and frequency detection module merge the shake and frequency detection module that form, and AND circuit, adopt CMOS technology to be integrated in a chip, chip-scale circuit is based on Digital Analog Hybrid Circuits structure; Adopt Digital Analog Hybrid Circuits structure high for the reliability improving square wave detector, thus meet the high reliability request of wireless awakening circuit;