CN103412615B - A kind of impulse- free robustness self-adaptation clock switching method for UART interface chip - Google Patents
A kind of impulse- free robustness self-adaptation clock switching method for UART interface chip Download PDFInfo
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- CN103412615B CN103412615B CN201310371235.7A CN201310371235A CN103412615B CN 103412615 B CN103412615 B CN 103412615B CN 201310371235 A CN201310371235 A CN 201310371235A CN 103412615 B CN103412615 B CN 103412615B
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Abstract
The invention discloses a kind of clock-switching method of UART interface chip, comprise the following steps：1) configuration information that self-adaptation clock handover module is written in parallel to according to CPU obtains the subsequent work state of UART interface chip：Input clock frequency and baud rate；2）Calculate master clock frequency needed for UART interface chip；3）Master clock frequency and input clock frequency needed for comparing, when required master clock frequency is higher than input clock frequency, overtones band is calculated, opens frequency multiplier, when required master clock frequency is less than input clock frequency, close frequency multiplier；4）According to the opening and closing of frequency multiplier, the switching of chip master clock is carried out.UART interface chip is connected including a self-adaptation clock handover module with chip master clock.The present invention automatically adjusts the clock strategy of chip, reaches the purpose for optimizing power consumption according to the current working condition of High Speed UART interface chip, and next working condition that CPU write enters.
Description
Technical field
The present invention relates to the clock-switching method of UART interface chip.
Background technology
Data transfer between main frame and external equipment includes two kinds of parallel transmission and serial transmission, wherein parallel
Transmit and be used for apart from short, fireballing occasion, and in the case where distance, rate request be not high, generally use serial transmission.
As shown in figure 1, more between CPU and serial equipment carry out simultaneously serial ports turn using UART (UART Universal Asynchronous Receiver Transmitter) interface chip
Change：The data that CPU is written in parallel to by UART interface chip change into serial port protocol, are sent by frame format set in advance and baud rate
To serial equipment；And the serial data received is stored in inner buffer, read parallel for CPU.
Most of UART interface chips may operate under a variety of baud rates (transmission rate), and serial logical in order to improve
The anti-interference and reliability of news, 16 times of clock sampling rs 232 serial interface signals of serial interface chip generally use, i.e. chip master clock are strings
16 times of mouth baud rate.With the continuous development of computer technology, some special occasions often may require that serial ports speed reaches
5Mbit/s even more highs, therefore it is required that serial port chip meet working standard baud rate (such as 110,300,600,1200,2400,
4800th, 9600,19200,38400,614400 etc.) in the case of transmitting, moreover it is possible to take into account nonstandard High Speed Serial agreement.In order to
Nonstandard High Speed Serial agreement is taken into account during 16 sampling, clock multiplier is generally integrated in UART interface chip as shown in Figure 1.Mesh
The baud rate adjustment of preceding serial port chip, is that chip input clock frequency is fixed mostly, when being adjusted by CPU inside UART interface chip
The method of clock pre-divider 101 is realized.But due to the presence of UART interface chip internal clocking frequency multiplier, only by frequency dividing
Mode adjusts baud rate, is unable to reach the optimization of UART interface chip power consumption.
The content of the invention
It is an object of the invention to：Make High Speed UART interface chip in wider baud rate scope, can be according to baud
Rate requirement adjustment chip internal clock strategy, and switching with ensureing clock safety, impulse- free robustness in real time, so as to reach optimization chip work(
The purpose of consumption.
In digital circuit, the data signal of input change or carry out some logical operations (it is such as non-, with or) when, it is defeated
Go out signal without energy Complete Synchronization to change, so as to trigger the error signal pulse in the of short duration time to export, this error signal
Pulse is very narrow, referred to as " burr " (English：glitch)；In the present invention, the master clock (mclk) of UART chip is defeated in chip
When entering clock clkin and chip internal frequency multiplier output clock pllclk and switching therebetween, misoperation can introduce narrow
Pulse, also referred to as burr.
Technical scheme is used by reach above-mentioned purpose：A kind of clock-switching method of UART interface chip, including
Following steps：
1) configuration information that self-adaptation clock handover module is written in parallel to according to CPU obtains next work of UART interface chip
Make state：Input clock frequency and baud rate；
2) master clock frequency needed for UART interface chip is calculated；
3) master clock frequency and input clock frequency needed for comparing, when required master clock frequency is higher than input clock frequency
When, calculate overtones band：Frequency during overtones band=master clock frequency/input, frequency multiplier is opened, when required master clock frequency is less than
During input clock frequency, frequency multiplier is closed；
4) according to the opening and closing of frequency multiplier, the switching of chip master clock is carried out.
Master clock frequency needed for the UART interface chip is baud rate * UART interface chip clock multipliers.UART interface
Chip clock multiple is 16.
The switching of the chip master clock is the switching between chip input clock and frequency multiplier output clock.
The switching method of chip input clock and frequency multiplier the output clock, comprises the following steps：
A. when frequency multiplier switches to closing by opening, switch to chip defeated by frequency multiplier output clock chip master clock
Enter clock；
B. when frequency multiplier switches to unlatching by closing, frequency multiplier is switched to export by chip input clock chip master clock
Clock；
If C. frequency multiplier need keep it turned on, and need adjust overtones band when, chip master clock is switched to overtones band
Frequency multiplier output clock after adjustment.
It is described by chip master clock by frequency multiplier output clock switch to chip input clock the step of be：
Frequency multiplier, which is closed, in the trailing edge of frequency multiplier output clock exports clock to the path of chip master clock；
Close frequency multiplier；
Next chip input clock trailing edge opening chip input clock to chip master clock path；
Complete chip master clock and switching of the clock to chip input clock is exported by frequency multiplier.
It is described by chip master clock by chip input clock switch to frequency multiplier export clock the step of be：
Overtones band is set, frequency multiplier is opened, the switching of chip master clock is carried out after frequency multiplier output is stable：
Chip input clock is closed to the path of chip master clock in the trailing edge of chip input clock；
Frequency multiplier, which is opened, in the trailing edge of next frequency multiplier output clock exports clock to the path of chip master clock；
Complete the switching that chip master clock is exported clock by chip input clock to frequency multiplier.
It is described by chip master clock be switched to overtones band adjustment after frequency multiplier export clock the step of be：
Frequency multiplier, which is closed, in the trailing edge of frequency multiplier output clock exports clock to the path of chip master clock；
Adjust the overtones band of frequency multiplier；
After frequency multiplier output is stable, opens frequency multiplier in the trailing edge of next frequency multiplier output clock and export clock to core
The path of piece master clock；
Complete the switching that the frequency multiplier after chip master clock adjusts to overtones band exports clock；
The stable required time of frequency multiplier output is determined by a counter, when the value of counter reaches the locking of frequency multiplier
Between after switch over.The advantages of patent of the present invention, is:
According to the current working condition of High Speed UART interface chip, and next working condition that CPU write enters, automatically
The clock strategy of chip is adjusted, reaches the purpose of optimization power consumption.
If desired the working condition of frequency multiplier inside High Speed UART interface chip is adjusted, then avoids frequency multiplier automatically in state
Amphibolia during switching, High Speed UART interface chip is avoided to run and fly because master clock shakes, impulse- free robustness when clock switches.
Frequency multiplier, which is exported between clock and High Speed UART interface chip input clock, has certain phase difference, and the phase
Potential difference is related to chip manufacturing process, it can be considered that frequency multiplier output clock is with High Speed UART interface chip input clock
Asynchronous relationship.The important component of the present invention is when ensureing the switching of the two asynchronous clocks, will not to introduce burr.
Brief description of the drawings
Fig. 1 is the structural representation of High Speed UART interface chip of the prior art；
Fig. 2 is the High Speed UART interface chip work of the addition self-adaptation clock handover module of the UART interface chip of the present invention
Make structural representation；
Fig. 3 is the flow chart of the inventive method；
Fig. 4 is the flow chart of the clock impulse- free robustness switch step in Fig. 3
Embodiment
Chip master clock (mclk) is the work clock of sequence circuit inside UART chip；According to the different work of UART chip
Make state, mclk can be chip input clock (clkin) or frequency multiplier output clock (pllclk), i.e., mclk is
Clkin and pllclk alternative；Such as during selection signal=0, mclk=pllclk, during selection signal=1, mclk=
clkin.The delay existed due to frequency multiplier between input and output is uncertain, causes the phase difference between pllclk and clkin
It is uncertain, so as to which very narrow pulse, i.e. burr occurs in mclk when causing pllclk and clkin to switch, so as to cause chip circuit
Very serious logic error.It is an object of the invention to solve chip master clock (mclk) because of the different working condition of UART chip
Switch the Burr Problem brought, ensure the safe operation of chip circuit.
Embodiment
The UART interface chip of the present invention is as shown in Fig. 2 in before the pre-divider 101 of original High Speed UART interface chip
Self-adaptation clock handover module 201 is added, self-adaptation clock handover module 201 is connected with chip master clock, according to frequency multiplier
State change, carry out the switching of chip master clock.
Specific self-adaptation clock handover module 201 also includes working condition identification module 202, clock switchover module 203,
The UART interface chip work state information that working condition identification module 202 is written in parallel to according to CPU, when main needed for computing chip
Whether the frequency of clock, the master clock frequency according to needed for are higher than input clock frequency and current frequency multiplier state, judge whether to open
Frequency multiplier simultaneously calculates overtones band when necessary；The state adjustment times in real time that clock switchover module 203 needs to redirect according to frequency multiplier
Frequency device, and carry out the switching between chip input clock and frequency multiplier output clock.
The present invention workflow as shown in figure 3,
A. the UART interface chip work state information being written in parallel to first by working condition identification module 202 according to CPU
(chip input clock clkin frequency fclkin, baud rate Br), the frequency f of master clock mclk needed for computing chipmclk=Br ×
16 (16 are UART interface chip clock multiplier).According to fmclkWhether f is more thanclkin, and the working condition of frequency multiplier at present, come
Determine next working condition of frequency multiplier：
If required master clock frequency is not higher than input clock frequency (fmclk≤fclkin), frequency multiplier will be closed.
If required master clock frequency is higher than input clock frequency (fmclk>fclkin), then calculate needed for overtones band.
B. clock switchover module 203 is according to the state transition situation of frequency multiplier, impulse- free robustness switching clock.
The clock impulse- free robustness switch operating flow of clock switchover module 203 in Fig. 3 is as shown in Figure 4：
If a. frequency multiplier state switches to closing by opening, judge that chip master clock mclk will export clock by frequency multiplier
Pllclk switches to chip input clock clkin：
Pllclk to mclk path is closed in pllclk trailing edge.(rising edge refer to signal from low transition to
The moment of high level, trailing edge refer to that signal jumps to low level moment from high level.)
Close frequency multiplier；
After pllclk to mclk path blockade, the logical of clkin to mclk is opened in next clkin trailing edge
Road；Complete switchings of the mclk by pllclk to clkin.(due to the alternative that mclk is clkin and pllclk, close clock and lead to
Road is completed by one with door, i.e., when " selection signal " is low level, should be clamped at low level with the output of door.)
If b. frequency multiplier state switches to unlatching by closing, judge that chip master clock mclk will be switched to by clkin
pllclk：
Overtones band is set, opens frequency multiplier；
Delay a period of time：Using clkin as clock count, count value is the locking time of frequency multiplier；
Clkin to mclk path is closed in clkin trailing edge；
After clkin to mclk path blockade, the logical of pllclk to mclk is opened in next pllclk trailing edge
Road, complete switchings of the mclk by clkin to pllclk.
If c. frequency multiplier need keep it turned on, and need adjust overtones band when：
Pllclk to mclk path is closed in pllclk trailing edge；
Adjust the overtones band of frequency multiplier；
Delay a period of time：Using clkin as clock count, count value is the locking time of frequency multiplier；
Pllclk to mclk path is opened in next pllclk trailing edge, completes the adjustment of overtones band.
Claims (4)
1. a kind of clock-switching method of UART interface chip, comprises the following steps：
1) configuration information that self-adaptation clock handover module is written in parallel to according to CPU obtains the subsequent work shape of UART interface chip
State：Input clock frequency and baud rate；
2) master clock frequency needed for UART interface chip is calculated；
3) master clock frequency and input clock frequency needed for comparing, when required master clock frequency is higher than input clock frequency, meter
Calculate overtones band：Frequency during overtones band=master clock frequency/input, frequency multiplier is opened, when required master clock frequency is less than input
During clock frequency, frequency multiplier is closed；
4) according to the opening and closing of frequency multiplier, the switching of chip master clock is carried out, switching method, is comprised the following steps：
A. when frequency multiplier switches to closing by opening, when switching to the chip to input by frequency multiplier output clock chip master clock
Clock, step are：
Frequency multiplier, which is closed, in the trailing edge of frequency multiplier output clock exports clock to the path of chip master clock；
Close frequency multiplier；
Next chip input clock trailing edge opening chip input clock to chip master clock path；
Complete chip master clock and switching of the clock to chip input clock is exported by frequency multiplier；
B. when frequency multiplier switches to unlatching by closing, when switching to the frequency multiplier to export by chip input clock chip master clock
Clock, step are：
Overtones band is set, frequency multiplier is opened, the switching of chip master clock is carried out after frequency multiplier output is stable：
Chip input clock is closed to the path of chip master clock in the trailing edge of chip input clock；
Frequency multiplier, which is opened, in the trailing edge of next frequency multiplier output clock exports clock to the path of chip master clock；
Complete the switching that chip master clock is exported clock by chip input clock to frequency multiplier；
If C. frequency multiplier need keep it turned on, and need adjust overtones band when, by chip master clock be switched to overtones band adjustment
Frequency multiplier output clock afterwards, step are：
Frequency multiplier, which is closed, in the trailing edge of frequency multiplier output clock exports clock to the path of chip master clock；
Adjust the overtones band of frequency multiplier；
After frequency multiplier output is stable, opens frequency multiplier in the trailing edge of next frequency multiplier output clock and export clock to chip master
The path of clock；
Complete the switching that the frequency multiplier after chip master clock adjusts to overtones band exports clock.
2. the clock-switching method of UART interface chip according to claim 1, it is characterised in that the UART interface core
Master clock frequency needed for piece is baud rate * UART interface chip clock multipliers.
3. the clock-switching method of UART interface chip according to claim 1, it is characterised in that the chip master clock
Switching be chip input clock and frequency multiplier output clock between switching.
4. the clock-switching method of UART interface chip according to claim 1, it is characterised in that by a counter come
The time required to determining that frequency multiplier output is stable, switched over after the locking time that the value of counter reaches frequency multiplier.
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| CN201310371235.7A CN103412615B (en) | 2013-08-22 | 2013-08-22 | A kind of impulse- free robustness self-adaptation clock switching method for UART interface chip |
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| CN201310371235.7A CN103412615B (en) | 2013-08-22 | 2013-08-22 | A kind of impulse- free robustness self-adaptation clock switching method for UART interface chip |
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| CN103412615B true CN103412615B (en) | 2018-02-09 |
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| CN104360974A (en) * | 2014-10-29 | 2015-02-18 | 上海伽利略导航有限公司 | Method and device for automatically adjusting Baud rate of universal asynchronous receiver/transmitter (UART) |
| CN108170630B (en) * | 2017-12-28 | 2021-02-02 | 杭州万高科技股份有限公司 | Serial port communication baud rate self-adaption method, system and equipment |
| CN111400216A (en) * | 2019-01-03 | 2020-07-10 | 珠海格力电器股份有限公司 | UART module, UART module transmission parameter adjusting method and system-on-chip |
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| CN1589425A (en) * | 2001-11-15 | 2005-03-02 | 模拟设备股份有限公司 | Glitch-free clock select switching |
| CN102314208A (en) * | 2010-06-30 | 2012-01-11 | 重庆重邮信科通信技术有限公司 | Method and device for dynamically adjusting frequency and voltage of embedded equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6895518B2 (en) * | 2001-05-31 | 2005-05-17 | Koninklijke Philips Electronics N.V. | Power and frequency adjustable UART device |
| EP1793301A1 (en) * | 2005-11-30 | 2007-06-06 | Thomson Licensing | Method and apparatus for providing a stable clock signal |
| CN101521565A (en) * | 2008-02-26 | 2009-09-02 | 华为技术有限公司 | Main/standby system clock seamless switching method, device and communication equipment |
| CN102281063A (en) * | 2010-06-10 | 2011-12-14 | 中兴通讯股份有限公司 | Method and device for adjusting frequencies |
| CN101902321B (en) * | 2010-08-13 | 2014-11-05 | 中兴通讯股份有限公司 | Clock management method and system |
| CN102445953B (en) * | 2010-09-30 | 2016-08-03 | 重庆重邮信科通信技术有限公司 | A kind of method of adjustment of embedded device clock source |
| CN103258560B (en) * | 2012-02-20 | 2015-09-23 | 北京兆易创新科技股份有限公司 | A kind of serial interface flash memory and clock multiplier circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1589425A (en) * | 2001-11-15 | 2005-03-02 | 模拟设备股份有限公司 | Glitch-free clock select switching |
| CN102314208A (en) * | 2010-06-30 | 2012-01-11 | 重庆重邮信科通信技术有限公司 | Method and device for dynamically adjusting frequency and voltage of embedded equipment |
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