CN203071658U

CN203071658U - Intelligent substation link redundancy sampling value switching circuit

Info

Publication number: CN203071658U
Application number: CN2013200630967U
Authority: CN
Inventors: 赵燕茹; 杨臻; 周纬; 莫娟; 李力; 文继峰; 吕航; 朱晓彤; 李广华
Original assignee: China Electric Power Research Institute Co Ltd CEPRI; NR Electric Co Ltd
Current assignee: China Electric Power Research Institute Co Ltd CEPRI; NR Electric Co Ltd
Priority date: 2013-02-04
Filing date: 2013-02-04
Publication date: 2013-07-17
Anticipated expiration: 2023-02-04

Abstract

The utility model discloses an intelligent substation link redundancy sampling value switching circuit, comprising two DSP plugins and a backplane differential bus, wherein the data exchange between the two DSP plugins is realized through the backplane differential bus. According to the link control, the data can be either transmitted from an FPGA of any DSP plugin to the high-speed backplane differential bus through an LVDS chip, then transmitted to an LVDS chip of the other DSP plugin, then transmitted to a corresponding FPGA, and finally written into a logic operation DSP processor via the FPGA through a PPI high-speed synchronous parallel interface, thereby finishing the data exchange. The utility model can realize the online seamless switching of the sampling value under the condition of sampling value link redundancy, and can ensure that the transmission reliability of the sampling value data is not affected when any link fails.

Description

A kind of intelligent substation link redundancy sampled value commutation circuit

Technical field

The utility model belongs to the intelligent substation technical field, particularly a kind of intelligent substation link redundancy sampled value commutation circuit.

Background technology

The application of intelligent substation has been experienced from simple to process complicated, that promote from the pilot project to the small lot along with the continuous development of the through engineering approaches of intelligent substation correlation technique is promoted.

Using relevant communication service with relaying protection in the intelligent substation mainly is GOOSE service and SV service, wherein the GOOSE service is mainly used in the switching value transmission between process layer and the bay device, mainly comprise contents such as protection is tripped, startup is malfunctioning, circuit breaker information is obtained, also can finish the less demanding analog quantity transmission of a small amount of real-time, mainly be that the function of measure and control device is used; The SV service mainly is to obtain sampled value for bay device.GOOSE and SV serve by comparison, and the SV real-time requires very high, and communication flows is also very big, and from realizing that the realization threshold of GOOSE is lower, this has also just caused the GOOSE service, and service is applied in the intelligent substation early than SV.Early stage SV uses and substantially adopts networking mode, at first is that GOOSE and SV branch is opened the application mode of networking, progressively develops into the application mode that GOOSE and SV merge networking.

The engineering of GOOSE and SV is used and is attempted effectively having promoted the application of intelligent substation through engineering approaches; simultaneously; enforcement along with the intelligent substation pilot project; the engineering application level of GOOSE and SV is also improving constantly; but during also expose some problems, relatively distinct issues are exactly the decline of the reliability of relaying protection system.

The intelligent substation several times based on GOOSE and SV networking application in state reticular tissue is concentrated in the test; find that more problem has appearred in the SV service under the networking applicable cases; the degree of perfection that is each producer's device on the one hand is not enough; show on the one hand in addition that the SV service also has a lot of problems not solved at all under the networking applicable cases; seriously influenced the reliability of relaying protection system, these problems have directly caused the appearance of 441 standards " intelligent substation Protection Technology standards ".

State's net " intelligent substation Protection Technology standard " has been determined the implementation of protection equipment " Direct Sampling, directly tripping operation "; directly adopt straight jumping mode and fundamentally avoided the exchanges data problem of stationary problem and the switch of SV sampled data; this scheme does not rely on network; can avoid a series of problems because using switch to bring; and adopt and directly to adopt the mode sample-synchronous and finish at IED equipment; do not rely on the lock-out pulse in clock source, so overall technology performance and security reliability height.But for striding equipment (as bus protection) at interval, for realizing " Direct Sampling, directly tripping operation ", need provide a large amount of sampled value and GOOSE interfaces, the immediate problem that brings is that protection light mouth is many, and equipment power dissipation and caloric value are big, the probability of malfunction height.For many at interval application scenarios, bus protection may need to adopt distributed schemes, and the problem of bringing is the communication link that has increased main frame and handset, the global reliability of influence protection.

Technical scheme from intelligent substation, no matter be existing point-to-point application mode, or dualization network mode at a specified future date, all must take into full account the unusual possibility of link, and prevent under the single link abnormal conditions, the function of device is not affected, and is one of the key problem that need consider of intelligent substation process layer integration mode.

The utility model content

The purpose of this utility model is to provide a kind of intelligent substation link redundancy sampled value commutation circuit, and the online seamless switching that it can realize sampled value guarantees that the transmission reliability of arbitrary link failure situation down-sampled values data is unaffected.

In order to reach above-mentioned purpose, solution of the present utility model is:

A kind of intelligent substation link redundancy sampled value commutation circuit, comprise two blocks of DSP plug-in units and backboard differential bus, first block of DSP plug-in unit comprises 100,000,000 SFP optical modules, PHY, a FPGA and a DSP, described 100,000,000 SFP optical modules are converted to 100,000,000 differential electric signal with 100,000,000 light signals of outside input, send to PHY then; Described PHY sends to FPGA with data by RMII Ethernet high-speed interface again through after the inner encoding and decoding; Described FPGA carries out data link with aforementioned decoded data and resolves and decoded packet is stored among the inner FIFO; Simultaneously, DSP reads in the DDR of this DSP by EPPI synchronous high-speed interface with valid data, and sends to a FPGA; Described second block of DSP plug-in unit includes interconnective the 2nd FPGA and the 2nd DSP, and described the 2nd FPGA connects a FPGA by the backboard differential bus, sends to the sampled data of a FPGA with a synchronous DSP.

After adopting such scheme, the utility model is under sampled value link redundancy situation, it no matter is point-to-point and the networking link redundancy, or dualization network redundancy mode, all can realize the online seamless switching of sampled value, guarantee that the transmission reliability of arbitrary link failure situation down-sampled values data is unaffected.

Description of drawings

Fig. 1 is structured flowchart of the present utility model.

Embodiment

Below with reference to accompanying drawing, the technical solution of the utility model is elaborated.

The utility model provides a kind of intelligent substation link redundancy sampled value commutation circuit, comprises DSP plug-in unit 1, DSP plug-in unit 2 and backboard differential bus.

As shown in Figure 1, DSP plug-in unit 1 comprises 100,000,000 SFP optical modules, PHY, FPGA and DSP, described DSP plug-in unit 1 can be connected with the external fiber Ethernet by fiber optical transceiver, 100,000,000 light signals of outside input are converted to 100,000,000 differential electric signal by 100,000,000 SFP optical modules on the DSP plug-in unit 1, through 100,000,000 differential paths of capacitance-resistance coupling, the ethernet communication data are sent to ethernet physical layer special chip PHY then; Described ethernet physical layer special chip PHY will receive that through after the inner encoding and decoding data of link layer (MAC) send to field programmable gate array chip FPGA by RMII Ethernet high-speed interface; Described field programmable gate array chip FPGA carries out data link with decoded data and resolves and decoded packet is stored among the internal data buffer queue FIFO; Simultaneously, digital processor chip DSP is read in the external sync memory DDR of digital processor chip DSP by EPPI synchronous high-speed interface with valid data, finishes storage and handles.

Described DSP plug-in unit 2 includes interconnective FPGA and DSP, in order to guarantee that the DSP in the DSP plug-in unit 2 can receive same data content, DSP in the DSP plug-in unit 1 can send to field programmable gate array chip FPGA by the EPPI interface with sampled data, core bus controller among the FPGA can be collected these data, and passes through the backboard differential bus synchronously to the FPGA in the DSP plug-in unit 2.The core bus controller of FPGA in the DSP plug-in unit 2 can receive and insert data buffering formation FIFO with these data, reads for this plate DSP, and the DSP on the DSP plug-in unit 2 just can carry out processing such as interpolation, calculating to sampled value subsequently.

DSP in the DSP plug-in unit 1 writes FPGA by EPPI synchronous high-speed interface with data, and FPGA is connected to the LVDS differential driver of this plate by high speed serial port, and the output of the LVDS differential driver between the different integrated circuit boards directly links to each other.

Can be transferred to the backboard differential bus through the LVDS chip from the FPGA of any DSP plug-in unit according to link control data, and then be transferred to the LVDS chip of another DSP plug-in unit, and then be transferred to corresponding FPGA, final FPGA writes DSP by EPPI synchronous high-speed interface with data, finishes exchanges data.

Two blocks of DSP plug-in units connect by core bus, can be from a DSP plug-in unit real-time transmission data to another one DSP plug-in unit according to link control data.

In the present embodiment, the ethernet physical layer special chip in the DSP plug-in unit 1 adopts 88E3082, and field programmable gate array chip adopts XC6SLX25, and fiber optical transceiver adopts GTLS-1303-02MIL, and dsp chip adopts ADSP-BF548.

Need to prove that the above embodiment has only expressed execution mode of the present utility model, it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model claim.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the utility model design, can also make some distortion and improvement, these all belong to protection range of the present utility model.Therefore, the protection range of the utility model patent should be as the criterion with claims.

Claims

1. intelligent substation link redundancy sampled value commutation circuit, it is characterized in that: comprise two blocks of DSP plug-in units and backboard differential bus, first block of DSP plug-in unit comprises 100,000,000 SFP optical modules, PHY, a FPGA and a DSP, described 100,000,000 SFP optical modules are converted to 100,000,000 differential electric signal with 100,000,000 light signals of outside input, send to PHY then; Described PHY sends to FPGA with data by RMII Ethernet high-speed interface again through after the inner encoding and decoding; Described FPGA carries out data link with aforementioned decoded data and resolves and decoded packet is stored among the inner FIFO; Simultaneously, DSP reads in the DDR of this DSP by EPPI synchronous high-speed interface with valid data, and sends to a FPGA; Described second block of DSP plug-in unit includes interconnective the 2nd FPGA and the 2nd DSP, and described the 2nd FPGA connects a FPGA by the backboard differential bus, sends to the sampled data of a FPGA with a synchronous DSP.