CN110442187A - System and method are limited for the clock of module - Google Patents

System and method are limited for the clock of module Download PDF

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Publication number
CN110442187A
CN110442187A CN201910728323.5A CN201910728323A CN110442187A CN 110442187 A CN110442187 A CN 110442187A CN 201910728323 A CN201910728323 A CN 201910728323A CN 110442187 A CN110442187 A CN 110442187A
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China
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module
clock
frequency
signal
functional
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CN201910728323.5A
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CN110442187B (en
Inventor
顾雪春
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Nanjing Semidrive Technology Co Ltd
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Nanjing Semidrive Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom

Abstract

A kind of clock limitation system and method for module, including clock source device and functional module;Further include: clock limiting mechanism;The clock source device is connected with functional module by clock limiting mechanism;The clock frequency that the clock limiting mechanism is used to run the functional module limits.The clock limiting mechanism includes frequency limit module and gated clock module;The frequency limit module and the gated clock module are communicated to connect with the clock source device;The gated clock module and the functional module communicate to connect;The frequency limit module is used for the signal come according to clock source device transmission, and the clock frequency for controlling the gated clock module with this to allow the functional module to run is limited.The unordered chaotic defect of clock frequency for effectively preventing the clock frequency that can not prevent client from allowing functional module acquirement outside allowed band come overclocking by software configuration in the prior art, usually functional module being run.

Description

System and method are limited for the clock of module
Technical field
The present invention relates to clock restriction technologies fields, are also related to the technical field of chip module, and in particular to one kind is directed to The clock of module limits system and method.
Background technique
With the development of semiconductor technology, the chip that different function more and more may be implemented is applied to such as hand In the electronic equipments such as machine, laptop, tablet computer.
The different modules being made of different circuit structures can be divided into according to function on same chips, these The module divided according to function is also referred to as functional module, and the running frequency of functional module different in same chips may Difference, but these functional modules may be from identical clock source.
In order to realize different running frequencies it is necessary to provide different clock frequencies to these different functional modules, And traditional mode is that the different frequency division coefficient of register configuration is controlled by software, with this obtain different clock frequencies to Different functional modules.But this clock frequency by software configuration is limited in clock frequency the highest of module operation It is more complicated and difficult in technology realization in frequency range.
And on the other hand, as an improvement, the different functional modules of same chips will realize different clock frequencies Rate, can be by the setting to the different curing modules as eFuse register, to be configured to for each functional module Different clock frequencies, it is thus achieved that the clock frequency that different function module allows to run is different;But such improvement, It can not still prevent client from allowing functional module to obtain the clock frequency outside allowed band come overclocking by software configuration, thus often The clock frequency for running functional module is unordered and chaotic.
Summary of the invention
To solve the above problems, the present invention provides a kind of clocks for module to limit system, effectively prevent existing It can not prevent client from allowing functional module to obtain clock frequency outside allowed band, usually come overclocking by software configuration in technology So that the defect that the clock frequency of functional module operation is unordered and chaotic.
A kind of solution of the clock limitation system for module in order to overcome the deficiencies in the prior art, the present invention provides Scheme, specific as follows:
A kind of clock limitation system for module, including clock source device and functional module;
Further include: clock limiting mechanism;
The clock source device is connected with functional module by clock limiting mechanism;
The clock frequency that the clock limiting mechanism is used to run the functional module limits.
The clock limiting mechanism includes frequency limit module and gated clock module;
The frequency limit module and the gated clock module are communicated to connect with the clock source device;
The gated clock module and the functional module communicate to connect;
The frequency limit module be used for according to the clock source device transmit come signal, when controlling the gate with this Clock module is limited come the clock frequency for allowing the functional module to run.
The frequency limit module includes curing module, frequency check module and frequency signal control module;
Solidify the limit value for being stored with the clock frequency for limiting the functional module operation in the curing module;
The frequency check module and the clock source device communicate to connect, the frequency check module also with the solidification Module communication connection, the frequency check module be used for according to the clock source device transmit come signal and the curing module The limit value for the clock frequency for being used to limit the functional module operation is transmitted to check frequency;
The frequency check module and the frequency signal control module communicate to connect, and the frequency check module can be Inspection result is sent in the frequency signal control module, allows the frequency signal control module output frequency control to believe with this Number;
The frequency signal control module and the gated clock module communicate to connect, and the frequency signal control module is just The frequency control signal can be sent to the gated clock module.
The curing module is eFuse register.
When the clock source device includes clock source, more than one clock division circuits and more than one benchmark Clock;
The input terminal of the clock source and all clock division circuits communicates to connect;
The quantity of the clock division circuits clock division electricity consistent and described with the quantity of the frequency limit module Road and the frequency limit module correspond, and the output end of the clock division circuits as functional clock is same to be corresponding to it The frequency limit module frequency check module and the gated clock module corresponding with the frequency limit module it is logical Letter connection, the quantity of the functional clock is consistent with the reference clock quantity and corresponds, the functional clock and with The corresponding reference clock be both connected in the same frequency check module;
The quantity of the frequency limit module also frequency limit consistent and described with the quantity of the gated clock module Module and the gated clock module correspond, and the frequency signal control module of the frequency limit module and limit with the frequency The corresponding gated clock module communication connection of molding block;
The quantity of the gated clock module gated clock module consistent and described with the quantity of the functional module with The functional module corresponds, and the gated clock module is communicated to connect with the corresponding functional module.
The method of the clock limitation system for module, including such as under type:
The clock frequency that the clock limiting mechanism runs the functional module limits.
The method that the clock frequency that the clock limiting mechanism runs the functional module is limited, comprising:
The frequency limit module according to the clock source device transmit come signal, the gated clock mould is controlled with this Block is limited come the clock frequency for allowing the functional module to run.
The frequency limit module according to the clock source device transmit come signal, the gated clock mould is controlled with this Block is come the method for allowing the clock frequency of the functional module operation to be limited, and steps are as follows:
Step 1: the frequency check module according to the clock source device transmission come signal and the curing module biography It is defeated come described examined for limiting the limit value of the clock frequency of functional module operation being checked frequency Come to an end fruit;
Step 2: the frequency check module is sent to inspection result in the frequency signal control module, allows institute with this State frequency signal control module output frequency control signal;
Step 3: the frequency control signal is sent to the gated clock module by the frequency signal control module;
Step 4: the gated clock module is just realized under the action of the frequency control signal to the functional module The limitation of the clock frequency of operation.
It include the clock source, more than one clock division circuits and more than one base in the clock source device Under conditions of punctual clock, the frequency limit module according to the clock source device transmit come signal, the door is controlled with this Control clock module includes the following steps: come the method for allowing the clock frequency of the functional module operation to be limited
Step 1-1: the curing module of the frequency limit module described in its storage for limiting the functional module The limit value of the clock frequency of operation is transferred to the frequency check module of the frequency limit module, which connects Whether the limit value for limiting the clock frequency of the functional module operation received is preset stale value, if it is Preset stale value, representing frequency limit module belonging to the frequency check module is failure, that is, the frequency limit Module will not enable, and allow for gated clock module corresponding with the frequency limit module in this way and do not turn off, so that the function Can module operation clock frequency and the clock signal sent out therewith by the clock division circuits that gated clock module is connected Frequency be consistent;
Step 1-2: if being not preset stale value, when which just receives the function being attached thereto The functional clock signal and reference clock signal that clock and the reference clock are sent respectively, then carry out frequency check, described Frequency check is exactly the frequency size of comparing function clock signal and the frequency size of reference clock signal;
Step 1-3: if the frequency size of the functional clock signal is lower than the frequency size of the reference clock signal Twice, the frequency limit module will not enable, and allow for gated clock module corresponding with the frequency limit module so not It can close, so that the clock frequency of functional module operation and the clock division circuits that is connected therewith by gated clock module The frequency for the clock signal sent out is consistent;
Step 1-4: if the frequency size of the functional clock signal is greater than or equal to the frequency of the reference clock signal Twice of rate size, the frequency limit module just enable;
Step 1-5: after the frequency limit module is enabled, the frequency limit module is just described for limiting according to described The limit value of the clock frequency of functional module operation generates the frequency control signal as gated clock module control signal, to function Energy clock is gated, and the limitation of the clock frequency to functional module operation is realized with this.
The frequency limit module in the step 1-5 just according to it is described for limit the functional module operation when The limit value of clock frequency generates the frequency control signal as gated clock module control signal, carries out door to functional clock signal Control includes the following steps: in the method for this limitation for realizing the clock frequency to functional module operation
Step 1-5-1: the frequency check module of the frequency limit module is with the frequency of function clock signal to reference clock Signal carries out sample count;
Step 1-5-2: when sample count values are less than or equal to the clock frequency for being used to limit the functional module operation Limit value when, which is less than or equal to this and is used to limit the functional module by the frequency check module runs The inspection result of limit value of clock frequency be sent in the frequency signal control module, allow the frequency signal control in this way Molding block output allow by frequency control signal;
Step 1-5-3: the frequency signal control module it is described allow by frequency control signal be sent to the door Control clock module, the gated clock module just according to this allow by frequency control signal allow functional module operation Clock frequency kept with the frequency of clock signal sent out therewith by the clock division circuits that gated clock module is connected Unanimously;
Step 1-5-4: when sample count values are greater than the restriction of the clock frequency for being used to limit the functional module operation When value, which is greater than this and is used to limit the clock frequency that the functional module is run by the frequency check module The inspection result of limit value is sent in the frequency signal control module, and frequency signal control module output is allowed to be prohibited in this way The frequency control signal only passed through;
Step 1-5-5: the frequency control signal that no thoroughfare is sent to the door by the frequency signal control module Clock module is controlled, the gated clock module just allows the functional module to run according to the frequency control signal that no thoroughfare is somebody's turn to do Clock frequency be separated by with the frequency for the clock signal sent out therewith by the clock division circuits that gated clock module is connected It is disconnected, allow the clock frequency of the functional module operation to be maintained at this for limiting the clock frequency of the functional module operation in this way Limit value defined by frequency range.
The invention has the benefit that
The reference clock frequency that the present invention enables to functional module to run limits more accurate, and uses more convenient, peace The clock frequency that the complete higher mode of property runs functional module is limited and is protected;The present invention can configure software error And the mistake for the clock frequency for causing functional module to run is protected, and keeps functional module operation safer.Meanwhile the present invention It can be more efficient, easily and efficiently prevent user using software mode come to functional module in the scene of Properties Control Illegal overclocking.
Detailed description of the invention
Fig. 1 is the overall structure figure that the clock for module of the invention limits system.
Fig. 2 is the structure chart of clock limiting mechanism of the invention.
Fig. 3 is the detailed structure view that the clock for module of the invention limits system, and n therein is positive integer, is indicated The number of component represented by text in its place box.
Fig. 4 is the partial process view for the method that the clock for module of the invention limits system.
Fig. 5 is the base of the invention under conditions of the limit value of the clock frequency run for limitation function module is 5 Clock signal (CLK_24MHZ), functional clock signal (CLK_Func), frequency control signal (Gating_signal) and The timing diagram of the clock signal (CLK_Func after gating) of functional module operation.
Specific embodiment
The present invention is described further below in conjunction with drawings and examples.
As Figure 1-Figure 5, system, including clock source device and functional module are limited for the clock of module;Function mould Block can be on the same chip, according to function division at the different functional modules being made of different circuit structures, these Functional module can be on a single die such as CPU, GPU, TIMER module, PWM module, I2C module or AUDIO module Such functional module.Further include: clock limiting mechanism;Clock source device is connected with functional module by clock limiting mechanism; The clock frequency that clock limiting mechanism is used to run functional module limits, and prevents client from passing through software configuration with this to surpass Frequency allows functional module to obtain the clock frequency outside allowed band, the nothing for the clock frequency for usually bringing functional module to run in this way Sequence and chaotic defect.Clock limiting mechanism includes frequency limit module and gated clock module;Frequency limit module and gate The clock signal input terminal of clock module is communicated to connect with clock source device;The clock signal output terminal of gated clock module with Functional module communication connection;Frequency limit module be used for according to clock source device transmission come signal, gated clock is controlled with this Module is limited come the clock frequency for allowing functional module to run.Thus function mould can be allowed with software in external client It, can be by the limitation of frequency limit module and gated clock module, finally before block obtains the clock frequency outside allowed band So that functional module operation clock frequency can orderly and will not overclocking.Frequency limit module includes curing module, frequency check Module and frequency signal control module;Solidify in curing module and is stored with the clock frequency for the operation of limitation function module Limit value;The limit value of the clock frequency run for limitation function module is used in frequency check module, as function The clock frequency of module operation defines value, the signal frequency that can thus allow frequency check module to judge that clock source device transmission comes Rate whether over range;Frequency check module and clock source device communicate to connect, frequency check module also with curing module communication link Connect, signal and the curing module transmission that frequency check module is used to be come according to clock source device transmission come for limitation function mould The limit value of the clock frequency of block operation checks frequency;Frequency check module and frequency signal control module communication link It connects, frequency check module can be sent to inspection result in frequency signal control module, allow frequency signal control module with this Output frequency controls signal;The clock output control terminal of frequency signal control module and gated clock module communicates to connect, frequency Signal control module can be sent to frequency control signal the clock output control terminal of gated clock module;Gated clock module It can be door control clock circuit, door control clock circuit is by a latch, one and Men Zucheng;Latch is equipped with an input terminal, a control End processed and an output end, input terminal constitute the clock signal input terminal of door control clock circuit, and control terminal constitutes gated clock The clock output control terminal of circuit;It sets with door there are two input terminal, an output end, with an input termination latch of door Output end, the input terminal of another input termination latch, output end constitute the clock signal output terminal of door control clock circuit. Curing module is eFuse register.Clock source device include clock source, more than one clock division circuits and more than one Reference clock;The input terminal of clock source and all clock division circuits communicates to connect;The quantity and frequency of clock division circuits Rate limits the quantity of module unanimously and clock division circuits and frequency limit module correspond, the clock as functional clock The output end of frequency dividing circuit with corresponding frequency limit module frequency check module and with the frequency limit module pair The gated clock module communication connection answered, the quantity of functional clock is consistent with reference clock quantity and corresponds, when function Clock and corresponding reference clock are both connected in the same frequency check module;The quantity of frequency limit module also and gate The quantity of clock module is consistent and frequency limit module and gated clock module correspond, the frequency letter of frequency limit module The communication connection of the clock output control terminal of number control module and gated clock module corresponding with the frequency limit module;When gate And the quantity of functional module is consistent and gated clock module and functional module correspond, gated clock mould for the quantity of clock module The clock signal output terminal of block is communicated to connect with corresponding functional module.
For the method for the clock limitation system of module, including such as under type:
The clock frequency that clock limiting mechanism runs functional module limits, and prevents client from passing through software configuration with this Carrying out overclocking allows functional module to obtain the clock frequency outside allowed band, the clock frequency for usually bringing functional module to run in this way Unordered and chaotic defect.
The method that the clock frequency that clock limiting mechanism runs functional module is limited, comprising:
Frequency limit module according to clock source device transmission come signal, gated clock module is controlled with this to allow function mould The clock frequency of block operation is limited.Thus functional module can be allowed to obtain with software in external client is allowing model Before enclosing outer clock frequency, finally functional module can be transported by the limitation of frequency limit module and gated clock module Capable clock frequency meeting is orderly and will not overclocking.
Frequency limit module according to clock source device transmission come signal, gated clock module is controlled with this to allow function mould The method that the clock frequency of block operation is limited, steps are as follows:
Step 1: frequency check module according to clock source device transmission come signal and curing module transmission come be used for limit The limit value of the clock frequency of functional module operation processed obtains inspection result to be checked frequency;
Step 2: frequency check module is sent to inspection result in frequency signal control module, allows frequency signal control with this Molding block output frequency controls signal;
Step 3: frequency signal control module controls the clock output that frequency control signal is sent to gated clock module End;
Step 4: gated clock module just realizes the clock frequency run to functional module under the action of frequency control signal The limitation of rate.
It include clock source, more than one clock division circuits and more than one reference clock in clock source device Under the conditions of, frequency limit module according to clock source device transmission come signal, gated clock module is controlled with this to allow function mould The method that the clock frequency of block operation is limited, includes the following steps:
Step 1-1: the clock frequency that for limitation function module runs of the curing module of frequency limit module its storage The limit value of rate is transferred to the frequency check module of the frequency limit module, and what which received is used to limit Whether the limit value of the clock frequency of functional module operation processed is preset stale value, and the stale value is usually set as 0, if For preset stale value, representing frequency limit module belonging to the frequency check module is failure, that is, frequency limit mould Block will not enable, and allow for gated clock module corresponding with the frequency limit module in this way and do not turn off, that is, the gate Clock module will not separate the signal of its clock division circuits corresponding with the frequency limit module, and when can convey the gate The corresponding functional module of clock module can continuously receive the signal of the clock division circuits, so that the clock frequency of functional module operation Rate is consistent with the frequency for the clock signal sent out therewith by the clock division circuits that gated clock module is connected;
Step 1-2: if not being preset stale value, the frequency check module just receive the functional clock that is attached thereto and The functional clock signal and reference clock signal that reference clock is sent respectively, then carry out frequency check, frequency check is exactly According to nyquist sampling theorem, nyquist sampling theorem is exactly: to twice of frequency of the function of being lower than reference clock signal The frequency of clock signal can not be sampled correctly, and the frequency size of comparing function clock signal and the frequency of reference clock signal are big It is small;
Step 1-3: if the frequency size of functional clock signal is lower than twice of frequency size of reference clock signal, also It is to be unsatisfactory for nyquist sampling theorem, frequency limit module will not enable, and allow for so corresponding with the frequency limit module Gated clock module do not turn off, that is, the gated clock module will not be its clock corresponding with the frequency limit module The signal of frequency dividing circuit separates, and can convey the corresponding functional module of gated clock module can continuously receive the clock division The signal of circuit, so that the clock frequency of functional module operation and the clock division circuits that is connected therewith by gated clock module The frequency for the clock signal sent out is consistent;
Step 1-4: if the frequency size of functional clock signal is greater than or equal to the frequency size two of reference clock signal Times, that is, nyquist sampling theorem is met, frequency limit module just enables;
Step 1-5: after frequency limit module is enabled, frequency limit module just according to for the operation of limitation function module when The limit value of clock frequency generates the frequency control signal as gated clock module control signal, gates to functional clock, The limitation of the clock frequency to functional module operation is realized with this.
Frequency limit module in step 1-5 is just produced according to the limit value of the clock frequency for the operation of limitation function module The raw frequency control signal as gated clock module control signal, is gated functional clock signal, is realized with this to function The method of the limitation of the clock frequency of energy module operation, includes the following steps:
Step 1-5-1: in general, this is used for the meaning of the limit value of the clock frequency of limitation function module operation are as follows: This is used for the limit value of the clock frequency of limitation function module operation multiplied by the frequency of the corresponding reference clock signal of the functional clock The product value of rate size is exactly the upper limit value of the clock frequency of functional module operation;
If the frequency size of reference clock is 24MHZ, the frequency size of functional clock is 1GHZ, and is used for limitation function mould When the limit value of the clock frequency of block operation is 5, the frequency check module of the frequency limit module with the frequency check module The reference clock that the frequency pair of the functional clock signal of the functional clock of communication connection is communicated to connect with the frequency check module Reference clock signal carries out sample count;
Step 1-5-2: when sample count values are less than or equal to the limit for the clock frequency that limitation function module is run Definite value, that is, when 5, frequency check module the sample count values be less than or equal to this for limitation function module run when The inspection result of the limit value of clock frequency is sent in the frequency signal control module communicated to connect with the frequency check module, this Sample come allow frequency signal control module output allow by frequency control signal, this allow by frequency control signal Value can be set as 1;
Step 1-5-3: the frequency signal control module allow by frequency control signal be sent to and the frequency believe The clock output control terminal of the gated clock module of number control module communication connection, gated clock module just allow to pass through according to this Frequency control signal come the clock frequency that allows functional module to run and the clock division that is connected therewith by gated clock module The frequency for the clock signal that circuit is sent out is consistent;
Step 1-5-4: when sample count values be greater than this for limitation function module operation clock frequency limit value, When being exactly 5, which is greater than the restriction for the clock frequency that limitation function module is run by frequency check module The inspection result of value is sent to the frequency signal control module of frequency check module communication connection, allows the frequency in this way The signal control module output frequency control signal that no thoroughfare, the value for being somebody's turn to do the frequency control signal that no thoroughfare can be set as 0;
Step 1-5-5: the frequency signal control module is sent to the frequency control signal that no thoroughfare to be believed with the frequency The clock output control terminal of the gated clock module of number control module communication connection, gated clock module is just according to should no thoroughfare Frequency control signal come the clock frequency that allows functional module to run and the clock division that is connected therewith by gated clock module The frequency for the clock signal that circuit is sent out is blocked, and the clock frequency for allowing functional module to run in this way is maintained at this and is used to limit Under the upper limit value of the clock frequency of functional module operation defined by the limit value of the clock frequency of functional module operation In frequency range, that is, the average value of clock frequency of functional module operation can be reduced to 5*24MHZ=from 1GHZ 120MHZ, to be limited in normal range.In common chip system, the same clock source passes through different frequency dividings Circuit obtains the clock of different frequency, gives different functional modules.All moulds can be caused by limiting the frequency of clock source The clock of block changes, while complexity is higher, and limits system with clock frequency provided by the invention, and flexibility is high, design Complexity is low, while safety is relatively high.
The present invention is described in a manner of being illustrated with embodiment above, it will be understood by those of skill in the art that this It is open to be not limited to embodiments described above, in the case of without departing from the scope of the present invention, it can make a variety of changes, change And replacement.

Claims (10)

1. a kind of clock for module limits system, comprising:
Clock source device and functional module;
It is characterized by further comprising: clock limiting mechanism;
The clock source device is connected with functional module by clock limiting mechanism;
The clock frequency that the clock limiting mechanism is used to run the functional module limits.
2. the clock according to claim 1 for module limits system, which is characterized in that the clock limiting mechanism packet Include frequency limit module and gated clock module;
The frequency limit module and the gated clock module are communicated to connect with the clock source device;
The gated clock module and the functional module communicate to connect;
The frequency limit module be used for according to the clock source device transmit come signal, the gated clock mould is controlled with this Block is limited come the clock frequency for allowing the functional module to run.
3. the clock according to claim 2 for module limits system, which is characterized in that the frequency limit module packet Include curing module, frequency check module and frequency signal control module;
Solidify the limit value for being stored with the clock frequency for limiting the functional module operation in the curing module;
The frequency check module and the clock source device communicate to connect, the frequency check module also with the curing module Communication connection, the frequency check module be used for according to the clock source device transmission come signal and the curing module transmission That comes described checks frequency for limiting the limit value of the clock frequency of functional module operation;
The frequency check module and the frequency signal control module communicate to connect, and the frequency check module can be inspection As a result it is sent in the frequency signal control module, allows the frequency signal control module output frequency to control signal with this;
The frequency signal control module and the gated clock module communicate to connect, and the frequency signal control module can handle The frequency control signal is sent to the gated clock module.
4. the clock according to claim 3 for module limits system, which is characterized in that the curing module is EFuse register.
5. the clock according to claim 1 for module limits system, which is characterized in that the clock source device includes Clock source, more than one clock division circuits and more than one reference clock;
The input terminal of the clock source and all clock division circuits communicates to connect;
The quantity of the clock division circuits clock division circuits consistent and described with the quantity of the frequency limit module with The frequency limit module corresponds, and the output end of the clock division circuits as functional clock is the same as corresponding institute State the frequency check module and the gated clock module communication link corresponding with the frequency limit module of frequency limit module It connects, the quantity of the functional clock is consistent with the reference clock quantity and corresponds, the functional clock and right therewith The reference clock answered is both connected in the same frequency check module;
The quantity of the frequency limit module also frequency limit module consistent and described with the quantity of the gated clock module With the gated clock module correspond, the frequency signal control module of the frequency limit module and with the frequency limit mould The corresponding gated clock module communication connection of block;
The quantity of the gated clock module gated clock module consistent and described with the quantity of the functional module with it is described Functional module corresponds, and the gated clock module is communicated to connect with the corresponding functional module.
6. a kind of method of the clock limitation system for module, which is characterized in that including such as under type:
The clock frequency that the clock limiting mechanism runs the functional module limits.
7. the method for the clock limitation system according to claim 6 for module, which is characterized in that the clock limitation The method that the clock frequency that mechanism runs the functional module is limited, comprising:
The signal that the frequency limit module is come according to clock source device transmission controls the gated clock module with this The clock frequency of the functional module operation is allowed to be limited.
8. the method for the clock limitation system according to claim 7 for module, which is characterized in that the frequency limit The signal that module is come according to clock source device transmission controls the gated clock module with this to allow functional module fortune The method that capable clock frequency is limited, steps are as follows:
Step 1: the frequency check module according to the clock source device transmission come signal and the curing module transmit come Described obtain checking knot to check frequency for limiting the limit value of the clock frequency of functional module operation Fruit;
Step 2: the frequency check module is sent to inspection result in the frequency signal control module, allows the frequency with this Rate signal control module output frequency controls signal;
Step 3: the frequency control signal is sent to the gated clock module by the frequency signal control module;
Step 4: the gated clock module is just realized under the action of the frequency control signal and is run to the functional module Clock frequency limitation.
9. the method for the clock limitation system according to claim 7 for module, which is characterized in that in the clock source It is described under conditions of device includes the clock source, more than one clock division circuits and more than one reference clock Frequency limit module according to the clock source device transmit come signal, the gated clock module is controlled with this to allow the function The method that the clock frequency of energy module operation is limited, includes the following steps:
Step 1-1: the curing module of the frequency limit module described in its storage for limiting the functional module running The limit value of clock frequency be transferred to the frequency check module of the frequency limit module, which receives The limit value for limiting the clock frequency of functional module operation whether be preset stale value, if it is default Stale value, representing frequency limit module belonging to the frequency check module is failure, that is, the frequency limit module It will not enable, allow for gated clock module corresponding with the frequency limit module in this way and do not turn off, so that the function mould Clock frequency and the frequency for the clock signal sent out therewith by the clock division circuits that gated clock module is connected of block operation Rate is consistent;
Step 1-2: if not being preset stale value, the frequency check module just receive the functional clock that is attached thereto and The functional clock signal and reference clock signal that the reference clock is sent respectively, then carry out frequency check, the frequency Check to be exactly the frequency size of comparing function clock signal and the frequency size of reference clock signal;
Step 1-3: if the frequency size of the functional clock signal is lower than twice of frequency size of the reference clock signal, The frequency limit module will not enable, and allowing for gated clock module corresponding with the frequency limit module in this way will not close It closes, so that the clock frequency of functional module operation is sent out with the clock division circuits being connected therewith by gated clock module The frequency for the clock signal come is consistent;
Step 1-4: if the frequency that the frequency size of the functional clock signal is greater than or equal to the reference clock signal is big Twice small, the frequency limit module just enables;
Step 1-5: after the frequency limit module is enabled, the frequency limit module is just according to described for limiting the function The limit value of the clock frequency of module operation generates the frequency control signal as gated clock module control signal, when to function Clock is gated, and the limitation of the clock frequency to functional module operation is realized with this.
10. the method for the clock limitation system according to claim 9 for module, which is characterized in that the step 1-5 In limit value of the frequency limit module just according to described for limiting the clock frequency of the functional module operation generate As the frequency control signal of gated clock module control signal, functional clock signal is gated, is realized with this to described The method of the limitation of the clock frequency of functional module operation, includes the following steps:
Step 1-5-1: the frequency check module of the frequency limit module is with the frequency of function clock signal to reference clock signal Carry out sample count;
Step 1-5-2: when sample count values are less than or equal to the limit of the clock frequency for being used to limit the functional module operation When definite value, the frequency check module the sample count values be less than or equal to this be used to limit the functional module runs when The inspection result of the limit value of clock frequency is sent in the frequency signal control module, and the frequency signal is allowed to control mould in this way Block output allow by frequency control signal;
Step 1-5-3: the frequency signal control module it is described allow by frequency control signal be sent to the gate when Clock module, the gated clock module just according to this allow by frequency control signal come allow functional module operation when Clock frequency is consistent with the frequency for the clock signal sent out therewith by the clock division circuits that gated clock module is connected;
Step 1-5-4: when sample count values are greater than the limit value of the clock frequency for being used to limit the functional module operation, The frequency check module is greater than the sample count values restriction of the clock frequency for being used to limit the functional module operation The inspection result of value is sent in the frequency signal control module, and frequency signal control module output is allowed to forbid leading in this way The frequency control signal crossed;
Step 1-5-5: when the frequency control signal that no thoroughfare is sent to the gate by the frequency signal control module Clock module, the gated clock module just according to should the frequency control signal that no thoroughfare come allow the functional module runs when Clock frequency and the frequency for the clock signal sent out therewith by the clock division circuits that gated clock module is connected are blocked, this Sample allows the clock frequency of the functional module operation to be maintained at this for limiting the limit for the clock frequency that the functional module is run In frequency range defined by definite value.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113055099A (en) * 2019-12-26 2021-06-29 大唐移动通信设备有限公司 Detection method and device of clock gating module
CN116306409A (en) * 2023-05-22 2023-06-23 南京芯驰半导体科技有限公司 Chip verification method, device, equipment and storage medium

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1202997A (en) * 1995-09-29 1998-12-23 艾利森电话股份有限公司 Operation and maintenance of clock distribution networks having redundancy
CN1490688A (en) * 2002-10-17 2004-04-21 深圳市中兴通讯股份有限公司上海第二 Timing system and method thereof
CN1613186A (en) * 2002-01-08 2005-05-04 摩托罗拉公司 Method and apparatus for clock generation using reference signal selection
CN101101504A (en) * 2007-08-16 2008-01-09 中国科学院计算技术研究所 Processor and its frequency-reducing device and method
US20100023793A1 (en) * 2003-11-13 2010-01-28 Janzen Leel S Apparatus and method for generating a delayed clock signal
CN102684654A (en) * 2012-04-20 2012-09-19 华为技术有限公司 Clock signal generator
CN103499739A (en) * 2013-09-25 2014-01-08 浪潮电子信息产业股份有限公司 Frequency measurement method based on FPGA
CN103580684A (en) * 2012-08-07 2014-02-12 国民技术股份有限公司 Chip clock signal generation circuit and chip system
CN106992770A (en) * 2016-01-21 2017-07-28 华为技术有限公司 Clock circuit and its method for transmitting clock signal

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1202997A (en) * 1995-09-29 1998-12-23 艾利森电话股份有限公司 Operation and maintenance of clock distribution networks having redundancy
CN1613186A (en) * 2002-01-08 2005-05-04 摩托罗拉公司 Method and apparatus for clock generation using reference signal selection
CN1490688A (en) * 2002-10-17 2004-04-21 深圳市中兴通讯股份有限公司上海第二 Timing system and method thereof
US20100023793A1 (en) * 2003-11-13 2010-01-28 Janzen Leel S Apparatus and method for generating a delayed clock signal
CN101101504A (en) * 2007-08-16 2008-01-09 中国科学院计算技术研究所 Processor and its frequency-reducing device and method
CN102684654A (en) * 2012-04-20 2012-09-19 华为技术有限公司 Clock signal generator
CN103580684A (en) * 2012-08-07 2014-02-12 国民技术股份有限公司 Chip clock signal generation circuit and chip system
CN103499739A (en) * 2013-09-25 2014-01-08 浪潮电子信息产业股份有限公司 Frequency measurement method based on FPGA
CN106992770A (en) * 2016-01-21 2017-07-28 华为技术有限公司 Clock circuit and its method for transmitting clock signal

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113055099A (en) * 2019-12-26 2021-06-29 大唐移动通信设备有限公司 Detection method and device of clock gating module
CN113055099B (en) * 2019-12-26 2022-03-25 大唐移动通信设备有限公司 Detection method and device of clock gating module
CN116306409A (en) * 2023-05-22 2023-06-23 南京芯驰半导体科技有限公司 Chip verification method, device, equipment and storage medium
CN116306409B (en) * 2023-05-22 2023-08-08 南京芯驰半导体科技有限公司 Chip verification method, device, equipment and storage medium

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