CN113055099A - Detection method and device of clock gating module - Google Patents
Detection method and device of clock gating module Download PDFInfo
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Abstract
The embodiment of the invention provides a method and a device for detecting a clock gating module, which are used for realizing automatic detection of the clock gating module. Firstly, acquiring a working signal and a first clock gating switch state of a functional module in a base station, then determining a current working scene of the base station, and determining a working model corresponding to the working scene; secondly, determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and finally, determining the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state. The method can realize automatic detection of the clock gating module, not only improves the speed and accuracy of detection, but also can avoid the cost of manual detection.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for detecting a clock gating module.
Background
With the increase of the number of communication antennas and the variety of services, the design of the base station chip tends to be complicated, and the number of modules inside the base station chip is increased, which makes the requirement for the flexibility of the physical transmission channel inside the base station chip higher. In order to further reduce the power consumption of the base station on the basis of not influencing the operation of the base station, the current communication field can shut off part of the non-operating physical transmission channels through a clock gating technology.
Because each functional module of the base station chip has the clock to which the functional module belongs, the clock can control the corresponding functional module to work. The clock gating module can acquire a working signal of the functional module, judge whether the functional module is in a working state or not through the working signal, and close the clock of the functional module if the functional module is in a non-working state, so that the functional module stops working, and the power consumption of the base station chip is reduced. Therefore, whether the function of the clock gating module is effective or not plays a crucial role in reducing the power consumption of the base station chip and ensuring the normal work of the base station chip.
At present, in order to check the functional validity of a clock gating module, it is necessary to first obtain the waveform of a working signal of the functional module through simulation by a simulation tool, and then manually determine whether the clock gating module is valid by observing the waveform of the working signal with human eyes. In addition, as the base station chip is complicated, the number of functional modules inside the base station chip is increased, so that the number of detected signals is obviously increased, and the labor cost is increased.
Disclosure of Invention
The application provides a detection method and a detection device of a clock gating module, which are used for realizing automatic detection of the clock gating module.
The embodiment of the invention provides the following specific technical scheme:
in a first aspect, an embodiment of the present application provides a method and an apparatus for detecting a clock gating module, where the method specifically includes the following steps:
acquiring a working signal of a functional module in a base station and a first clock gating switch state, wherein the first clock gating switch state is the clock gating switch state of the functional module determined by the clock gating module according to the working signal of the functional module;
determining a current working scene of the base station, and determining a working model corresponding to the working scene, wherein the working model is used for representing the corresponding relation between a working signal of a functional module in the base station and the state of a clock gating switch of the functional module;
determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model;
and determining the detection state of the clock gating module according to the state of the first clock gating switch and the state of the second clock gating switch.
In a possible implementation manner, determining, according to the working model, a second clock gating switch state of the functional module corresponding to the working signal of the functional module specifically includes:
modifying the signal identifier of the working signal of the functional module from the first signal identifier to the second signal identifier according to the preset corresponding relation between the first signal identifier and the second signal identifier; wherein the first signal identifier is a true signal identifier and the second signal identifier is a signal identifier of the working signal in the working model;
and inputting the working signal of the functional module with the signal identifier as the second signal identifier into the working model to obtain the state of the second clock gating switch.
In one possible implementation manner, determining the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state further includes:
when the first clock gating switch state is the same as the second clock gating switch state, determining that the detection state of the clock gating module is normal;
and when the first clock gating switch state and the second clock gating switch state are different, determining that the detection state of the clock gating module is abnormal.
In one possible implementation manner, the operation signal of the functional module is at least one or a combination of the following: clock input signal, channel enable signal, software clock selection signal, hardware clock enable signal.
In a second aspect, an embodiment of the present application provides a detection apparatus, including:
the communication unit is used for acquiring a working signal of a functional module in a base station and a first clock gating switch state, wherein the first clock gating switch state is the clock gating switch state of the functional module determined by the clock gating module according to the working signal of the functional module;
the processing unit is used for determining the current working scene of the base station and determining a working model corresponding to the working scene, wherein the working model is used for representing the corresponding relation between the working signal of a functional module in the base station and the clock gating switch state of the functional module;
the clock gating control module is also used for determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and determining the detection state of the clock gating module according to the state of the first clock gating switch and the state of the second clock gating switch.
In a possible implementation manner, the processing unit determines, according to the working model, a second clock gating switch state of the functional module corresponding to the working signal of the functional module, and is specifically configured to:
modifying the signal identifier of the working signal of the functional module from the first signal identifier to the second signal identifier according to the preset corresponding relation between the first signal identifier and the second signal identifier; wherein the first signal identifier is a true signal identifier and the second signal identifier is a signal identifier of the working signal in the working model;
and inputting the working signal of the functional module with the signal identifier as the second signal identifier into the working model to obtain the state of the second clock gating switch.
In one possible implementation manner, the determining, by the processing unit, the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state includes:
when the first clock gating switch state is the same as the second clock gating switch state, determining that the detection state of the clock gating module is normal;
and when the first clock gating switch state and the second clock gating switch state are different, determining that the detection state of the clock gating module is abnormal.
In one possible implementation manner, the operation signal of the functional module is at least one or a combination of the following: clock input signal, channel enable signal, software clock selection signal, hardware clock enable signal.
In a third aspect, an embodiment of the present application provides a computer-readable storage medium, including: the computer-readable storage medium has stored thereon a computer program which, when run on an electronic device, causes the electronic device to perform any one of the possible implementations of any of the above aspects.
In a fourth aspect, embodiments of the present application provide a computer program comprising instructions that, when executed on a computer, cause the computer to perform any one of the possible implementations of any one of the above aspects.
In a fifth aspect, the present application provides a chip, where the chip is configured to read a computer program stored in a memory, and perform any one of the possible implementations of the foregoing aspects.
In the technical scheme of the embodiment of the application, firstly, a working signal of a functional module in a base station and a first clock gating switch state are obtained; then, determining the current working scene of the base station, and determining a working model corresponding to the working scene; secondly, determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and finally, determining the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state. The method can realize automatic detection of the clock gating module, not only improves the speed and accuracy of detection, but also can avoid the cost of manual detection.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a base station chip according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for detecting a clock gating module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a working model in an embodiment of the invention;
FIG. 4 is a diagram of a partially complete model in an embodiment of the invention;
fig. 5 is a schematic diagram of a detection apparatus of a clock gating module according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a detection device of a clock gating module according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a detection method of a clock gating module, which is used for realizing automatic detection of the clock gating module. The method and the device are based on the same inventive concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.
In the technical scheme of the embodiment of the application, firstly, a detection device acquires a working signal of a functional module in a base station and a first clock gating on-off state, wherein the first clock gating on-off state is the clock gating on-off state of the functional module determined by the clock gating module according to the working signal of the functional module; then, the detection device determines the current working scene of the base station and determines a working model corresponding to the working scene, wherein the working model is used for representing the corresponding relation between the working signal of a functional module in the base station and the clock gating switch state of the functional module; secondly, the detection device determines a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and finally, the detection device determines the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state. The method can realize automatic detection of the clock gating module, not only improves the speed and accuracy of detection, but also can avoid the cost of manual detection.
Some terms in the embodiments of the present application will be explained below to facilitate understanding by those skilled in the art.
1. A Base Station (BS), also referred to as a network device, is a device deployed in a radio access network to provide wireless communication functions.
Currently, some examples of base stations are: a gbb, an NR base station, an evolved Node B (eNB), a Transmission Reception Point (TRP), a Radio Network Controller (RNC), a Node B (NB), a Base Station Controller (BSC), a Base Transceiver Station (BTS), a home base station (e.g., home evolved Node B, or home Node B, HNB), or a Base Band Unit (BBU), etc.
In addition, in a network structure, the base station may include a Centralized Unit (CU) node and a Distributed Unit (DU) node. The structure separates the protocol layers of the eNB in a Long Term Evolution (LTE) system, the functions of part of the protocol layers are controlled in the CU in a centralized way, the functions of the rest part or all of the protocol layers are distributed in the DU, and the CU controls the DU in a centralized way.
2. And the base station chip is a control center for realizing the functions of the base station. The base station chip comprises a plurality of functional modules for realizing corresponding functions, and the functional modules cooperate with each other to finally realize the functions of the base station.
3. And the clock gating module is used for controlling the clock corresponding to the functional module to be opened or closed according to the working signal of the functional module. When the functional module is in a working state, the clock gating module controls the clock to be opened; when the functional module is in a non-working state, the clock gating module controls the clock to be closed.
4. And the working model comprises clock gating signals of the functional modules, which correspond to the states of the clock gating switches in different scenes, and the process is displayed and applied in a coded form through the working model. And obtaining the clock gating switch state corresponding to the working signal by inputting the working signal of the functional module.
5. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The three types of characters "/" generally indicate that the former and latter associated objects are in an "or" relationship.
In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order.
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Fig. 1 shows a possible base station chip to which the detection method of the clock gating module provided in the present application is applied. As shown in the figure, the base station chip includes a clock module 101, a function module 102, a clock gating module 103, and a communication module 104.
The clock module 101 is connected with the functional module 102, and when the clock module 101 is opened, the functional module 102 works; when the clock module 101 is turned off, the function module 102 stops operating.
Wherein, the clock gating module 103 is connected with the functional module 102. When the functional module 102 is in a working state, the clock gating module 103 obtains a working signal of the functional module 102, so as to control a clock corresponding to the functional module 102 to be turned on; when the functional module 102 is in a non-operating state, the clock gating module 103 cannot acquire the operating signal of the functional module 102 or the acquired operating signal of the functional module 102 is invalid, so as to control the clock corresponding to the functional module 102 to be turned off.
When the functional module 102 is in an operating state, data is transmitted through the communication module 104.
Therefore, the effectiveness of the clock gating module 103 directly determines whether the functional module 102 can work normally, so as to ensure that the functional module 102 performs normal data transmission and save the power consumption of the base station chip.
In order to detect the effectiveness of the clock gating module 103, the detection device obtains a working signal corresponding to the clock gating module 103, and observes a waveform of the working signal corresponding to the clock gating module 103 by using a simulation tool, thereby detecting the clock gating module 103. However, as the base station chip becomes complicated, the number of functional modules inside the base station chip increases, which results in a significant increase in the number of signals to be tested, an increase in difficulty of detection, and a higher labor cost.
The embodiment of the application provides a detection method of a clock gating module, which can realize automatic detection of the clock gating module. The method can be applied to a base station chip as shown in fig. 1. The following describes in detail a flow of a detection method of a clock gating module according to an embodiment of the present application with reference to fig. 2.
S201: the detection device acquires a working signal of a functional module in a base station and a first clock gating switch state, wherein the first clock gating switch state is the clock gating switch state of the functional module determined by the clock gating module according to the working signal of the functional module.
Optionally, the working signal of the functional module is at least one or a combination of the following: clock input signal, channel enable signal, software clock selection signal, hardware clock enable signal.
Optionally, the first clock gating switch state is: open or close.
S202: the detection device determines the current working scene of the base station.
S203: and the detection device determines a working model corresponding to the working scene, wherein the working model is used for representing the corresponding relation between the working signal of the functional module in the base station and the clock gating switch state of the functional module.
Optionally, the working scenario of the base station may be divided into: enable state, disable state.
Optionally, in an enable state and a disable state, a corresponding relationship between a working signal of a functional module in the base station in the working model and a clock gating switch state of the functional module is shown in fig. 3.
In the enabled state, the corresponding relationship between the working signal of the functional module and the clock gating switch state of the functional module includes the following conditions:
1) a just-released reset stage:
a: when the software clock select signal is present (clk _ sel ═ 1), then the corresponding clock gating switch is open.
B: when the software clock select signal (clk _ sel ═ 0) is absent and the software clock enable signal (clk _ en ═ 1) is present, then the functional module enters a hardware low power state. Wherein the corresponding clock-gated switch states include the following:
a. if no configuration is involved (active is 0), the corresponding clock gating switch is off.
b. If the configuration is intervened (active is 1), the corresponding clock gating switch is turned on.
For example, when the base station chip controls the base station to establish a cell, the clock gating module controls the corresponding clock gating module to be turned off or on according to different scenarios, that is, whether the channel has data information transmission or not. In a product of type 8aNR100+ NR60, the physical channel 6/7 does not perform the transmission and processing of data information, and the clock gating controlling the channel may be turned off at this time, thereby reducing power consumption. And the physical channel 0 always carries out data transmission, and the clock gating is required to be kept always on.
2) And the standby stage:
that is, the software clock select signal (clk _ sel ═ 0) is not present, and the functional module enters the hardware low power state when the software clock enable signal (clk _ en ═ 1) is present. Wherein, the corresponding clock gating switch state comprises the following conditions:
a. if no configuration is involved (active is 0), the corresponding clock gating switch is off.
b. If the configuration is intervened (active is 1), the corresponding clock gating switch is turned on.
If the configuration is not changed in the standby state of the functional module in the normal working state, the corresponding clock gating switch is turned off, and the codes are as follows.
Wherein, the specific value of $ in [0: $ ] is determined according to the continuous adjustment of the waveform of the working signal.
Optionally, in order to facilitate subsequent statistics of the detection state of the clock gating module in the working scenario, a print keyword, for example, "$ display", is added to the code.
3) And a working stage:
when the functional module is in a normal working state, the corresponding clock in each channel should keep a continuous clock opening state. That is, the software clock select signal (clk _ sel ═ 0) is absent, the software clock enable signal (clk _ en ═ 1) is present, the functional module enters the hardware low power consumption state, and when the configuration intervention is present (active ═ 1), the corresponding clock gating switch state is on.
And when the non-enabling state determines that the working signal of the current functional module is invalid, the clock gating switch is closed correspondingly.
For example, when the number of the effective antennas in the base station product type is less than 8, the uplink physical layer path does not need to work, and the corresponding clock gating switch is turned off at this time.
Optionally, in the working scenario, attention needs to be paid to a bus configuration condition, and the clock gating switch is forced to be turned on.
S204: and the detection device determines the second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model.
In one embodiment, the detecting device may perform S204 by:
the detection device modifies the signal identifier of the working signal of the functional module from the first signal identifier to the second signal identifier according to the corresponding relation of a preset first signal identifier and a preset second signal identifier; wherein the first signal identifier is a true signal identifier and the second signal identifier is a signal identifier of the working signal in the working model;
and the detection device inputs the working signal of the functional module with the signal identification as the second signal identification into the working model to obtain the state of the second clock gating switch.
Optionally, the state of the second clock-gated switch is obtained by the detection device executing the working model and the stored instantiation file through a simulation tool. And the instantiation file stores the corresponding relation between the first signal identifier and the second signal identifier.
Optionally, the stored instantiation file is a file generated by executing a "gen _ sva.pl + instance.in" instruction using a configuration model of a clock signal and a script model. The configuration model comprises a real signal identifier, and the script model further comprises a second signal identifier.
Optionally, the determining, by the detecting device, the configuration model includes the following steps:
s1: writing an initial configuration model of a clock gating signal: the simple module identification is manually filled in, and the real signal identification of the working signal.
S2: and filling a mapping form of the configuration register address to which the clock gating signal belongs in all the instantiation files according to the soft and hard register table.
S3: and (4) rapidly reading the real identification of each functional module and the real signal identification of the working signal of each functional module by using a simulation tool. Wherein, the real identifiers carry corresponding paths.
S4: compiling a functional script, extracting effective information of the compiled configuration file, merging and summarizing, and executing 'gen _ module.pl + channel _ template.in (file 1) + cfg _ template.in (file 2) + getModsignal.log (file 3)'.
S5: and automatically realizing complete configuration models of all functional modules by using the functional scripts. Fig. 4 shows a partial complete model, where the complete model includes information of a working signal, a level, a clock, a global clock, an active module, a software clock enable signal, and a software clock selection signal.
Optionally, the instantiation model and the working model are bound, and the binding can be implemented by the following means:
“bind top.u2 mutex_chk i2(c，d，clk)”。
s205: and the detection device determines the detection state of the clock gating module according to the state of the first clock gating switch and the state of the second clock gating switch.
In one embodiment, when the first clock gating switch state and the second clock gating switch state are the same, determining that the detection state of the clock gating module is normal;
in another embodiment, when the first clock-gated switch state and the second clock-gated switch state are different, it is determined that the detection state of the clock gating module is abnormal.
Optionally, the detection device performs statistics according to the script to generate a statistical table according to the detection states of the clock gating modules corresponding to different working scenes of each functional module.
For example, as shown in table 1, the detection results include: normal and abnormal, wherein the number of normalizations is 173 and the number of abnormalities is 3.
TABLE 1
| The result of the detection | Number of times |
| Is normal | 173 |
| Abnormality (S) | 3 |
Counting is performed for abnormal conditions, and as shown in table 2, the detection device determines a working scene according to the keyword and determines a corresponding working signal.
Optionally, for the working signal in the abnormal condition, the problem is analyzed by further observing the waveform of the working signal.
TABLE 2
| Working scene | Working signal |
| a22 | CH0 |
| a33 | CH1 |
| a24 | CH0 |
According to the detection device, the detection states of the clock gating modules corresponding to different working scenes of each module are rapidly counted by using the script, and the detection efficiency is greatly improved.
Based on the same technical concept, the embodiment of the present application further provides a detection apparatus, the structure of which is shown in fig. 5, and the detection apparatus includes a communication unit 501 and a processing unit 502. The detection device can be applied to the base station chip device shown in fig. 1, and can implement the detection method of the clock gating module shown in fig. 2. The functions of the various units in the apparatus 500 are described below.
A communication unit 501, configured to obtain a working signal of a functional module in a base station and a first clock gating on-off state, where the first clock gating on-off state is a clock gating on-off state of the functional module determined by the clock gating module according to the working signal of the functional module;
a processing unit 502, configured to determine a current working scenario of the base station, and determine a working model corresponding to the working scenario, where the working model is used to represent a correspondence between a working signal of a function module in the base station and a clock gating switch state of the function module;
the clock gating control module is also used for determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and determining the detection state of the clock gating module according to the state of the first clock gating switch and the state of the second clock gating switch.
In an embodiment, the processing unit 502 determines, according to the working model, a second clock-gated switch state of the functional module corresponding to the working signal of the functional module, and is specifically configured to:
modifying the signal identifier of the working signal of the functional module from the first signal identifier to the second signal identifier according to the preset corresponding relation between the first signal identifier and the second signal identifier; wherein the first signal identifier is a true signal identifier and the second signal identifier is a signal identifier of the working signal in the working model;
and inputting the working signal of the functional module with the signal identifier as the second signal identifier into the working model to obtain the state of the second clock gating switch.
In one embodiment, the determining, by the processing unit 502, the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state includes:
when the first clock gating switch state is the same as the second clock gating switch state, determining that the detection state of the clock gating module is normal;
and when the first clock gating switch state and the second clock gating switch state are different, determining that the detection state of the clock gating module is abnormal.
In one embodiment, the operation signal of the functional module is at least one or a combination of the following: clock input signal, channel enable signal, software clock selection signal, hardware clock enable signal.
Based on the same technical concept, the embodiment of the present application further provides a detection device, which can be applied to the base station chip device shown in fig. 1 and can implement the detection method of the clock gating module shown in fig. 2. Referring to fig. 6, the detecting apparatus includes: a communication module 601, a processor 602, and a memory 603. The communication module 601, the processor 602, and the memory 603 are connected to each other.
Optionally, the communication module 601, the processor 602, and the memory 603 are connected to each other through a bus 604. The bus 604 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc.
A communication module 601, configured to obtain a working signal of a functional module in a base station and a first clock gating on-off state, where the first clock gating on-off state is a clock gating on-off state of the functional module determined by the clock gating module according to the working signal of the functional module;
a processor 602, configured to determine a current working scenario of the base station, and determine a working model corresponding to the working scenario, where the working model is used to represent a correspondence between a working signal of a function module in the base station and a clock gating switch state of the function module;
the clock gating control module is also used for determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and determining the detection state of the clock gating module according to the state of the first clock gating switch and the state of the second clock gating switch.
In an embodiment, the processor 602 determines, according to the working model, a second clock-gated switch state of the functional module corresponding to the working signal of the functional module, where the second clock-gated switch state is specifically configured to:
modifying the signal identifier of the working signal of the functional module from the first signal identifier to the second signal identifier according to the preset corresponding relation between the first signal identifier and the second signal identifier; wherein the first signal identifier is a true signal identifier and the second signal identifier is a signal identifier of the working signal in the working model;
and inputting the working signal of the functional module with the signal identifier as the second signal identifier into the working model to obtain the state of the second clock gating switch.
In one embodiment, the determining, by the processor 602, the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state includes:
when the first clock gating switch state is the same as the second clock gating switch state, determining that the detection state of the clock gating module is normal;
and when the first clock gating switch state and the second clock gating switch state are different, determining that the detection state of the clock gating module is abnormal.
In one embodiment, the operation signal of the functional module is at least one or a combination of the following: clock input signal, channel enable signal, software clock selection signal, hardware clock enable signal.
Based on the above embodiments, the embodiments of the present application further provide a computer program, which, when running on a computer, causes the computer to execute the method for detecting a clock gating module provided in the embodiment shown in fig. 2.
Based on the above embodiments, the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a computer, the computer is caused to execute a method for detecting a clock gating module, which is provided by the embodiment shown in fig. 2.
Based on the above embodiments, the embodiments of the present application further provide a chip, where the chip is used to read a computer program stored in a memory, and implement the detection method for the clock gating module provided in the embodiment shown in fig. 2.
Based on the foregoing embodiments, an embodiment of the present application provides a chip system, where the chip system includes a processor, and is used to support a computer device to implement the function of the detection apparatus in the embodiment shown in fig. 6. In one possible design, the system-on-chip further includes a memory for storing programs and data necessary for the computer device. The chip system may be constituted by a chip, or may include a chip and other discrete devices.
In summary, the present application provides a method and an apparatus for detecting a clock gating module. In the scheme, firstly, a working signal of a functional module in a base station and a first clock gating switch state are obtained, wherein the first clock gating switch state is the clock gating switch state of the functional module determined by the clock gating module according to the working signal of the functional module; then, determining a current working scene of the base station, and determining a working model corresponding to the working scene, wherein the working model is used for representing the corresponding relation between a working signal of a functional module in the base station and the clock gating switch state of the functional module; secondly, determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and finally, determining the detection state of the clock gating module according to the first clock gating switch state and the second clock gating switch state. The method can realize automatic detection of the clock gating module, not only improves the speed and accuracy of detection, but also can avoid the cost of manual detection.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (11)
1. A method for detecting a clock gating module, comprising:
acquiring a working signal of a functional module in a base station and a first clock gating switch state, wherein the first clock gating switch state is the clock gating switch state of the functional module determined by the clock gating module according to the working signal of the functional module;
determining a current working scene of the base station, and determining a working model corresponding to the working scene, wherein the working model is used for representing the corresponding relation between a working signal of a functional module in the base station and the state of a clock gating switch of the functional module;
determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model;
and determining the detection state of the clock gating module according to the state of the first clock gating switch and the state of the second clock gating switch.
2. The method according to claim 1, wherein determining, according to the operation model, a second clock-gated switch state of the functional module corresponding to the operation signal of the functional module specifically comprises:
modifying the signal identifier of the working signal of the functional module from the first signal identifier to the second signal identifier according to the preset corresponding relation between the first signal identifier and the second signal identifier; wherein the first signal identifier is a true signal identifier and the second signal identifier is a signal identifier of the working signal in the working model;
and inputting the working signal of the functional module with the signal identifier as the second signal identifier into the working model to obtain the state of the second clock gating switch.
3. The method of claim 1, wherein determining the detection state of the clock gating module based on the first clock-gated switch state and the second clock-gated switch state, further comprises:
when the first clock gating switch state is the same as the second clock gating switch state, determining that the detection state of the clock gating module is normal;
and when the first clock gating switch state and the second clock gating switch state are different, determining that the detection state of the clock gating module is abnormal.
4. The method of claim 1, wherein the operational signal of the functional module is at least one or more of: clock input signal, channel enable signal, software clock selection signal, hardware clock enable signal.
5. A device for detecting a clock gating module, comprising:
the communication unit is used for acquiring a working signal of a functional module in a base station and a first clock gating switch state, wherein the first clock gating switch state is the clock gating switch state of the functional module determined by the clock gating module according to the working signal of the functional module;
the processing unit is used for determining the current working scene of the base station and determining a working model corresponding to the working scene, wherein the working model is used for representing the corresponding relation between the working signal of a functional module in the base station and the clock gating switch state of the functional module;
the clock gating control module is also used for determining a second clock gating switch state of the functional module corresponding to the working signal of the functional module according to the working model; and determining the detection state of the clock gating module according to the state of the first clock gating switch and the state of the second clock gating switch.
6. The apparatus according to claim 5, wherein the processing unit determines, according to the operation model, a second clock-gated switch state of the functional module corresponding to the operation signal of the functional module, and is specifically configured to:
modifying the signal identifier of the working signal of the functional module from the first signal identifier to the second signal identifier according to the preset corresponding relation between the first signal identifier and the second signal identifier; wherein the first signal identifier is a true signal identifier and the second signal identifier is a signal identifier of the working signal in the working model;
and inputting the working signal of the functional module with the signal identifier as the second signal identifier into the working model to obtain the state of the second clock gating switch.
7. The apparatus of claim 5, wherein the processing unit to determine the detection state of the clock gating module based on the first clock-gated switch state and the second clock-gated switch state comprises:
when the first clock gating switch state is the same as the second clock gating switch state, determining that the detection state of the clock gating module is normal;
and when the first clock gating switch state and the second clock gating switch state are different, determining that the detection state of the clock gating module is abnormal.
8. The apparatus of claim 5, wherein the operational signal of the functional module is at least one or a combination of: clock input signal, channel enable signal, software clock selection signal, hardware clock enable signal.
9. A computer-readable storage medium, in which a computer program is stored which, when run on an electronic device, causes the electronic device to perform the method according to any one of claims 1-4.
10. A computer program, comprising instructions which, when run on a computer, cause the computer to perform the method according to any one of claims 1-4.
11. A chip for reading a computer program stored in a memory for performing the method according to any one of claims 1 to 4.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116088667A (en) * | 2023-03-03 | 2023-05-09 | 此芯科技(北京)有限公司 | System-level SOC chip control circuit, method and electronic equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102193580A (en) * | 2010-02-12 | 2011-09-21 | 布鲁旺德通讯有限公司 | Method and device for clock gate controlling |
| US20130038352A1 (en) * | 2011-08-12 | 2013-02-14 | Texas Instruments Incorporated | Circuits and methods for clock malfunction detection |
| US20130101006A1 (en) * | 2011-10-24 | 2013-04-25 | Sigear Europe Sarl | Clock Masking Scheme In A Mixed-Signal System |
| CN103491036A (en) * | 2012-06-12 | 2014-01-01 | 马维尔国际贸易有限公司 | Apparatus and method for wireless baseband processing |
| CN106709859A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Adaptive low-power-consumption clock gating structure of rasterization unit of graphic processing unit |
| CN108153920A (en) * | 2016-12-02 | 2018-06-12 | 恩智浦美国有限公司 | Clock gating verification during the RTL stages of IC design |
| CN110442187A (en) * | 2019-08-08 | 2019-11-12 | 南京芯驰半导体科技有限公司 | System and method are limited for the clock of module |
-
2019
- 2019-12-26 CN CN201911367619.5A patent/CN113055099B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102193580A (en) * | 2010-02-12 | 2011-09-21 | 布鲁旺德通讯有限公司 | Method and device for clock gate controlling |
| US20130038352A1 (en) * | 2011-08-12 | 2013-02-14 | Texas Instruments Incorporated | Circuits and methods for clock malfunction detection |
| US20130101006A1 (en) * | 2011-10-24 | 2013-04-25 | Sigear Europe Sarl | Clock Masking Scheme In A Mixed-Signal System |
| CN103491036A (en) * | 2012-06-12 | 2014-01-01 | 马维尔国际贸易有限公司 | Apparatus and method for wireless baseband processing |
| CN108153920A (en) * | 2016-12-02 | 2018-06-12 | 恩智浦美国有限公司 | Clock gating verification during the RTL stages of IC design |
| CN106709859A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Adaptive low-power-consumption clock gating structure of rasterization unit of graphic processing unit |
| CN110442187A (en) * | 2019-08-08 | 2019-11-12 | 南京芯驰半导体科技有限公司 | System and method are limited for the clock of module |
Non-Patent Citations (1)
| Title |
|---|
| 朱涛涛 等: "面向宽电压应用的容错时钟门控单元设计", 《浙江大学学报》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116088667A (en) * | 2023-03-03 | 2023-05-09 | 此芯科技(北京)有限公司 | System-level SOC chip control circuit, method and electronic equipment |
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