CN116257427A - Heterogeneous test method, heterogeneous test system, heterogeneous test equipment and heterogeneous test storage medium for federal learning task - Google Patents

Heterogeneous test method, heterogeneous test system, heterogeneous test equipment and heterogeneous test storage medium for federal learning task Download PDF

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CN116257427A
CN116257427A CN202111515773.XA CN202111515773A CN116257427A CN 116257427 A CN116257427 A CN 116257427A CN 202111515773 A CN202111515773 A CN 202111515773A CN 116257427 A CN116257427 A CN 116257427A
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federal learning
data
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王亚玲
王玮
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Shenzhen Zhixing Technology Co Ltd
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Abstract

The application discloses heterogeneous testing method, system, equipment and storage medium of federal learning tasks, wherein the method comprises the following steps: when detecting heterogeneous test instructions of a federal learning task, determining configuration information corresponding to the heterogeneous processing instructions; according to the configuration information, issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU, wherein the data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants; and receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result. In this application, the training efficiency of federal learning task is significantly improved.

Description

Heterogeneous test method, heterogeneous test system, heterogeneous test equipment and heterogeneous test storage medium for federal learning task
Technical Field
The application relates to the technical field of artificial intelligence, in particular to a heterogeneous test method, a heterogeneous test system, heterogeneous test equipment and a heterogeneous test storage medium for federal learning tasks.
Background
Along with the development of artificial intelligence technology, the application of federal learning is also more and more widespread, and federal learning is a distributed machine learning framework, and the framework can break the situation of data island and realize the sharing of data of both sides on the premise of ensuring the safety, privacy and legality of data for different enterprises, institutions or users.
Specifically, in the process of training the federal learning model, different participants train the federal learning model locally based on local data (different participants train the same model), after training for a certain number of times, the different participants perform interaction of intermediate parameters, after the interaction of the intermediate parameters is completed, the different participants continue training the model based on the interacted intermediate parameters and the local data until a trained model is obtained, and the training of the local model by the participants involves homomorphic encryption, matrix multiplication and other operations of the data, so that the subsequent interaction of the intermediate parameters can be continued. The computation amount of the operations such as the secret addition, the matrix multiplication and the like is large and complex, at present, the operations such as the secret addition, the matrix multiplication and the like are only completed at the CPU end of the participator, the internal structure of the CPU end is extremely complex, namely, the CPU needs to process different types of data, the logic judgment needs to be carried out on branches and jumps, and the operations such as homomorphic encryption and the like are only carried out at the CPU end of the participator, so that the training efficiency of the federal learning model is low.
Disclosure of Invention
The application mainly aims to provide a heterogeneous test method, a heterogeneous test system, electronic equipment, a storage medium and a heterogeneous test product for a federal learning task, and aims to solve the technical problem that training efficiency is low because homomorphic encryption and other operations are only carried out on data at a CPU (central processing unit) end of a participant in the existing federal learning model training process.
In order to achieve the above objective, the present application provides a heterogeneous testing method of a federal learning task, which is applied to a CPU end of a federal learning participant, and the heterogeneous testing method of the federal learning task includes:
when detecting heterogeneous test instructions of a federal learning task, determining configuration information corresponding to the heterogeneous processing instructions;
according to the configuration information, issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU, wherein the data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants;
and receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result.
Optionally, the step of determining configuration information corresponding to the heterogeneous processing instruction when the heterogeneous test instruction of the federal learning task is detected includes:
the heterogeneous test instruction of the federal learning task is triggered under the condition of meeting the preset acceleration processing data;
when detecting heterogeneous test instructions of the federal learning task, extracting associated parameters from the heterogeneous processing instructions, wherein the associated parameters comprise at least one of data bit width, algorithm types to be tested of the federal learning task and test scale of the federal learning task;
and determining configuration information corresponding to the heterogeneous processing instruction according to the association parameter.
Optionally, the step of issuing the data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU end according to the configuration information includes:
determining the process number of the federal learning task, the allocable thread number in each process and a data quantity threshold value in each process according to the configuration information;
and distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU end according to the number of processes of the federal learning task, the number of distributable threads in each process and the data quantity threshold in each process.
Optionally, the CPU side includes a processing layer, and the step of distributing data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip communicatively connected to the CPU side according to the number of processes of the federal learning task, the number of threads allocable in each process, and a data amount threshold in each process includes:
distributing data to be calculated corresponding to the federal learning task to the processing layer according to the number of processes of the federal learning task, the number of threads which can be distributed in each process and a data quantity threshold value in each process;
based on the processing layer, analyzing the data to be calculated corresponding to the federal learning task to obtain analysis data;
determining one or more of a computing task function, a data feature, and a parameter of the federal learning task based on the parsed data;
determining a target heterogeneous computing chip based on one or more of the computing task functions, data features, and parameters;
and distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU.
Optionally, the step of distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip communicatively connected to the CPU side includes:
Determining an initial format of data to be calculated corresponding to the federation learning task, and determining a target format corresponding to and matched with the target heterogeneous computing chip;
if the initial format is inconsistent with the target format, performing format conversion processing on the data to be calculated corresponding to the federal learning task based on the target format to obtain converted data;
and distributing the converted data to a corresponding target heterogeneous computing chip in communication connection with the CPU.
Optionally, after the step of receiving the first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, the method includes:
obtaining a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task;
and determining heterogeneous test effects of the federal learning task based on the first calculation result and the second calculation result.
Optionally, the configuration information includes comparison information that needs to be compared between a local calculation result and a heterogeneous chip calculation result, and the step of obtaining a second calculation result obtained after the local calculation of the federal learning task corresponding to the data to be calculated includes:
And if the configuration information comprises the comparison information, executing a step of obtaining a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task.
Optionally, the heterogeneous test method of the federal learning task includes:
the federation learning task is a model training task of longitudinal federation learning logistic regression;
the configuration information comprises the data size, the data bit width and the algorithm type to be tested of the federal learning task of the data to be calculated, wherein the algorithm type to be tested is Paillier decryption operation type;
the data to be calculated is ciphertext data which is correspondingly obtained and used for local model training and interaction with other participants after preprocessing, data intersection and data encryption processing are carried out on the original data;
the first calculation result is a calculation result obtained after the target heterogeneous calculation chip carries out decryption calculation on the data to be calculated.
The application also provides a heterogeneous testing device of federal learning task, is applied to the CPU end of federal learning participant, heterogeneous testing device of federal learning task includes:
the first determining module is used for determining configuration information corresponding to heterogeneous processing instructions when heterogeneous testing instructions of the federal learning task are detected;
The issuing module is used for issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU according to the configuration information, wherein the data to be calculated is intermediate data which is obtained correspondingly after preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants;
the receiving module is used for receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result.
The application also provides a device, the device is an electronic device, the electronic device is an entity node device, and the electronic device includes: the system comprises a memory, a processor and a program of the heterogeneous test method of the federal learning task, wherein the program of the heterogeneous test method of the federal learning task is stored on the memory and can run on the processor, and the program of the heterogeneous test method of the federal learning task can realize the steps of the heterogeneous test method of the federal learning task when being executed by the processor.
The application also provides a storage medium, wherein the storage medium stores a program for realizing the heterogeneous test method of the federal learning task, and the program for realizing the heterogeneous test method of the federal learning task realizes the steps of the heterogeneous test method of the federal learning task when being executed by a processor.
The application also provides a heterogeneous test system of federal learning tasks, the heterogeneous test system of federal learning tasks comprising: the heterogeneous test system of the federal learning task comprises: the system comprises a CPU end and a target heterogeneous computing chip, wherein the CPU end comprises a federal learning task layer, a processing layer and a issuing layer;
when detecting heterogeneous test instructions of the federal learning task, the federal learning task layer acquires data corresponding to the federal learning task and sends the data corresponding to the federal learning task to be calculated to a processing layer;
the processing layer acquires configuration information corresponding to the heterogeneous processing instruction, wherein the configuration information comprises comparison information which needs to be compared between a local calculation result and a heterogeneous chip calculation result, a target heterogeneous calculation chip is determined based on the configuration information, and after the target heterogeneous calculation chip is determined, data corresponding to the federal learning task to be calculated is sent to a sending layer;
the issuing layer issues data to be calculated corresponding to the federal learning task to the target heterogeneous computing chip;
the target heterogeneous computing chip calculates the federal learning task to obtain a first computing result, and sends the first computing result to the federal learning task layer through the issuing layer and the processing layer;
And the federal learning task layer calculates the data to be calculated according to the comparison information to obtain a second calculation result, compares the first calculation result with the second calculation result to determine the calculation effect of the target heterogeneous calculation chip, and executes the post-processing flow of the federal learning task based on the first calculation result.
The present application also provides an article of manufacture, the article of manufacture being a computer program product comprising a computer program which, when executed by a processor, performs the steps of the heterogeneous test method of federal learning tasks described above.
Compared with the prior art that the calculation such as homomorphic encryption is carried out on data only at the CPU end of a participant, so that the model training efficiency is low, the heterogeneous test method, system, electronic equipment, storage medium and product of the federal learning task determine the configuration information corresponding to the heterogeneous processing instruction when the heterogeneous test instruction of the federal learning task is detected; according to the configuration information, issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU, wherein the data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants; and receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result. In the application, when the federation learning model is trained, the data is not only subjected to homomorphic encryption and other operations on the CPU end, but is directly distributed to a proper target heterogeneous computing chip based on configuration information corresponding to heterogeneous processing instructions, wherein the data to be computed (intermediate data which is correspondingly obtained and used for local model training and interacting with other participants after the participants perform preprocessing and data intersection on the original data of the federation learning task) is distributed to the proper target heterogeneous computing chip, so that the data types processed by the heterogeneous computing chip are highly uniform, the computing environment is pure (only high-speed operation is needed and logic judgment is not needed), and the data to be computed corresponding to the federation learning task is issued to the target heterogeneous computing chip in communication connection with the CPU end so as to be computed by the target heterogeneous computing chip, and the training efficiency of the federation learning task can be remarkably improved.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic flow chart of a first embodiment of a heterogeneous test method for federal learning tasks of the present application;
fig. 2 is a schematic diagram of a refinement flow of step S10 in the first embodiment of the heterogeneous test method for federal learning task in the present application;
FIG. 3 is a schematic diagram of an electronic device in a hardware operating environment according to an embodiment of the present application;
FIG. 4 is a schematic flow chart of a heterogeneous test method of the federal learning task according to the present application;
fig. 5 is a schematic diagram of a communication architecture of a video center in a heterogeneous test method of federal learning task in the present application.
The implementation, functional features and advantages of the present application will be further described with reference to the accompanying drawings in conjunction with the embodiments.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, the following description of the embodiments accompanied with the accompanying drawings will be given in detail. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
In a first embodiment of the heterogeneous testing method for federal learning tasks of the present application, referring to fig. 1, the heterogeneous testing method for federal learning tasks is applied to a CPU end of a federal learning participant, and includes:
step S10, when detecting a heterogeneous test instruction of a federal learning task, determining configuration information corresponding to the heterogeneous processing instruction;
step S20, according to the configuration information, issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU, wherein the data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants correspondingly;
Step S30, a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated is received.
In the process of training the federal learning model, different participants can train the federal learning model locally based on local data (different participants train the same model), after training for a certain number of times, the different participants perform interaction of intermediate parameters, after the interaction of the intermediate parameters is completed, the different participants can continue to train the model based on the interacted intermediate parameters and the local data and continuously interact with other participants (privacy leakage is avoided, thus encryption is needed in the interaction process), until the trained model is obtained, the participants perform the training of the local model and interact with other participants, the homomorphic encryption, matrix multiplication and other operations of data can be involved, the subsequent interaction of the intermediate parameters can be continued, and the calculation amount of the secret addition, the matrix multiplication and the like is large and complex.
In this embodiment, the CPU performs operations such as homomorphic encryption on data to be calculated, but directly distributes related computing tasks such as homomorphic encryption to a suitable target heterogeneous computing chip based on configuration information corresponding to heterogeneous processing instructions, which can be understood that the types of data processed by the heterogeneous computing chip are highly uniform, the computing environment is pure (only needs to perform high-speed operations without logic judgment), the related computing task (preprocessing the original data of the federal learning task and performing data interaction) of the federal learning task corresponding to the data to be calculated, and the obtained intermediate data for local model training and interaction with other participants is sent to the target heterogeneous computing chip in communication connection with the CPU for the target heterogeneous computing chip to perform computation, so that the test efficiency of the federal learning task can be significantly improved.
The method comprises the following specific steps:
step S10, when detecting a heterogeneous test instruction of a federal learning task, determining configuration information corresponding to the heterogeneous processing instruction;
in this embodiment, it should be noted that, the heterogeneous test method of the federal learning task may be applied to a CPU end of a federal learning participant, where the CPU end and a heterogeneous computing chip communicatively connected to the CPU end belong to a heterogeneous test system of the federal learning task, where the heterogeneous test system of the federal learning task belongs to an electronic device or other electronic devices, and where the heterogeneous processing device or other electronic devices belong to the participant.
It should be noted that, the federal learning includes a longitudinal federal learning calculation and a transverse federal learning calculation, and the longitudinal federal learning is that the federal learning (Sample-Aligned Federated Learning) with aligned samples is suitable for the situations that the training Sample IDs of the participants overlap more and the data features overlap less, and the training and the optimization of the model are required to be completed cooperatively by multiple parties under the framework of security and confidentiality.
The horizontal federal learning (Horizontal Federated Learning) is suitable for the situation that the characteristics of the training sample data of the participants overlap more and the user IDs are less, and the training and the optimization of the model are completed cooperatively by multiple parties under the framework of security and confidentiality.
Whether the model is used for horizontal federal learning or longitudinal federal learning, each round of model parameter updating links are divided into two steps: (a) Each participant only uses own data to train the machine learning model and sends model parameter updates to a central coordinator; (b) The coordinator fuses (e.g., averages) the received model updates from different participants, and redistributes the fused model parameter updates to each participant, and in federal learning, the participants do not need to expose own data to other participants or the coordinator, so that federal learning can well protect user privacy and ensure data security.
That is, in both the longitudinal federal learning calculation and the transverse federal learning calculation, the model parameters are required to be fused, and in the fusion process of the model parameters, in order to ensure that the data is not leaked, the calculation modes of modular exponentiation, modular multiplication, dense addition, dense multiplication, paillie encryption, non-confusion encryption, RSA and the like are involved. The modular exponentiation, modular multiplication, secret addition, secret multiplication, paillie encryption, non-confusion encryption, RSA and other calculation modes have large data processing capacity and consume more calculation resources, so that the resource consumption condition in the corresponding test process of the federal learning task needs to be considered, and the method is also a research and development background of the application.
That is, in this embodiment, the specific application scenario targeted may be:
in the process of training the federal learning model, different participants can train the federal learning model (different participants train the same model) locally based on local data, after training for a certain number of times, interaction of intermediate parameters is carried out among different participants, after the interaction of the intermediate parameters is completed, the different participants can continue training the model based on the interacted intermediate parameters and the local data until a trained model is obtained, and training of the local model by the participants can involve homomorphic encryption, matrix multiplication and other operations of the data, so that subsequent interaction of the intermediate parameters can be continued. The computation amount of the operations such as the secret addition, the matrix multiplication and the like is large and complex, at present, the operations such as the secret addition, the matrix multiplication and the like are only completed at the CPU end of the participator, the internal structure of the CPU end is extremely complex, namely, the CPU needs to process different types of data, the logic judgment needs to be carried out on branches and jumps, and the operations such as homomorphic encryption and the like are only carried out at the CPU end of the participator, so that the training efficiency of the federal learning model is low.
In this embodiment, the computing power in the model training process is greatly improved by combining the CPU with the testing mode of the heterogeneous computing chip, that is, by obtaining the heterogeneous testing system of the federal learning task through hardware optimization, so that the model training efficiency is improved.
In the embodiment, the CPU side directly distributes the homomorphic encryption related computing tasks to the appropriate heterogeneous computing chips and distributes the matrix multiplication related computing tasks to other appropriate heterogeneous computing chips in consideration of the characteristics of different heterogeneous computing chips, so that the overall operation efficiency of the test platform is improved, that is, the heterogeneous computing chips generally play a role of a high-speed arithmetic unit, carry out complex arithmetic in the test process, and lighten the working pressure of the CPU side.
In this embodiment, the corresponding CPU end may be operated in Windows, MAC, linux and various UNIX environments, and the CPU end application is completed by a free editing and compiling script tool, so that the cost of professional software can be saved.
In this embodiment, it should be noted that only one PC is needed when the heterogeneous test system of the federal learning task is running, that is, the PC is a federal learning participant.
In this embodiment, as shown in fig. 1, the CPU side and the heterogeneous computing chip side are involved, and data transmission and communication are performed between the CPU side and the heterogeneous computing chip side through PCIe (interface), so as to complete information interaction between the CPU side and the heterogeneous computing chip side.
In addition, as shown in fig. 4, in this embodiment, the CPU side involves four modules: the processing layer analyzes and distributes the received upper layer data, the issuing layer is mainly responsible for data communication between the CPU end and the PCIe, and the memory is mainly responsible for data storage of other modules.
In this embodiment, the heterogeneous test system of the federal learning task may be run on Windows, mac, linux and various UNIX systems, and the heterogeneous test system of the federal learning task may flexibly configure related parameters, such as the type of algorithm to be tested, the number of parallel cores of the CPU processor, the type of heterogeneous computing chip, and the like.
And when detecting heterogeneous test instructions of the federal learning task, determining configuration information corresponding to the heterogeneous processing instructions.
When detecting a heterogeneous test instruction of the federal learning task, determining configuration information corresponding to the heterogeneous processing instruction may specifically include:
when a heterogeneous test instruction of a federal learning task is detected, determining configuration information corresponding to the heterogeneous processing instruction;
or when heterogeneous test instructions of a plurality of federal learning tasks are detected, determining configuration information corresponding to the heterogeneous processing instructions.
That is, in this embodiment, only one federal learning task may be processed at a time, or a plurality of federal learning tasks may be processed at the same time, and when a plurality of federal learning tasks are processed at the same time, the types of the plurality of federal learning tasks may be different.
The federal learning task may specifically be tasks such as sample alignment, model training, model prediction, and the like.
In this embodiment, the triggering manner of the heterogeneous test instruction of the federal learning task may be:
mode one: heterogeneous test instructions of federal learning tasks are triggered manually;
mode two: when data to be tested are received, triggering heterogeneous test instructions of the federal learning task through a preset trigger program segment;
mode three: the heterogeneous test instruction of the federal learning task is triggered under the condition of meeting the preset acceleration processing data, and the preset acceleration processing data condition can be: the decryption operator, the encryption operator, the modular curtain operator and the like run to the federation learning operator layer, so that heterogeneous test instructions of the federation learning task are triggered to be generated.
When detecting heterogeneous test instructions of the federal learning task, determining configuration information corresponding to the heterogeneous processing instructions, and acquiring the configuration information corresponding to the heterogeneous processing instructions.
The configuration information comprises the type of an algorithm to be tested, the parallel core number of the CPU processor, the type of a heterogeneous computing chip and the like.
The source mode of the configuration information on the CPU side can be as follows:
mode one: the user leads the configuration information into the CPU end through the configuration file;
And secondly, the user directly fills configuration information on the CPU end in a corresponding processing interface of the heterogeneous test system of the federal learning task.
Referring to fig. 2, the step of determining configuration information corresponding to a heterogeneous processing instruction when a heterogeneous test instruction of a federal learning task is detected includes:
the heterogeneous test instruction of the federal learning task is triggered under the condition of meeting the preset acceleration processing data;
step S11, when a heterogeneous test instruction of a federal learning task is detected, extracting relevant parameters from the heterogeneous processing instruction, wherein the relevant parameters comprise at least one of data bit width, heterogeneous test mode of the federal learning task and test scale of the federal learning task;
and step S12, determining configuration information corresponding to the heterogeneous processing instruction according to the association parameters.
In this embodiment, the data is in binary expression, so the data bit width may be 1024, 2048, 4096, etc., and the test scale of the federal learning task specifically refers to the test size, including the size of the data volume, the data batch, etc.
In this embodiment, the configuration information further includes the kind of algorithm to be tested, the number of parallel cores of the CPU processor, the type of heterogeneous computing chip, and the like (carried in heterogeneous processing instructions).
It should be noted that, when the types of algorithms to be tested, the number of parallel cores of the CPU processor, the types of heterogeneous computing chips, and the like are the same, but the data bit width, the test scale, and the like are different, the corresponding target heterogeneous computing chips may be different. Thus, in the present embodiment, the configuration information is determined based on the associated parameters including at least one of the data bit width, the kind of the test algorithm, and the test scale, and after the configuration information is determined, the target heterogeneous computing chip can be accurately determined.
Step S20, according to the configuration information, issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU, wherein the data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants correspondingly;
after the configuration information is obtained, a target heterogeneous computing chip is determined according to the configuration information, and further data to be computed corresponding to the federation learning task is issued to the target heterogeneous computing chip in communication connection with the CPU end, so that the data to be computed corresponding to the federation learning task is computed in the target heterogeneous computing chip.
The data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data interaction, and is used for local model training and interaction with other participants.
Specifically, the participants interact with other participants in the training process of performing the federal learning task, at this time, intermediate processing result data is obtained, and after the participants obtain the intermediate processing result data, the intermediate processing result data is issued to the heterogeneous computing chip to perform acceleration processing (modular exponentiation, modular multiplication, secret addition, secret multiplication, paillie encryption, non-confusion encryption, RSA and other processing).
The specific heterogeneous computing chip is used for carrying out modular exponentiation, modular multiplication, secret addition, secret multiplication, paillie encryption or non-confusion encryption on the result data of the intermediate processing, and the specific heterogeneous computing chip is determined according to the configuration information.
The step of issuing the data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU end according to the configuration information comprises the following steps:
step S21, determining the process number of the federal learning task, the allocable thread number in each process and the data quantity threshold value in each process according to the configuration information;
And step S22, distributing the data to be calculated corresponding to the federation learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU end according to the number of processes of the federation learning task, the number of threads which can be distributed in each process and the data quantity threshold in each process.
In this embodiment, the configuration information further includes the number of processes of the federal learning task, the number of threads that can be allocated in each process, and a data volume threshold in each process, so that the CPU end starts to run the multi-process and multi-thread computing task according to the configuration information, and issues the federal learning task corresponding to the data to be computed to the processing layer, after the processing layer of the CPU end receives the data to be computed, the processing layer of the CPU end analyzes the data format first, then selects a corresponding heterogeneous computing chip, that is, a target heterogeneous computing chip, and issues corresponding data to the corresponding computing chip through the PCIe interface by means of the issuing layer.
It should be noted that, according to the number of processes of the federal learning task, the number of threads that can be allocated in each process, and the data amount threshold in each process, distributing the data to be calculated corresponding to the federal learning task to the corresponding target heterogeneous computing chip that is in communication connection with the CPU terminal includes:
Mode one: when a plurality of data corresponding to the federation learning task exist, the data corresponding to the federation learning task and to be calculated are distributed through a plurality of processes (each process can correspond to different processing algorithms, one process corresponds to a plurality of threads, each process has a data quantity threshold), and further, the data corresponding to the federation learning task and to be calculated are distributed to a corresponding target heterogeneous computing chip in communication connection with the CPU.
Mode two: when 1 federal learning task corresponding data exists, distributing the data to be calculated corresponding to the 1 federal learning task through multiple processes (each process can correspond to the same processing algorithm, one process corresponds to multiple threads, each process has a data volume threshold), and further distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU.
In this embodiment, the heterogeneous computing chip includes an FPGA type computing chip, a GPU type computing chip, an ASIC type computing chip, and the like.
The GPU type computing chip and the ASIC type computing chip are computing chips with fixed function types, for example, the GPU type computing chip is a computing chip specially aiming at video processing, and the FPGA type computing chip can flexibly allocate FPGA resources to realize optimal performance configuration under different function conditions.
Although the GPU type computing chip and the ASIC type computing chip are computing chips having a fixed function type, the fixed function type of the ASIC type computing chip can be adjusted, and the fixed function type of the GPU type computing chip is difficult to adjust.
Step S30, receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result.
After receiving data to be calculated corresponding to the federal learning task, the target heterogeneous computing chip stores the data in a memory and processes the data, wherein the received computing task (which can be in a parallel processing mode) is processed in the most efficient mode by taking the FPGA or the GPU as the computing chip of the task, and after the processing is completed, a first computing result is timely transmitted back to the CPU end through PCIe.
After the heterogeneous computing chip computes the data to be computed, the CPU end obtains a first computing result returned by the heterogeneous computing chip, and the first computing result is directly utilized to execute a post-processing flow of the federal learning task, wherein the post-processing flow can be interaction with other participants, and the like.
After the step of receiving the first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, the method includes:
step S40, a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task is obtained;
and step S50, determining heterogeneous test effects of the federal learning task based on the first calculation result and the second calculation result.
In this embodiment, a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task is also obtained, that is, a part of calculation tasks (data to be calculated) of the federal learning task is processed at a CPU end, at this time, a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task is obtained, and then, based on the first calculation result and the second calculation result, a heterogeneous test effect of the federal learning task is determined.
In this embodiment, a part of the data to be calculated may be calculated at the CPU side, and a part of the data may be calculated in a heterogeneous computing chip.
In this embodiment, the configuration information includes comparison information that needs to be compared between a local calculation result and a heterogeneous chip calculation result, and the step of obtaining a second calculation result obtained after the local calculation of the federal learning task corresponding to the data to be calculated includes:
and step M1, executing a step of obtaining a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task if the configuration information comprises the comparison information.
In this embodiment, the configuration information includes comparison information that needs to be compared between the local calculation result and the heterogeneous chip calculation result, and if the configuration information is detected to include the comparison information, a step of acquiring a second calculation result obtained after the federal learning task is locally calculated corresponding to the data to be calculated is performed, so that flexibility of verification is improved.
In this embodiment, after the first calculation result and the second calculation result are obtained, the first calculation result and the second calculation result are combined, and whether the first calculation result is accurate or not is determined based on the combined first calculation result and second calculation result.
Compared with the prior art that the calculation such as homomorphic encryption is carried out on data only at the CPU end of a participant, so that the model training efficiency is low, the heterogeneous test method, system, electronic equipment, storage medium and product of the federal learning task determine the configuration information corresponding to the heterogeneous processing instruction when the heterogeneous test instruction of the federal learning task is detected; according to the configuration information, issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU, wherein the data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants; and receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result. In the application, when the federation learning model is trained, the data is not only subjected to homomorphic encryption and other operations on the CPU end, but is directly distributed to a proper target heterogeneous computing chip based on configuration information corresponding to heterogeneous processing instructions, wherein the data to be computed (intermediate data which is correspondingly obtained and used for local model training and interacting with other participants after the participants perform preprocessing and data intersection on the original data of the federation learning task) is distributed to the proper target heterogeneous computing chip, so that the data types processed by the heterogeneous computing chip are highly uniform, the computing environment is pure (only high-speed operation is needed and logic judgment is not needed), and the data to be computed corresponding to the federation learning task is issued to the target heterogeneous computing chip in communication connection with the CPU end so as to be computed by the target heterogeneous computing chip, and the training efficiency of the federation learning task can be remarkably improved.
Example two
Further, based on the first embodiment of the present application, as shown in fig. 4, in this embodiment, the CPU side includes a processing layer, and the step of distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip communicatively connected to the CPU side according to the number of processes of the federal learning task, the number of threads that can be allocated in each process, and a data amount threshold in each process includes:
a1, distributing data to be calculated corresponding to the federation learning task to the processing layer according to the process number of the federation learning task, the allocable thread number in each process and the data quantity threshold value in each process;
in this embodiment, the data corresponding to the federal learning task is distributed to the processing layer according to the number of processes of the federal learning task in the configuration information, the number of threads that can be allocated in each process, and the data amount threshold in each process.
Step A2, analyzing the data to be calculated corresponding to the federal learning task based on the processing layer to obtain analysis data;
in this embodiment, as shown in fig. 5, the parsing processing of the data to be calculated corresponding to the federal learning task includes parsing the format of the data corresponding to the federal learning task, parsing the content, and further obtaining format parsing data and content parsing data.
A3, determining one or more of a calculation task function, a data characteristic and a parameter of the federal learning task based on the analysis data;
step A4, determining a target heterogeneous computing chip based on one or more of the computing task functions, the data features and the parameters;
in this embodiment, based on the content analysis data, one or more of a calculation task function, a data feature and a parameter of the federal learning task are determined, so as to determine a target heterogeneous calculation chip.
In this embodiment, the target heterogeneous computing chip may be plural.
And step A5, distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU end.
In this embodiment, the CPU-side processing layer issues data to the corresponding target heterogeneous computing chip through the PCIe interface by means of the issuing layer.
The application provides a heterogeneous test method, a heterogeneous test system, electronic equipment, a storage medium and a heterogeneous test product of a federal learning task, wherein the federal learning task is distributed to the processing layer corresponding to data to be calculated according to the number of processes of the federal learning task, the number of threads which can be distributed in each process and a data quantity threshold value in each process; based on the processing layer, analyzing the data to be calculated corresponding to the federal learning task to obtain analysis data; determining one or more of a computing task function, a data feature, and a parameter of the federal learning task based on the parsed data; determining a target heterogeneous computing chip based on one or more of the computing task functions, data features, and parameters; and distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU. In the embodiment, the target heterogeneous computing chip is accurately determined based on the processing layer, so that a foundation is laid for improving the testing efficiency of the federal learning task.
Example III
Further, based on the first embodiment and the second embodiment in the present application, another embodiment of the present application is provided, where the step of distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip communicatively connected to the CPU side includes:
step B1, determining an initial format of data to be calculated corresponding to the federation learning task, and determining a target format corresponding to and matched with the target heterogeneous computing chip;
step B2, if the initial format is inconsistent with the target format, performing format conversion processing on the data to be calculated corresponding to the federal learning task based on the target format to obtain converted data;
and step B3, distributing the converted data to a corresponding target heterogeneous computing chip in communication connection with the CPU.
In this embodiment, if it is determined in the processing layer that the initial format of the data corresponding to the federal learning task is inconsistent with the target format, format conversion processing is performed on the data corresponding to the federal learning task to be calculated based on the target format, so as to obtain converted data.
In this embodiment, determining an initial format of data to be calculated corresponding to the federal learning task, and determining a target format corresponding to and matched with the target heterogeneous computing chip; if the initial format is inconsistent with the target format, performing format conversion processing on the data to be calculated corresponding to the federal learning task based on the target format to obtain converted data; and distributing the conversion data to a corresponding target heterogeneous computing chip in communication connection with the CPU, wherein in the embodiment, the processing efficiency of the computing task is improved.
Example IV
Further, based on the first, second, and third embodiments in the present application, another embodiment of the present application is provided, in which the federal learning task is a model training task of longitudinal federal learning logistic regression;
the configuration information comprises the data size, the data bit width and the algorithm type to be tested of the federal learning task of the data to be calculated, wherein the algorithm type to be tested is Paillier decryption operation type;
the data to be calculated is ciphertext data which is correspondingly obtained and used for local model training and interaction with other participants after preprocessing, data intersection and data encryption processing are carried out on the original data;
The first calculation result is a calculation result obtained after the target heterogeneous calculation chip carries out decryption calculation on the data to be calculated.
In this embodiment, specifically, taking the federal learning task as an example of a model training task of longitudinal federal learning logistic regression, the overall description will be given:
1. before training, the participant CPU executes a model training task of longitudinal federal learning logistic regression, and first, relevant parameters (configuration information) used in a model training process are configured, where the relevant parameters may be a storage location of original data (local data) used in the model training process, a size of a corresponding data volume (10 w×80, which may be a maximum data volume), operations related to interaction with a heterogeneous computing chip, such as Paillier encryption, paillier decryption, dense state addition, matrix multiplication, and the like (types of algorithms to be tested of the federal learning task are Paillier encryption, paillier decryption, dense state addition, matrix multiplication, and the like), and a key bit width requirement (which may be 2048 bits).
2. After relevant parameters used in the model training process are configured, a CPU (Central processing Unit) end (federal learning task layer) starts the model training task, specifically, the CPU end performs preprocessing and data intersection on original data, then performs encryption on the preprocessed and data intersection data to obtain ciphertext data, performs other series of operations on the ciphertext data, and then issues the ciphertext data to a target heterogeneous computing chip through a processing layer for the target heterogeneous computing chip to execute Pailier decryption operation.
3. Specifically, the processing layer receives ciphertext data, firstly converts the ciphertext data (python language data format) into a data format processed by a C language, then selects a corresponding target heterogeneous computing chip according to factors such as configuration information (factors such as decryption operator mode_mode, data size batch_size, data bit width n_length and the like issued by a computing task), then converts the related data format into a data format suitable for the heterogeneous computing chip, and finally issues data to the corresponding target heterogeneous computing chip (memory) through a PCIe interface by means of the issuing layer.
4. And the target heterogeneous computing chip reads the ciphertext data after format conversion from the memory of the target heterogeneous computing chip after receiving the ciphertext data after format conversion sent by PCIe, then executes Paillier decryption operation in an efficient parallel mode, stores a first computing result in the heterogeneous computing chip in time after computation is completed, and reads the first computing result back through a PCIe bus when the processing layer detects that the computation of the target heterogeneous computing chip is completed.
5. After receiving the returned first calculation result, the CPU terminal processing layer performs format combination on the received first calculation result to obtain a first calculation result in a python language data format, and finally returns the first calculation result to the federal learning task layer.
6. The federal learning task layer obtains a first calculation result of the round of decryption operators, if the configuration information sets the CPU end to compare with the result of the target heterogeneous calculation chip, the CPU end Paillier decryption operation is waited to be completed, a second calculation result is obtained, and then comparison and verification of result data are automatically carried out to determine the calculation effect of the target heterogeneous calculation chip.
Example five
Referring to fig. 3, fig. 3 is a schematic structural diagram of a device, particularly an electronic device, in a hardware running environment according to an embodiment of the present application.
As shown in fig. 3, the electronic device may be an electronic device dedicated to implementing the heterogeneous test method of the federal learning task, or may be an integrated system device using the electronic device as a module. The electronic device may include: a processor 1001, such as a CPU, memory 1005, and a communication bus 1002. Wherein a communication bus 1002 is used to enable connected communication between the processor 1001 and a memory 1005. The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above.
Optionally, the electronic device may also include a rectangular user interface, a network interface, a camera, RF (Radio Frequency) circuitry, sensors, audio circuitry, wiFi modules, and the like. The rectangular user interface may include a Display screen (Display), an input sub-module such as a Keyboard (Keyboard), and the optional rectangular user interface may also include a standard wired interface, a wireless interface. The network interface may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface).
Those skilled in the art will appreciate that the electronic device structure shown in fig. 3 is not limiting of the electronic device and may include more or fewer components than shown, or may combine certain components, or may be arranged in different components.
As shown in fig. 3, a heterogeneous test program of an operating system, a network communication module, and a federal learning task may be included in the memory 1005 as one type of storage medium. An operating system is a program that manages and controls the hardware and software resources of an electronic device, heterogeneous test programs that support federal learning tasks, and the execution of other software and/or programs. The network communication module is used to enable communication between components within the memory 1005 and with other hardware and software in the heterogeneous test system for federal learning tasks.
In the electronic device shown in fig. 3, the processor 1001 is configured to execute a heterogeneous test program of a federal learning task stored in the memory 1005, to implement the steps of the heterogeneous test method of a federal learning task described in any one of the above.
The specific implementation manner of the electronic device is basically the same as each embodiment of the heterogeneous test method of the federal learning task, and is not repeated here.
Example six
The application also provides a heterogeneous testing device of federal learning task, is applied to the CPU end of federal learning participant, heterogeneous testing device of federal learning task includes:
the first determining module is used for determining configuration information corresponding to heterogeneous processing instructions when heterogeneous testing instructions of the federal learning task are detected;
the issuing module is used for issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU according to the configuration information, wherein the data to be calculated is intermediate data which is obtained correspondingly after preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants;
The receiving module is used for receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result.
The specific implementation manner and the beneficial effects of the heterogeneous test device for the federal learning task are basically the same as those of each embodiment of the heterogeneous test method for the federal learning task, and are not repeated here.
Example seven
The embodiment of the application provides a storage medium, and the storage medium stores one or more programs, and the one or more programs can be further executed by one or more processors to realize the steps of the heterogeneous test method of the federal learning task.
The storage medium and the specific implementation of the beneficial effects are basically the same as the above embodiments of the heterogeneous test method of the federal learning task, and are not described herein again.
Example eight
The present application also provides a computer program product comprising a computer program which, when executed by a processor, performs the steps of the heterogeneous test method of federal learning tasks described above.
The specific implementation manner and beneficial effects of the computer program product are substantially the same as those of the above-mentioned heterogeneous test method embodiments of the federal learning task, and are not repeated here.
Example nine
The application also provides a heterogeneous test system of federal learning tasks, the heterogeneous test system of federal learning tasks comprising: the system comprises a CPU end and a target heterogeneous computing chip, wherein the CPU end comprises a federal learning task layer, a processing layer and a issuing layer;
when detecting heterogeneous test instructions of the federal learning task, the federal learning task layer acquires data corresponding to the federal learning task and sends the data corresponding to the federal learning task to be calculated to a processing layer;
the processing layer acquires configuration information corresponding to the heterogeneous processing instruction, determines a target heterogeneous computing chip based on the configuration information, and sends data to be computed corresponding to the federal learning task to a transmitting layer after determining the target heterogeneous computing chip;
the issuing layer issues data to be calculated corresponding to the federal learning task to the target heterogeneous computing chip;
and the target heterogeneous computing chip computes the federal learning task to obtain a first computing result.
The specific implementation manner and the beneficial effects of the heterogeneous test system of the federal learning task are basically the same as those of each embodiment of the heterogeneous test method of the federal learning task, and are not repeated here.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (12)

1. The heterogeneous test method of the federal learning task is characterized by being applied to a CPU end of a federal learning participant, and comprises the following steps of:
when detecting heterogeneous test instructions of a federal learning task, determining configuration information corresponding to the heterogeneous processing instructions;
according to the configuration information, issuing data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU, wherein the data to be calculated is intermediate data which is obtained by preprocessing the original data of the federal learning task and performing data intersection and is used for local model training and interaction with other participants;
and receiving a first calculation result obtained after the target heterogeneous calculation chip calculates the data to be calculated, so as to execute the post-processing flow of the federal learning task based on the first calculation result.
2. The heterogeneous test method for a federal learning task according to claim 1, wherein the step of determining configuration information corresponding to the heterogeneous processing instruction when the heterogeneous test instruction for the federal learning task is detected comprises:
the heterogeneous test instruction of the federal learning task is triggered under the condition of meeting the preset acceleration processing data;
when detecting heterogeneous test instructions of the federal learning task, extracting associated parameters from the heterogeneous processing instructions, wherein the associated parameters comprise at least one of data bit width, algorithm types to be tested of the federal learning task and test scale of the federal learning task;
and determining configuration information corresponding to the heterogeneous processing instruction according to the association parameter.
3. The heterogeneous test method of federal learning task according to claim 1, wherein the step of issuing the data to be calculated corresponding to the federal learning task to a target heterogeneous computing chip in communication connection with the CPU terminal according to the configuration information includes:
determining the process number of the federal learning task, the allocable thread number in each process and a data quantity threshold value in each process according to the configuration information;
And distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU end according to the number of processes of the federal learning task, the number of distributable threads in each process and the data quantity threshold in each process.
4. The heterogeneous test method of federal learning tasks according to claim 3, wherein the CPU side includes a processing layer, and the step of distributing data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip communicatively connected to the CPU side according to the number of processes of the federal learning task, the number of threads assignable in each process, and a data amount threshold in each process includes:
distributing data to be calculated corresponding to the federal learning task to the processing layer according to the number of processes of the federal learning task, the number of threads which can be distributed in each process and a data quantity threshold value in each process;
based on the processing layer, analyzing the data to be calculated corresponding to the federal learning task to obtain analysis data;
determining one or more of a computing task function, a data feature, and a parameter of the federal learning task based on the parsed data;
Determining a target heterogeneous computing chip based on one or more of the computing task functions, data features, and parameters;
and distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip in communication connection with the CPU.
5. The heterogeneous testing method of federal learning task according to claim 4, wherein the step of distributing the data to be calculated corresponding to the federal learning task to a corresponding target heterogeneous computing chip communicatively connected to the CPU side includes:
determining an initial format of data to be calculated corresponding to the federation learning task, and determining a target format corresponding to and matched with the target heterogeneous computing chip;
if the initial format is inconsistent with the target format, performing format conversion processing on the data to be calculated corresponding to the federal learning task based on the target format to obtain converted data;
and distributing the converted data to a corresponding target heterogeneous computing chip in communication connection with the CPU.
6. The heterogeneous test method of federal learning task according to claim 1, wherein after the step of receiving the first calculation result obtained by the target heterogeneous calculation chip after calculating the data to be calculated, the method comprises:
Obtaining a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task;
and determining heterogeneous test effects of the federal learning task based on the first calculation result and the second calculation result.
7. The heterogeneous test method of federal learning task according to claim 6, wherein the configuration information includes comparison information for comparing a local calculation result with a heterogeneous chip calculation result, and the step of obtaining a second calculation result of the federal learning task obtained after the local calculation of the data to be calculated includes:
and if the configuration information comprises the comparison information, executing a step of obtaining a second calculation result obtained after the local calculation of the data to be calculated corresponding to the federal learning task.
8. The heterogeneous testing method of federal learning tasks of any of claims 1-7, wherein the federal learning task is a model training task of longitudinal federal learning logistic regression;
the configuration information comprises the data size, the data bit width and the algorithm type to be tested of the federal learning task of the data to be calculated, wherein the algorithm type to be tested is Paillier decryption operation type;
The data to be calculated is ciphertext data which is correspondingly obtained and used for local model training and interaction with other participants after preprocessing, data intersection and data encryption processing are carried out on the original data;
the first calculation result is a calculation result obtained after the target heterogeneous calculation chip carries out decryption calculation on the data to be calculated.
9. A heterogeneous test system of federal learning tasks, the heterogeneous test system of federal learning tasks comprising: the system comprises a CPU end and a target heterogeneous computing chip, wherein the CPU end comprises a federal learning task layer, a processing layer and a issuing layer;
when detecting heterogeneous test instructions of the federal learning task, the federal learning task layer acquires data corresponding to the federal learning task and sends the data corresponding to the federal learning task to be calculated to a processing layer;
the processing layer acquires configuration information corresponding to the heterogeneous processing instruction, wherein the configuration information comprises comparison information which needs to be compared between a local calculation result and a heterogeneous chip calculation result, a target heterogeneous calculation chip is determined based on the configuration information, and after the target heterogeneous calculation chip is determined, data corresponding to the federal learning task to be calculated is sent to a sending layer;
The issuing layer issues data to be calculated corresponding to the federal learning task to the target heterogeneous computing chip;
the target heterogeneous computing chip calculates the federal learning task to obtain a first computing result, and sends the first computing result to the federal learning task layer through the issuing layer and the processing layer;
and the federal learning task layer calculates the data to be calculated according to the comparison information to obtain a second calculation result, compares the first calculation result with the second calculation result to determine the calculation effect of the target heterogeneous calculation chip, and executes the post-processing flow of the federal learning task based on the first calculation result.
10. An apparatus, wherein the apparatus is an electronic apparatus, the electronic apparatus comprising: a memory, a processor, and a program stored on the memory for implementing a heterogeneous test method of the federal learning task,
the memory is used for storing programs of heterogeneous test methods for realizing federal learning tasks;
the processor is configured to execute a program for implementing the heterogeneous test method of federal learning tasks to implement the steps of the heterogeneous test method of federal learning tasks according to any one of claims 1 to 8.
11. A storage medium having stored thereon a program for implementing a heterogeneous test method of a federal learning task, the program for implementing the heterogeneous test method of a federal learning task being executed by a processor to implement the steps of the heterogeneous test method of a federal learning task according to any one of claims 1 to 8.
12. An article of manufacture which is a computer program product comprising a computer program which, when executed by a processor, performs the steps of the heterogeneous test method of federal learning tasks according to any one of claims 1 to 8.
CN202111515773.XA 2021-12-10 2021-12-10 Heterogeneous test method, heterogeneous test system, heterogeneous test equipment and heterogeneous test storage medium for federal learning task Pending CN116257427A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117555695A (en) * 2024-01-10 2024-02-13 深圳本贸科技股份有限公司 Optimization method and system for realizing heterogeneous computation based on parallel computation
CN117892355A (en) * 2024-03-14 2024-04-16 蓝象智联(杭州)科技有限公司 Multiparty data joint analysis method and system based on privacy protection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117555695A (en) * 2024-01-10 2024-02-13 深圳本贸科技股份有限公司 Optimization method and system for realizing heterogeneous computation based on parallel computation
CN117555695B (en) * 2024-01-10 2024-05-14 深圳本贸科技股份有限公司 Optimization method and system for realizing heterogeneous computation based on parallel computation
CN117892355A (en) * 2024-03-14 2024-04-16 蓝象智联(杭州)科技有限公司 Multiparty data joint analysis method and system based on privacy protection
CN117892355B (en) * 2024-03-14 2024-05-24 蓝象智联(杭州)科技有限公司 Multiparty data joint analysis method and system based on privacy protection

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